Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d), However, none of the certified copies of the priority documents have been received.
Claims 1-16 are pending in the application.
Election/Restrictions
Applicant’s election without traverse of Species 2 (claims 9-16) is acknowledged.
Therefore, claims 1-8 are withdrawn from further consideration.
Since the applicant makes an election without traverse of Species 2 (claims 9-16). Therefore, the arguments is not needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al. (US 20200381055 A1).
Regarding claim 9: Ko discloses a semiconductor device (100, FIG. 1), comprising: a voltage generation circuit (voltage generator 150, FIG. 1) configured to provide bias voltages to both ends (program operations inherently utilize bias voltages to both ends or any one end of a memory cell) of a memory cell (memory cells of memory cell array 110, FIG. 1) or to block the provision of the bias voltages in response to a voltage control signal in a write operation; a sensing circuit (sensing circuit 160, FIG. 1) configured to generate a sensing result signal (pass/fail signal, FIG. 1) by sensing a voltage level (sensing voltage VPB) of any one of the both ends of the memory cell in the write operation (during write operations, par. 58); and a control circuit (control logic 140, FIG. 1) configured to generate the voltage control signal (response to control signal out from control logic 140, par. 61) by determining whether the memory cell is a failed memory cell or a normal memory cell (determines memory cell via fail bit/pass bit for failed/normal cells, par. 163) based on the sensing result signal.
Regarding claim 14: Ko discloses a semiconductor device (100, FIG. 1), comprising: a memory cell (memory cells of memory cell array 110, FIG. 1) that is connected between a bit line (BL, FIG. 1) and a word line (WL, FIG. 1); a voltage generation circuit (voltage generator 150, FIG. 1) configured to provide one of a positive bias voltage and a negative bias voltage (Vread, Vpass; either can be positive or negative) to the bit line (bit lines BL through read/write circuit 130, FIG. 1) and provide the other of the positive bias voltage and the negative bias voltage to the word line (through word lines WL, FIG. 1), or block the provision of the positive bias voltage and the negative bias voltage based on a voltage control signal in a write operation; a sensing circuit (sensing circuit 160, FIG. 1) configured to generate a sensing result signal (pass/fail signal, FIG. 1) by sensing a voltage level of the negative bias voltage (sensing voltage VPB) in the write operation (during write operations, par. 58); and a control circuit (control logic 140, FIG. 1) configured to generate the voltage control signal (response to control signal out from control logic 140, par. 61) based on the sensing result signal (sensing circuit 160 determines memory cell via fail bit/pass bit for failed/normal cells, par. 163) in the write operation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 20200381055 A1) in view of Em (US 20180061493 A1).
Regarding claim 10: Ko does not disclose the sensing circuit generates the sensing result signal by sensing a bias voltage having a lower voltage level, among the bias voltages that are provided to the both ends of the memory cell in the write operation.
Em does disclose a semiconductor memory apparatus (1), wherein the sensing circuit generates the sensing result signal (signal DET, FIG. 2) by sensing a bias voltage having a lower voltage level (detection circuit 230 detects a lower level voltage level through the memory cell, par. 24-26, FIG. 2), among the bias voltages that are provided to the both ends of the memory cell in the write operation (write operation, par. 25).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Ko with the configuration of Em to allow the sensing circuit to measure the lower level bias voltage across the memory cells.
Regarding claims 11 and 15: Ko does not disclose the sensing circuit is configured to: enable the sensing result signal when the bias voltage having the lower level is equal to or greater than a reference voltage; and disable the sensing result signal when the bias voltage having the lower level is less than the reference voltage.
Em does disclose a semiconductor memory apparatus (1), wherein the sensing circuit is configured to: enable the sensing result signal (signal DET) when the bias voltage having the lower level is equal to or greater (enable DET when the voltage level is greater than a reference value REF, par. 24) than a reference voltage; and disable the sensing result signal when the bias voltage having the lower level is less (not enable signal DET with the voltage level is smaller than reference value REF, par. 24) than the reference voltage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Ko with the configuration of Em to allow the sensing circuit to control the output based on the measured bias voltage against the predetermined reference voltage.
Allowable Subject Matter
Claims 12-13, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a control circuit that, after determining the memory cell to be normal or failed based on the sensing result signal, generate a voltage control signal that enables the operating bias voltages to the memory cell when the memory cell is determined to be normal and generate a voltage control signal that disables the operating bias voltages to the memory cell when the memory cell is determined to be failed as in claims 12 and 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827