DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on May 27, 2026.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 27, 2026 has been entered. Claim 20 has been canceled. Claims 1-4, 6-11 and 14-19 are pending in the current application. Claims 1-4, 6-11 and 14-19 are rejected herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (Hereinafter Muchherla, U.S. Publication No. 2022/0342813) in view of Yoo et al. (Hereinafter Yoo, U.S. Publication No. 2007/0081405) in view of Miyamoto et al. (Hereinafter Miyamoto, U.S. Publication No. 2015/0067415).
Regarding claim 1, Muchherla teaches:
A system comprising:
a memory device comprising a plurality of wordlines forming an array of memory cells (See memory devices 130 and 140 depicted in Figure 1. See Figure 3A, which depict wordlines 311-316 and wordlines 321-326. See Figure 3B, which depicts wordlines 331-336 and wordlines 341-346.); and
a processing device, coupled with the memory device, configured to perform operations (See [0032] “the memory devices 130 include local media controllers 135 that operate in conjunction with memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 130.” See [0033] “The memory sub-system 110 can include a highly read data manager 113 that can be used to relocate and/or store highly read data at low impact read disturb pages of memory device 130. In some embodiments, the memory sub-system controller 115 includes at least a portion of the highly read data manager 113. In some embodiments, the highly read data manager 113 is part of the host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of highly read data manager 113 and is configured to perform the functionality described herein.” The processing device may correspond to the highly read data manager 113, local media controller 135, memory sub-system controller 115, or any combination of the aforementioned elements.) comprising:
receiving data from a host system (See [0009] “The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.” See [0036] “highly read data manager 113 can be invoked in response to receiving a write request from a host system to write new data to memory devices 130, 140.” See [0056] “while FIGS. 3A-3B depict the relocation of data already programmed to a memory device, aspects of the present disclosure can be applied to programming new data on first instance based on a write request received from a host system”);
writing the data to a portion of the memory device configured as single-level cell (SLC) memory (See [0036] “highly read data manager 113 can be invoked in response to receiving a write request from a host system to write new data to memory devices 130, 140.” See [0025] “Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell.” See [0025] “each of the memory devices 130 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, PLCs or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells.” See Figure 3A, in which data 313-A is written to memory portion/block 310, which may be SLC memory. See Figure 3B, in which data 333-A is written to memory portion/block 330, which may be SLC memory.);
determining to move at least a subset of data stored in the SLC memory of the memory device to another portion of the memory device (See [0039] “At operation 210, the processing logic receives a request to perform a data relocation operation on a wordline for a memory device (e.g., memory device 130 in FIG. 1).” See [0051] “As shown in FIG. 3A, a highly read data manager can receive a request to perform a data relocation operation on wordlines of a source data block 310 of a memory device.” See Figure 3A, in which data 313-A is moved/relocated from memory block/portion 310 to memory block/portion 320. See Figure 3B, in which data 333-A is moved/relocated from memory block/portion 330 to memory block/portion 340.) configured as multiple-level cell (XLC) memory (See [0046] “At operation 240, the processing logic, responsive to determining that the data includes the characteristic that satisfies the threshold criterion (e.g., the data is highly read data), identifies one or more low read disturb pages of a target wordline for relocating the data. As noted above, a low read disturb page can be used for programming a most significant bit of a memory cell. In MLC implementations, processing logic can identify one or more upper pages of the MLC memory cell”), the subset of data being associated with a first wordline of the plurality of wordlines (See [0039] “At operation 210, the processing logic receives a request to perform a data relocation operation on a wordline for a memory device (e.g., memory device 130 in FIG. 1).” See wordline 313 depicted in Figure 3A, which may correspond to the first wordline. See wordline 333 depicted in Figure 3B, which may correspond to the first wordline.);
obtaining information associated with a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline (See Figure 3A, in which information associated with second wordline 312 or 314 indicates the second wordline 312 or 314 to have a high bit error rate. The second wordline 312 or 314 is adjacent to wordline 313. See Figure 3B, in which information associated with second wordline 332 or 334 indicates the second wordline 332 or 334 to have a high bit error rate. The second wordline 332 or 334 is adjacent to wordline 333.); and
performing a data migration operation, using the information associated with the second wordline, to move the subset of data from the SLC memory to the XLC memory (See Figure 3A, in which information associated with second wordline 312 or 314 indicates the second wordline 312 or 314 to have a high bit error rate. The second wordline 312 or 314 is adjacent to wordline 313. The high bit error rate information (high read disturb information) is used to migrate/relocate the data 313-A to memory block 320, which may comprise XLC memory. See Figure 3B, in which information associated with second wordline 332 or 334 indicates the second wordline 332 or 334 to have a high bit error rate. The second wordline 332 or 334 is adjacent to wordline 333. The high bit error rate information (high read disturb information) is used to migrate/relocate the data 333-A to memory block 340, which may comprise XLC memory. See [0044]-[0045]. See [0052] and [0055].), wherein the data migration operation is associated with a corrective program operation (See [0015] “the highly read data manager can store the highly read data on the pages having suffered the least amount of read disturb or a lower amount of read disturb than other pages (i.e., “low read disturb pages”) of the memory cells of the target wordlines to significantly reduce the impact of applying higher voltages to the unselected adjacent wordlines. In another embodiment, the highly read data manager can receive a request to write new data to the memory device, where the write request specifies that the data will be highly read. The highly read data manager can utilize a similar process for identifying low read disturb pages of target wordlines for writing the highly read data in order to reduce read disturb effects on the unselected adjacent wordlines.” See [0016], Figure 3A and Figure 3B, in which the program/relocation operation is performed to mitigate read disturb issues. Therefore, such program/relocation operations are considered a corrective operation. Furthermore, see [0030] and [0034], in which the corrective program operation may also refer to wear leveling operations, garbage collection operations, and/or error correction code operations.), and
Muchherla does not explicitly disclose what Yoo teaches:
wherein the information associated with the second wordline is stored in a … latch of the memory device (See [0111] “According to one aspect of the invention, instead of maintaining the state of the wordlines, the wordline (state) information is stored in a circuit as the wordlines are turned off and retrieved as the wordlines are turned back on again. According to one implementation, the wordline information is stored at the output of pre-decoders in the pre-decoding signal latches as shown in FIG. 9.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data relocation method of Muchherla with the wordline information storage method of Yoo to maintain important wordline information in the event the wordline is turned off, thus reducing the chances of loss of important wordline information. Furthermore, although Yoo does not explicitly disclose storing the information in a NAND latch, the combination of Muchherla and Yoo would teach the latch functions of the memory device as taught in Yoo, to be applied to the NAND memory device disclosed in Muchherla (See [0010] and [0024]-[0026] of Muchherla, which teaches the memory devices to be NAND memory devices). Therefore, the combination of Muchherla and Yoo would teach storing the information in a NAND latch of the memory device.
Muchherla and Yoo do not explicitly disclose what Miyamoto teaches:
wherein the information associated with the second wordline is stored … in the memory device in a corrective program mode of the memory device (See [0036] “In the case where the NAND 10 includes an error correction circuit, the error correction circuit in the NAND 10 stores the number of corrected bits for each physical page. The bit-error-rate manager 42 obtains the number of corrected bits stored in the error correction circuit, calculates the bit error rate from the number of corrected bits and the number of data bits, and saves the calculated bit error rate in the bit-error-rate management table 44.” See [0037] “In case of using the error correction circuit 35 disposed in the memory controller 3, the error correction circuit 35 notifies the bit-error-rate manager 42 of the number of corrected bits for each physical page. The bit-error-rate manager 42 calculates the bit error rate from the notified number of corrected bits, and saves the calculated bit error rate in the bit-error-rate management table 44.” See Figure 9, in which the bit error rate 44 is stored in the memory system in an error correction mode of the memory system.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data relocation method of Muchherla and the wordline information storage method of Yoo with the bit error management method of Miyamoto to minimize the variation in bit error rate among physical blocks in a range that ensures parallel accessibility (See [0055] of Miyamoto.).
Regarding claim 2, Muchherla teaches:
The system of claim 1, wherein the information associated with the second wordline indicates whether the second wordline is in a high state or a low state (See Figure 3A, in which information associated with second wordline 312 or 314 indicates the second wordline 312 or 314 to have a high bit error rate. See Figure 3B, in which information associated with second wordline 332 or 334 indicates the second wordline 332 or 334 to have a high bit error rate. See [0052] “the highly read data manager can determine whether data 313-A is highly read (e.g., “hot read”) based on the attributes of the adjacent wordlines (e.g., wordlines 312 and 314). As shown in FIG. 3A, the bit error rates associated with the memory cells of wordlines 312 and 314 indicate high bit error rates. The presence of high bit error rates can indicate that these wordlines are experiencing high levels of read disturb.” See [0055] “As shown in FIG. 3B, the highly read data manager can determine that the data 333-A stored at wordline 333 is highly read data based on determining that the adjacent wordlines 332 and 334 are affected by high levels of read disturb. As described above, this can be determined by determining bit error rates for the memory cells of wordlines 332 and 334. As shown, the bit error rates associated with the memory cells of these adjacent wordlines are high, indicating that data 333-A is highly read data.”).
Regarding claim 3, Muchherla teaches:
The system of claim 1, wherein the XLC memory is triple-level cell (TLC) memory (See [0025] “In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, PLCs or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells.” See [0034] “Memory devices 130, 140 can include multi-level memory cells.” See [0034] “Similarly, a memory device configured with triple-level cells (TLCs) can store three bits per cell.”).
Regarding claim 4, Muchherla teaches:
The system of claim 1, wherein obtaining the information associated with the second wordline comprises retrieving the information from one or more SLC source blocks of the SLC memory (See [0042] “At operation 230, the processing logic determines whether the data stored at the high read disturb pages of the source wordline includes data characteristic that satisfies a threshold criterion in relation to data stored on other wordlines in the source data block for the memory device.” See [0051] “As shown in FIG. 3A, a highly read data manager can receive a request to perform a data relocation operation on wordlines of a source data block 310 of a memory device.” See [0054] “FIG. 3B. illustrates relocating highly read data to low read disturb pages of multiple target wordlines. As shown, the highly read data manager can receive a request to perform a data relocation operation on wordlines of a source data block 330 of a memory device.” High bit error rate information is retrieved from source data block 310 and 330. See [0025] and [0036], in which the source data block may be SLC memory.).
Regarding claim 6, Muchherla teaches:
The system of claim 1, wherein the corrective program operation is based on a program erase cycle of the SLC memory of the memory device (See [0039] “At operation 210, the processing logic receives a request to perform a data relocation operation on a wordline for a memory device (e.g., memory device 130 in FIG. 1). In some implementations, the relocation operation can be part of a memory management operation, such as a garbage collection operation to relocate data from one data block stripe of the memory device to a new destination block stripe of that memory device. The request to perform the garbage collection operation, or other memory management operation, can be initiated responsive to determining that data consolidation is to be performed on a candidate data block to free up memory resources for subsequent program/erase cycles.” See [0025]-[0026], in which program operations (i.e. data relocation operations) for memory 130/140 involves program/erase operations.).
Regarding claim 7, Muchherla teaches:
The system of claim 1, wherein obtaining the information associated with the second wordline (See Figure 3A, in which information associated with second wordline 312 or 314 indicates the second wordline 312 or 314 to have a high bit error rate. The high bit error rate information (high read disturb information) is used/obtained to migrate/relocate the data 313-A to memory block 320. See Figure 3B, in which information associated with second wordline 332 or 334 indicates the second wordline 332 or 334 to have a high bit error rate. The high bit error rate information (high read disturb information) is used/obtained to migrate/relocate the data 333-A to memory block 340.) comprises extracting the information during an SLC-to-XLC folding operation (See [0051] “As shown in FIG. 3A, a highly read data manager can receive a request to perform a data relocation operation on wordlines of a source data block 310 of a memory device. As noted above, the request can be initiated in response to a garbage collection operation, a data folding operation, or the like.”).
Claim 8 is rejected for the same reasons as claim 1. Although claim 8 differs from claim 1 in that claim 8 teaches data to be stored in XLC memory and moved to another XLC memory portion, while claim 1 teaches data to be stored in SLC memory and moved to an XLC memory portion, the rejection of claim 1 shows that the prior art teaches the memory device(s) to consist of SLC memory portions and/or MLC memory portions, and combinations of the two, in view of the data relocation operations. For example, see [0025] and Figure 3A and Figure 3B of Muchherla. Thus, the prior art teaches data relocation from SLC to MLC and MLC to MLC. Furthermore, claim 8 has a step of “decoding, by a system controller, the information associated with the second wordline” which is not present in claim 1. Prior art Yoo teaches the decoding step in paragraph [0111], which is used in the rejection of claim 1. See [0111] of Yoo “According to one aspect of the invention, instead of maintaining the state of the wordlines, the wordline (state) information is stored in a circuit as the wordlines are turned off and retrieved as the wordlines are turned back on again. According to one implementation, the wordline information is stored at the output of pre-decoders in the pre-decoding signal latches as shown in FIG. 9.”). That is, paragraph [0111] prior art Yoo teaches the limitation(s) of claim 8 that recite “wherein obtaining the information associated with the second wordline comprises: decoding, by a system controller, the information associated with the second wordline; and storing, by the system controller in a latch of the memory device, the information associated with the second wordline”.
Claim 9 is rejected for the same reasons as claim 2. Claim 10 is rejected for the same reasons as claim 3.
Regarding claim 11, Muchherla teaches:
The system of claim 8, wherein the data migration operation is associated with a media scan operation or a garbage collection (See [0034] “highly read data manager 113 can receive a request to perform a data relocation operation on data stored on a source wordline of a data block for memory devices 130, 140. The relocation operation can be a garbage collection operation, a data folding operation, or the like.” See [0051] “As shown in FIG. 3A, a highly read data manager can receive a request to perform a data relocation operation on wordlines of a source data block 310 of a memory device. As noted above, the request can be initiated in response to a garbage collection operation, a data folding operation, or the like.”).
Regarding claim 14, Yoo teaches:
The system of claim 8, wherein obtaining the information associated with the second wordline comprises:
performing, by a memory device controller, an on-chip read to read the information associated with the second wordline (See [0111] “According to one aspect of the invention, instead of maintaining the state of the wordlines, the wordline (state) information is stored in a circuit as the wordlines are turned off and retrieved as the wordlines are turned back on again. According to one implementation, the wordline information is stored at the output of pre-decoders in the pre-decoding signal latches as shown in FIG. 9. When the chip exits ICC3P mode, the wordlines are re-activated using information stored at the output of pre-decoders” The stored wordline information is accessed/read to re-activate the wordline.).
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla in view of Yoo in view of Athreya et al. (Hereinafter Athreya, U.S. Publication No. 2020/0118636).
Regarding claim 15, Muchherla teaches:
A system comprising: a memory device comprising a plurality of wordlines forming an array of memory cells; and
a processing device, coupled with the memory device, configured to perform operations comprising:
receiving data from a host system;
determining to move at least a subset of data stored in the first memory portion of the memory device to a second memory portion of the memory device configured as multiple-level cell (XLC) memory, the subset of data being associated with a first wordline of the plurality of wordlines;
obtaining information associated with a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; and
performing a data migration operation, using the information associated with the second wordline, to move the subset of data from the first memory portion to the second memory portion, wherein the data migration operation is associated with a corrective program operation (See rejection of claim 1).
Muchherla does not explicitly disclose what Yoo teaches:
and wherein the information associated with the second wordline is stored in a latch of the memory device (See rejection of claim 1)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data relocation method of Muchherla with the wordline information storage method of Yoo to maintain important wordline information in the event the wordline is turned off, thus reducing the chances of loss of important wordline information.
Muchherla and Yoo do not explicitly disclose what Athreya teaches:
determining whether a single-level cell (SLC) cache of the memory device is full;
writing the data to a first memory portion of the memory device based on whether the SLC cache of the memory device is full (See [0026] “The “write around SLC buffer” approach involves writing to SLC buffer as long as space is available. Once SLC buffer is full, host data is written directly to a QLC block.”);
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data relocation method of Muchherla and the wordline information storage method of Yoo with the caching method of Athreya to improve performance and speed and decrease load times by implementing caching operations to store frequently accessed data closer to the user or application.
Claim 16 is rejected for the same reasons as claim 2.
Regarding claim 17, Athreya teaches:
The system of claim 15, wherein the first memory portion is SLC memory, and wherein writing the data to the first memory portion based on whether the SLC cache of the memory device is full comprises writing the data to the SLC memory based on the SLC cache of the memory device not being full (See [0026] “Both the write through and write around approaches involve writing host data to a frontend SLC buffer. The SLC buffer can include a dedicated SLC region, a dynamic region used in an SLC mode, or both. The “write through SLC buffer” approach includes writing all host data through an SLC buffer. Once the SLC buffer is full, space is made available in the SLC buffer by moving data to one or more QLC blocks. New host data can then be written to SLC buffer. The “write around SLC buffer” approach involves writing to SLC buffer as long as space is available” When the SLC buffer is not full, data is written to the dedicated SLC region or SLC dynamic region.).
Regarding claim 18, Athreya teaches:
The system of claim 15, wherein the first memory portion is other XLC memory, and wherein writing the data to the first memory portion based on whether the SLC cache of the memory device is full comprises writing the data to the other XLC memory based on the SLC cache of the memory device being full (See [0026] “Once SLC buffer is full, host data is written directly to a QLC block”.).
Claim 19 is rejected for the same reasons as claim 11.
Response to Arguments
Applicant's arguments filed May 27, 2026 have been fully considered but they are not persuasive. On page 9 of applicant’s arguments, applicant’s representative submitted that Yoo does not teach or suggest storing information in a “NAND latch”, as recited by amended claims 1 and 8. Although Yoo does not explicitly disclose storing the information in a NAND latch, the combination of Muchherla and Yoo would teach the latch functions of the memory device as taught in Yoo, to be applied to the NAND memory device disclosed in Muchherla (See [0010] and [0024]-[0026] of Muchherla, which teaches the memory devices to be NAND memory devices). Therefore, the combination of Muchherla and Yoo would teach storing the information in a NAND latch of the memory device.
On page 9 of applicant’s arguments, applicant submitted that Yoo does not teach or suggest storing the information “in a corrective program mode of the memory device,” as recited by amended claims 1 and 8. Examiner submits that newly found prior art Miyamoto has been used to teach the amended limitations herein (See rejection of claim 1.), as opposed to prior art Yoo. All pending claims remain rejected herein.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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