DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/19/2026 has been entered.
Response to Amendment
The amendments filed 5/19/2026 have been accepted. Claims 1-15, 17, 18, and 20-24 are still pending. Claims 1-5, 7, 8, 11-15, 17, 18, and 21-23 are amended. Claim 24 is new. Claim 19 has been canceled. Applicant’s amendments to the claims have overcome each and every 102 and 103 rejections previously set forth in the Non-Final Office Action mailed 3/26/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15, 17, 18, and 20-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The independent claims contain the term “a cursor” which renders the claims indefinite as it is unclear as to what is meant by a block having “a cursor on” it. The term “cursor” appears to be a term only used by the applicant and only in their patent applications. The term also is appears to be used somewhat inconsistently across applications and the present application does not explicitly define the term (it is only used once).
In Cariello (US PGPub 2021/0048952) a cursor refers to a pointer (Cariello, Paragraph [0041]). In Vaghasiya et al. (US PGPub 2024/0054037, hereafter referred to as Vaghasiya) a cursor appears to be referred to as some kind of partition or zone (Vaghasiya, Paragraph [0038] and [0047], pointers are not something that are “opened” or that you store data in). Given this, and the fact that the present application only mentions cursors once in a sentence that contains the same subject matter that is now presented in the claims and nothing else, it makes it unclear as to what exactly is meant by the term cursor and what a block with a cursor “on it” means. For examination purposes, the limitations will be construed to mean that a pointer (cursor) is pointing to the particular block to be written to.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 9-11, 15, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Erez et al. (US PGPub 2024/0078015, hereafter referred to as Erez) in view of Cariello (US PGPub 2021/0048952).
Regarding claim 1, Erez teaches a method by a memory system, comprising: determining whether one or more operating parameters of the memory system satisfy one or more thresholds (Paragraphs [0032]-[0033], states the host can plan for large writes meaning the data to be written would have to be satisfy a certain threshold to qualify), and writing data via one or more single-level cell word lines of the memory system and one or more multiple level cell word lines of the memory system based at least in part on a ratio of writing information via single-level cell word lines to writing information via multiple level cell word lines (Paragraphs [0032]-[0033], states that a ratio of what type of memory (SLC, TLC, or QLC) the data for the large write can be calculated based on the incoming write and the available space in each type of memory. Paragraphs [0032]-[0033], states once the ratio of which memory types to write to is determined the system will write the data to the respective memories), the ratio being based at least in part on the one or more operating parameters and the one or more thresholds (Paragraphs [0032]-[0033], as stated previously, the host can plan for large writes meaning the data to be written would have to be satisfy a certain threshold to qualify and the amount of free space available for each type of memory can be used in the calculation of the ratio. This means the ratio would be based at least in part on the one or more operating parameters and thresholds). Erez does not teach wherein writing the data comprises performing a combination of writing via single-level cell word lines and writing via multiple level cell word lines based at least in part on the memory system having a cursor on a block of single-level cells and on a block of multiple level cells.
Cariello teaches wherein writing the data comprises performing a combination of writing based at least in part on the memory system having a cursor on two different blocks of memory cells (Paragraph [0041], states that cursors exist for both SLC and MLC blocks. Paragraph [0043] states that these cursors point to different cells of a write buffer). Since both Eres and Cariello teach writing data to storage it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Eres to use cursors to determine where to write data as taught in Cariello to obtain the predictable result of wherein writing the data comprises performing a combination of writing via single-level cell word lines and writing via multiple level cell word lines based at least in part on the memory system having a cursor on a block of single-level cells and on a block of multiple level cells.
Regarding claim 5, Eres and Cariello teach all the limitations to claim 1. Eres further teaches wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether an amount of free space in a memory drive of the memory system satisfies a free space threshold, wherein the one or more operating parameters comprise the amount of free space and the one or more thresholds comprise the free space threshold (Paragraphs [0032]-[0033], the amount of free space available for each type of memory can be used in the calculation of the ratio). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 6, Eres and Cariello teach all the limitations to claim 1. Eres further teaches wherein the one or more operating parameters comprise a quantity of commands in a command queue, a size of one or more commands in the command queue, a host delay, an amount of free space in a memory drive of the memory system, or any combination thereof (Paragraphs [0032]-[0033], as stated in the rejection to claim 5). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 9, Eres and Cariello teach all the limitations to claim 1. Eres further teaches wherein the ratio comprises an integer value, a percentage, or a decimal value (Paragraph [0033] and [0039], states the ratio can be represented by integer values). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 10, Eres and Cariello teach all the limitations to claim 1. Eres further teaches wherein the multiple level cell word lines comprise tri-level cell (TLC) word lines or quad-level cell (QLC) word lines (Paragraphs [0032]-[0033], the memory can be TLC or MLC). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 11, 15, and 20, claims are the computer readable medium claims associated with claims 1, 5, 6, and 10. Since Eres and Cariello teach all the limitations to claims 1, 5, 6, and 10, it also teaches all the limitations to claims 11, 15, and 20; therefore the rejections to claims 1, 5, 6, and 10 also apply to claims 11, 15, and 20.
Regarding claim 21, claim 21 is the system claim associated with claim 1. Since Erez and Cariello teach all the limitations to claim 1 and Erez further teaches one or more memory devices and processing circuitry coupled with the one or more memory devices (Fig. 1, shows the controller and flash memory devices), they also teach all the limitations to claim 21; therefore the rejection to claim 1 also applies to claim 21.
Claims 2, 12, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Erez and Cariello in further view of Tan et al. (US PGPub 2023/0107227, hereafter referred to as Tan).
Regarding claim 2, Erez and Cariello teach all the limitations of claim 1. Erez and Cariello do not teach wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a size of one or more commands in a command queue satisfies a command size threshold, wherein the one or more operating parameters comprise the size of the one or more commands and the one or more thresholds comprise the command size threshold.
Tan teaches wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a size of one or more commands in a command queue satisfies a command size threshold, wherein the one or more operating parameters comprise the size of the one or more commands and the one or more thresholds comprise the command size threshold (Paragraph [0070], states that the size of a write can be used to determine whether the write command is written to an SLC or TLC block). Since both Erez/Cariello and Tan teach the use of operating parameters to determine where to direct write operations it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Erez and Cariello to use the parameters as taught in Tan to obtain the predictable result of wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a size of one or more commands in a command queue satisfies a command size threshold, wherein the one or more operating parameters comprise the size of the one or more commands and the one or more thresholds comprise the command size threshold.
Regarding claim 12, claim 12 is the computer readable medium claim associated with claim 2. Since Erez, Cariello, and Tan teach all the limitations to claim 2, they also teach all the limitations to claim 12; therefore the rejection to claim 2 also applies to claim 12.
Regarding claim 22, claim 22 is the system claim associated with claim 2. Since Erez, Cariello, and Tan teach all the limitations to claim 2 and Erez further teaches one or more memory devices and processing circuitry coupled with the one or more memory devices (Fig. 1, shows the controller and flash memory devices), they also teach all the limitations to claim 22; therefore the rejection to claim 2 also applies to claim 22.
Claims 3, 13, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Erez and Cariello in further view of Bi (US PGPub 2022/0404976).
Regarding claim 3, Erez and Cariello teach all the limitations of claim 1. Erez and Cariello do not teach wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a quantity of commands in a command queue satisfies a queue threshold, wherein the one or more operating parameters comprise the quantity of commands and the one or more thresholds comprise the queue threshold.
Bi teaches wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a quantity of commands in a command queue satisfies a queue threshold, wherein the one or more operating parameters comprise the quantity of commands and the one or more thresholds comprise the queue threshold (Paragraphs [0012]-[0013], states that the number of commands in the command queue (queue depth) can be used to determine the operating mode of the memory (what type of cell to use)). Since both Erez/Cariello and Bi teach the use of operating parameters to determine where to direct write operations it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Erez and Cariello to use the parameters as taught in Bi to obtain the predictable result of wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a quantity of commands in a command queue satisfies a queue threshold, wherein the one or more operating parameters comprise the quantity of commands and the one or more thresholds comprise the queue threshold.
Regarding claim 13, claim 13 is the computer readable medium claim associated with claim 3. Since Erez, Cariello, and Bi teach all the limitations to claim 3, they also teach all the limitations to claim 13; therefore the rejection to claim 3 also applies to claim 13.
Regarding claim 23, Erez and Cariello teach all the limitations of claim 1. Erez and Cariello do not teach wherein the one or more operating parameters comprise: a quantity of commands in a command queue, wherein an increase in the quantity of commands in the command queue is associated with an increase in the ratio, a size of one or more commands in the command queue, wherein an increase in the size of the one or more commands is associated with an increase in the ratio, or a host delay, wherein an increase in the host delay is associated with a reduction of the ratio.
Bi teaches wherein the one or more operating parameters comprise: a quantity of commands in a command queue, wherein an increase in the quantity of commands in the command queue is associated with an increase in the ratio, a size of one or more commands in the command queue, wherein an increase in the size of the one or more commands is associated with an increase in the ratio, or a host delay, wherein an increase in the host delay is associated with a reduction of the ratio (Paragraphs [0012]-[0013], states that the number of commands in the command queue can change which type of block (and thus the ratio) to write to). Since both Erez/Cariello and Bi teach the use of operating parameters to determine where to direct write operations it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Erez and Cariello to use the parameters as taught in Bi to obtain the predictable result of wherein the one or more operating parameters comprise: a quantity of commands in a command queue, wherein an increase in the quantity of commands in the command queue is associated with an increase in the ratio, a size of one or more commands in the command queue, wherein an increase in the size of the one or more commands is associated with an increase in the ratio, or a host delay, wherein an increase in the host delay is associated with a reduction of the ratio.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Erez and Cariello in further view of Bensity et al. (US PGPub 2018/0275872, hereafter referred to as Bensity).
Regarding claim 4, Erez and Cariello teach all the limitations of claim 1. Erez and Cariello do not teach wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a host delay satisfies a host delay threshold, wherein the one or more operating parameters comprise the host delay and the one or more thresholds comprise the host delay threshold.
Bensity teaches wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a host delay satisfies a host delay threshold, wherein the one or more operating parameters comprise the host delay and the one or more thresholds comprise the host delay threshold (Paragraphs [0029] and [0095], states that host latency (delay) can be used as a parameter to determine when to post an interrupt meaning the latency would have to satisfy a threshold of some kind for the interrupt to trigger). Since both Erez/Cariello and Bensity teach the use of operating parameters it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Erez and Cariello to use the parameters presented in Bensity to obtain the predictable result of wherein determining whether the one or more operating parameters satisfy the one or more thresholds comprises: determining whether a host delay satisfies a host delay threshold, wherein the one or more operating parameters comprise the host delay and the one or more thresholds comprise the host delay threshold.
Regarding claim 14, claim 14 is the computer readable medium claim associated with claim 4. Since Erez, Cariello, and Bensity teach all the limitations to claim 4, they also teach all the limitations to claim 14; therefore the rejection to claim 4 also applies to claim 14.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Erez and Cariello in further view of Korean Patent KR 102434989 (hereafter referred to as KR Pat).
Regarding claim 7, Erez and Cariello teach all the limitations of claim 1. Erez and Cariello do not teach wherein the ratio is based at least in part on: identifying, based at least in part on the one or more operating parameters, an index in a mode register, wherein the index indicates the ratio corresponding to one or more ranges of operating parameters comprising the one or more operating parameters.
KR Pat teaches wherein determining the ratio is based at least in part on: identifying, based at least in part on the one or more operating parameters, an index in a mode register, wherein the index indicates the ratio corresponding to one or more ranges of operating parameters comprising the one or more operating parameters (pg. 12, Paragraph [0006], states a mode register with an index may be used to set the division ratio). Since both Erez/Cariello and KR Pat teach determining a ratio it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the method of determining the ratio of Erez and Cariello with that of KR Pat to obtain the predictable result of wherein the ratio is based at least in part on: identifying, based at least in part on the one or more operating parameters, an index in a mode register, wherein the index indicates the ratio corresponding to one or more ranges of operating parameters comprising the one or more operating parameters.
Regarding claim 17, claim 17 is the computer readable medium claim associated with claim 7. Since Erez, Cariello, and KR Pat teach all the limitations to claim 7, they also teach all the limitations to claim 17; therefore the rejection to claim 7 also applies to claim 17.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Erez and Cariello in further view of Hyun et al. (US PGPub 2016/0210050, hereafter referred to as Hyun).
Regarding claim 8, Erez and Cariello teaches all the limitations of claim 1. Erez and Cariello do not teach wherein the ratio is based at least in part on: determining the ratio in accordance with an algorithm, the algorithm comprising a weighted average of the one or more operating parameters.
Hyun teaches wherein determining the ratio is based at least in part on: determining the ratio in accordance with an algorithm, the algorithm comprising a weighted average of the one or more operating parameters (Paragraph [0087], [0126], and [0129], states that the ratio can be determined using a weighted average). Since both Erez/Cariello and Hyun teach determining a ratio it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the method of determining the ratio of Erez and Cariello with that of Hyun to obtain the predictable result of wherein the ratio is based at least in part on: determining the ratio in accordance with an algorithm, the algorithm comprising a weighted average of the one or more operating parameters.
Regarding claim 18, claim 18 is the computer readable medium claim associated with claim 8. Since Erez, Cariello, and Hyun teach all the limitations to claim 8, they also teach all the limitations to claim 18; therefore the rejection to claim 8 also applies to claim 18.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Eres and Cariello as applied to claim 1 above, and further in view of Jung et al. (US PGPub 2018/0081594, hereafter referred to as Jung).
Regarding claim 24, Erez and Cariello teaches all the limitations of claim 1. Erez and Cariello do not teach wherein writing the data comprises writing the data in an alternating fashion between one single-level cell word line and one multiple level cell word line.
Jung teaches wherein writing the data comprises writing the data in an alternating fashion between one single-level cell word line and one multiple level cell word line (Paragraph [0062], describes the process of receiving a mixed write operation that will write to an SLC region followed by an MLC region). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Eres and Cariello to utilize the alternating method of writing as taught in Jung so to provide a desired performance, buffer size, and lifetime, and the write data is written to the SLC region and the TLC region that are mixed at the adjusted write ratio (Jung, Paragraph [0048]).
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the applicant amended the claims with the limitation “wherein writing the data comprises performing a combination of writing via single-level cell word lines and writing via multiple level cell word lines based at least in part on the memory system having a cursor on a block of single-level cells and on a block of multiple level cells” to overcome the prior rejections set forth in the Final Rejection mailed 3/26/2026. To address this, new reference Cariello has been incorporated into the rejection to help teach the amended limitations.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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