DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The following Double Patenting rejection was originally presented in the Non-Final Rejection mailed 9/24/2025, and although the Applicant has amended the claims, the Double Patenting rejection has been maintained.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-4, 6-8, 10-12 and 18 of U.S. Patent No. 11,016,890. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims recite additional details not recited in the instant claims.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-4, 6, 11-12 and 14 of U.S. Patent No. 12,061,544. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims recite additional details not recited in the instant claims.
With regard to instant application, please refer to the tables below, which illustrates the anticipatory relationship of the claims at issue:
Instant Application 18/787,967
US Patent 11,016,890
Claims 1-2, 4, 7
Claims 1+11
Claims 3
Claim 18
Claim 5
Claim 12
Claim 6
Claim 10
Claims 8-9, 11
Claims 1+6
Claim 10
Claim 11
Claim 12
Claim 4
Claim 13
Claim 2
Claim 14
Claim 3
Claim 15-16, 18
Claim 1
Claim 19
Claim 7
Claim 20
Claim 8
Instant Application 18/787,967
US Patent 12,061,544
Claims 1-2, 4
Claims 1+11
Claims 3, 6
Claim 14
Claim 5
Claim 2
Claim 7
Claim 12
Claims 8-9, 11
Claims 1+6+12
Claim 10
Claim 11
Claim 12-13
Claim 3
Claim 14
Claim 4
Claim 15-17, 19
Claim 12
Claim 18
Claim 1
Response to Amendment
With respect to Applicant’s amendment to Claim 7 in regards to 35 U.S.C. 112, rejection with respect to the same has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nachimuthu et al. (US PGPUB 2016/0378344).
With regard to Claim 1, Nachimuthu teaches a system comprising:
non-volatile memory ([0027] “the mechanism employs a persistent storage device such as an SSD to back up selected data (or all data) on DRAM DIMMs (or other DRAM devices) upon detection of a power failure/power unavailable condition.”); and
at least one controller configured to, in response to detecting an impending loss of power, store first data in the non-volatile memory (Fig. 3a: CPU 304. [0039] “FIG. 5b shows a configuration under which AC power source 340 has failed or otherwise has been removed or is unavailable. In response to detecting such an event…” [0041] “In one embodiment, the DMA engine detects the socket power failure condition” [0044] “in one embodiment in response to detection of a power failure/unavailable condition, an SMI (System Management Interrupt) is signaled for BIOS to flush all the processor cache(s).” [0052] “The process flow begins in a start block 702 in which the platform power failure or platform shutdown occurs … In a block 706 the processor cache(s) and the write-pending queue are flushed to flush all of the persistent data (in the cache(s) and write-pending queues to memory (DRAM). If the platform power supply does not have enough capacitance, this operation is ignored and the DMA engine enables the SSD and starts copying data from DRAM to the SSD.”).
With regard to Claim 2, Nachimuthu teaches the system of claim 1, further comprising a power supply monitor configured to provide a signal to the controller responsive to detecting the impending loss of power provided by a power supply (Fig. 3a: DMA Engine 312. [0027] “when the platform power fails/becomes unavailable, the DMA engine detects the condition and reads the DRAM contents from the DRAM DIMMS and writes the data to the persistent storage device.” [0041] “In one embodiment, the DMA engine detects the socket power failure condition” [0044] “in one embodiment in response to detection of a power failure/unavailable condition, an SMI (System Management Interrupt) is signaled for BIOS to flush all the processor cache(s).”).
With regard to Claim 3, Nachimuthu teaches the system of claim 1, wherein the controller is further configured to, in response to detecting the impending loss of power, generate a log associated with storing the first data ([0077] “Under some failure conditions, enough of the operating system is still accessible to enable the surviving portion to dump the memory contents to storage (typically to a large log or debug file).”).
With regard to Claim 4, Nachimuthu teaches the system of claim 1, wherein the controller is further configured to, in response to detecting the impending loss of power, provide a signal to a host system ([0044] “in one embodiment in response to detection of a power failure/unavailable condition, an SMI (System Management Interrupt) is signaled for BIOS to flush all the processor cache(s) and then send a signal to the DMA engine to enter the power fail mode to save the DRAM content to SSD. Further details of the use of SMI are described below with reference to FIG. 10,” wherein the system shown in Fig. 3 of Nachimuthu is the “host system”.).
With regard to Claim 6, Nachimuthu teaches the system of claim 1, wherein the controller is further configured to, in response to detecting the impending loss of power, write a log associated with power fail handling ([0077] “Under some failure conditions, enough of the operating system is still accessible to enable the surviving portion to dump the memory contents to storage (typically to a large log or debug file).”).
With regard to Claim 7, Nachimuthu teaches the system of claim 1, wherein no further read or write operations, other than storing the first data, can be performed using the non-volatile memory after the impending loss of power is detected ([0053] “In a block 710, the processor enters a power down state, where all of the PCIe links expect the power protected links are turned off, processor to processor links (e.g., socket-to-socket links) are turned off, and the CPU cores are turned off,” wherein “no further read or write operations can be performed” after the all CPU cores have been turned off in Nachimuthu.).
Claims 8-11 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sweere et al. (US Patent 8,325,554).
With regard to Claim 8, Sweere teaches an apparatus comprising:
a memory interface (Col. 6 Ln. 33-40: “The memory module 200 may include a substrate with an interface 202 (e.g., bus interface, edge connector, one or more connecting sockets, etc.) for electrically and/or physically coupling the memory module 200 to an external bus that may provide data information, address information, control information, power/ground, etc., from a host system (e.g., RAID controller or other source).”); and
at least one controller configured to, in response to detecting that a voltage falls below a threshold, disable the memory interface (Col. 7 Ln. 54-55: “The backup/restore circuit 222 may be implemented by one or more controllers.” Col. 8 Ln. 24-39: “FIG. 3 illustrates a state diagram that may be implemented in a memory module to backup data upon detection of an external triggering event (e.g., power failure, hardware signal, host system command, etc.). In one example, the state diagram may be implemented by the backup/restore logic device 222… The memory module may monitor for (or receive an indicator of) an external triggering event (e.g., a low voltage, loss of power event, etc.).” Col. 9 Ln. 11-14: “an external triggering event is detected 404 (e.g., voltage to the memory module provided by an external power source falls below a threshold voltage level).” Col. 5 Ln. 41-43: “In backup mode, the controller may be adapted to decouple the volatile memory from the host system and couple it to the non-volatile memory devices,” and Col. 18 Ln. 49-52: “in FIG. 2, data bus switch 220 and address/control bus switch 218 may be reconfigured to decouple the volatile memory devices 204 from the interface 202,” wherein the decoupling described above serves to “disable the memory interface”.).
With regard to Claim 9, Sweere teaches the apparatus of claim 8, wherein the voltage is a power supply voltage (Col. 7 Ln. 34-36: “if the external power supply provides a low voltage (e.g., a voltage level less than a threshold voltage level).” Col. 9 Ln. 11-14: “an external triggering event is detected 404 (e.g., voltage to the memory module provided by an external power source falls below a threshold voltage level).”).
With regard to Claim 10, Sweere teaches the apparatus of claim 8, wherein
the memory interface is configured to receive data from a host (Col. 6 Ln. 1-5: “the RAID controller 104 may include cache memory storage 106 which may be used to temporarily store data as it is transferred from the host computer 102 to the RAID 108. In one example, the cache memory storage 106 may include may include volatile memory devices arranged as a double data rate (DDR) dual in-line memory modules (DIMM),” wherein the “cache memory storage” comprises the “memory module” shown Fig. 2 of Sweere.), and
the controller is further configured to store the data in a non-volatile memory (Col. 6 Ln. 50-55: “One or more of these components may allow data stored in the one or more volatile memory devices 204 to be backed up in the one or more non-volatile memory devices 206 when a triggering event (e.g., a power interruption, hardware signal, and/or host system command) is detected, thereby preventing loss of data.”).
With regard to Claim 11, Sweere teaches the apparatus of claim 8, wherein the memory interface is configured to receive data associated with write commands (Col. 6 Ln. 1-5: “the RAID controller 104 may include cache memory storage 106 which may be used to temporarily store data as it is transferred from the host computer 102 to the RAID 108.” Col. 1 Ln. 30-32: “The cache often will momentarily contain the only copy of a piece of write data until that data can be written to the disk.”).
With regard to Claim 15, Sweere teaches a device comprising:
a cache (Col. 6 Ln. 1-5: “the RAID controller 104 may include cache memory storage 106 which may be used to temporarily store data as it is transferred from the host computer 102 to the RAID 108. In one example, the cache memory storage 106 may include may include volatile memory devices arranged as a double data rate (DDR) dual in-line memory modules (DIMM).”); and
at least one controller configured to, in response to receiving a signal from a power supply, store data received by the cache prior to receiving the signal (Col. 6 Ln. 50-55: “One or more of these components may allow data stored in the one or more volatile memory devices 204 to be backed up in the one or more non-volatile memory devices 206 when a triggering event (e.g., a power interruption, hardware signal, and/or host system command) is detected, thereby preventing loss of data.” Col. 17 Ln. 40: “The power circuit 2100 may also include a voltage detector 2114 that is configured to sense changes in voltage from the external power source. The voltage detector 2114 may be adapted to determine when the incoming voltage level falls below a voltage threshold which may indicate a power failure or loss.” Col. 17 Ln. 51-55: “the voltage detector 2114 may also generate a power failure interrupt signal 2120. When the power failure interrupt signal 2120 is set, this is an indicator of imminent power failure and can be used by other components.”).
With regard to Claim 16, Sweere teaches the device of claim 15, wherein the cache is configured to receive write commands from a host (Col. 1 Ln. 30-32: “The cache often will momentarily contain the only copy of a piece of write data until that data can be written to the disk”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu as applied to Claim 1, and further in view of Marathe et al. (US PGPUB 2018/0046556).
With regard to claim 5, Nachimuthu teaches all the limitations of claim 1 as described above. Nachimuthu does not teach the memory refresh as described in claim 5. Marathe teaches
wherein the host system is configured to implement a memory refresh in response to receiving the signal ([0043] “Another example is the asynchronous DRAM refresh (ADR) feature provided by many modern processors, in which the memory controller buffers may be flushed out to memory DIMMs on power failure,” wherein the “signal” is the signal associated with a power failure as taught above in Nachimuthu.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Nachimuthu with the memory refresh as taught by Marathe since “With the ADR feature, the memory controller buffers may be considered effectively persistent in some embodiments since the data may be guaranteed to persist” (Marathe [0043]).
Claims 12-13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sweere as applied to Claims 11 and 15, and further in view of Jayakumar et al. (US PGPUB 2016/0188414).
With regard to claim 12, Sweere teaches all the limitations of claim 11 as described above. Sweere does not teach the queue and cache configuration as described in claim 12. Jayakumar teaches
wherein the write commands are moved to a queue from at least one cache of a host system ([0015] “each of the cores 106 may include a Level 1 (L1) cache (116-1) (generally referred to herein as ‘L1 cache 116’) and/or Level 2 (L2) cache (e.g., discussed with reference to FIG. 3).” [0036] “WPQ or memory buffers generally refer to Write Pending Queue (WPQ) or buffers (labeled as ‘P1’ in FIG. 3) inside the iMC 310.” [0037] “buffers in the iMC 310 (shown as P1) and in the IIO switch 312 (shown as P2) reside en route to persistent memory,” wherein the WPQ buffers in Jayakumar are well-known to comprise data originating from an L1/L2 cache of a host processor core which is en route to the persistent memory, i.e. NVM 152 shown in Fig. 1 of Jayakumar.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Sweere with the queue and cache configuration as taught by Jayakumar as this “ensures durability of data that is residing in volatile buffers (such as one or more of memory buffer(s), IIO buffer(s), etc.), in the face of platform failures” (Jayakumar [0030]).
With regard to claim 13, Sweere teaches all the limitations of claim 11 as described above. Sweere does not teach the persisting of writes as described in claim 13. Jayakumar teaches
wherein the write commands correspond to stores to be persisted by a host system, and wherein the host system moves the write commands to a queue prior to retiring the stores ([0009] “Software considers that data written to a persistence memory range has reached durability as soon as the store instruction completes, but that data could still be residing in volatile buffers (such as memory controller write pending queue or processor caches).” [0036] “WPQ or memory buffers generally refer to Write Pending Queue (WPQ) or buffers (labeled as ‘P1’ in FIG. 3) inside the iMC 310.” [0037] “buffers in the iMC 310 (shown as P1) and in the IIO switch 312 (shown as P2) reside en route to persistent memory.” [0038] “any store operation that is done by software is considered complete once it is posted to the buffers (P1/P2) shown in this diagram. That the data is still residing in these buffers en route to NVDIMM is transparent to software and software at this point considers this as persistent data.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Sweere with the persisting of writes as taught by Jayakumar as this “ensures durability of data that is residing in volatile buffers (such as one or more of memory buffer(s), IIO buffer(s), etc.), in the face of platform failures” (Jayakumar [0030]).
With regard to claim 17, Sweere teaches all the limitations of claim 15 as described above. Sweere does not teach the protected write buffer as described in claim 17. Jayakumar teaches
wherein the signal causes a central processing unit (CPU) to save a protected write buffer to persistent memory ([0036] “WPQ or memory buffers generally refer to Write Pending Queue (WPQ) or buffers (labeled as ‘P1’ in FIG. 3) inside the iMC 310,” wherein the “WPQ” is the “protected write buffer”. [0031] “a (e.g., relatively small) non-volatile shadow buffer is provided inside the processor. This is not used under normal operations. In response to occurrence of an ADR event, the processor takes a snap-shot (or copy) the contents of the volatile buffers into this non-volatile storage device. This can act as a non-volatile back up storage device for the data in the WPQ and IIO Buffers,” wherein the “non-volatile shadow buffer” is the “persistent memory”. [0036] “ADR generally refers to a legacy mechanism, which provides an external trigger, that when activated causes the data in the WPQ, conceptually referred to as ‘ADR safe zone’, to be flushed over to NVDIMM. The ADR pin is triggered by an early AC power detection circuitry... ADR covers AC power failure”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Sweere with the queue and cache configuration as taught by Jayakumar as this “ensures durability of data that is residing in volatile buffers (such as one or more of memory buffer(s), IIO buffer(s), etc.), in the face of platform failures” (Jayakumar [0030]).
With regard to Claim 18, Sweere in view of Jayakumar teaches all the limitations of Claim 17 as described above. Jayakumar further teaches wherein the write buffer is a write queue including write commands that are flushed responsive to the signal ([0010] “ADR is a legacy mechanism that flushes the memory controller buffers (e.g., Write Pending Queue) … in response to AC (Alternating Current) power failure.”).
With regard to Claim 19, Sweere in view of Jayakumar teaches all the limitations of Claim 18 as described above. Jayakumar further teaches wherein write commands in the write queue correspond to write operations committed by a host ([0034] “FIG. 3 illustrates a block diagram of various components present on a processor Integrated Circuit (IC) die 300, according to an embodiment. For example, processor die 300 may include the same or similar components as those discussed with reference to processors of FIGS. 1-2 and 5-7 in various embodiments,” wherein the “processor Integrated Circuit (IC) die 300” is the “host”. [0036] “As discussed herein, WPQ or memory buffers generally refer to Write Pending Queue (WPQ) or buffers (labeled as ‘P1’ in FIG. 3) inside the iMC 310. The data in the WPQ is waiting to be committed to memory, but are globally visible.” [0038] “Moreover, any store operation that is done by software is considered complete once it is posted to the buffers (P1/P2) shown in this diagram. That the data is still residing in these buffers en route to NVDIMM is transparent to software and software at this point considers this as persistent data. Any system power failure or reset at this point may result in a silent data corruption since software considered this data as committed to persistent storage.”).
With regard to Claim 20, Sweere in view of Jayakumar teaches all the limitations of Claim 19 as described above. Jayakumar further teaches device of claim 19, wherein the write commands are flushed based on an instruction provided by software executing on the host ([0072] “In various embodiments, the operations discussed herein, e.g., with reference to FIGS. 1-7, may be implemented as hardware (e.g., circuitry), software, firmware, microcode, or combinations thereof, which may be provided as a computer program product… having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein.”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sweere in view of Jayakumar as applied to Claim 13, and further in view of Beckmann et al. (US PGPUB 2012/0254541).
With regard to claim 14, Sweere in view of Jayakumar teaches all the limitations of claim 13 as described above. Sweere in view of Jayakumar does not teach the fence instruction as described in claim 14. Jayakumar teaches
wherein the host system ensures that stores prior to a store fence instruction are globally visible before any store after the store fence instruction becomes globally visible ([0047] “a FENCE instruction 124 performs a serializing operation on all stores to memory (e.g., write requests 130/de-coupled writethroughs 132) that were issued prior to the FENCE instruction 124. This serializing operation ensures that every store instruction that precedes the FENCE instruction 124 in program order is globally visible before any load/store instruction that follows the FENCE instruction 124 is globally visible.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Sweere in view of Jayakumar with the fence instruction as taught by Beckmann as this “to enforce an ordering constraint on memory operations (e.g., reads/writes)” (Beckmann [0047]).
Response to Arguments
Applicant’s arguments, see Pages 1-5 of the Remarks filed 12/22/2025, with respect to the rejections under 35 U.S.C. 102/103 have been fully considered but they are not persuasive.
With respect to applicant’s arguments that the features of Claims 1-20 are not taught by the cited prior art, the Office respectfully disagrees and refers applicant to the rejection of the instant claims as discussed supra with respect to the same.
With respect to Applicant’s argument regarding Claim 1, Page 2 of the Remarks, that Nachimuthu does not teach, “at least one controller configured to, in response to detecting an impending loss of power, store data in the non-volatile memory”, the Office respectfully disagrees. The Applicant argues that “The prior art does not identically teach the foregoing combination of features” since “Nachimuthu at paragraph 27 merely describes that a DMA engine detects a power failure and reads the DRAM contents. The DRAM contents is written to a persistent storage device” [sic], the Office respectfully disagrees and contends that the system disclosed by Nachimuthu does teach the system recited in Claim 1. The Office would like to draw the Applicant’s attention to the following citations in Nachimuthu:
[0026] “As used herein, the term SSD (Solid State Disk) is used to describe a type of persistent storage device”.
[0027] “Under an embodiment of the solution, DRAM DIMMs, memory controllers, an IO link that links a processor in communication with the persistent storage device and a DMA (Direct Memory Access) engine (memory copy engine) are power protected, such that they are provided with temporary power in the event of a power failure or power unavailable condition. In one embodiment, when the platform power fails/becomes unavailable, the DMA engine detects the condition and reads the DRAM contents from the DRAM DIMMS and writes the data to the persistent storage device.”
[0028] “System 300 includes a processor 302 comprising a CPU 304, two iMCs 306 and 308, and an IIO interface 310 including a DMA engine 312.”
[0039] “FIG. 5b shows a configuration under which AC power source 340 has failed or otherwise has been removed or is unavailable. In response to detecting such an event…”.
[0041] “In one embodiment, the DMA engine detects the socket power failure condition and starts to read the local socket DIMMs contents and stores (via DMA writes) to the power protected SSD(s).”
[0044] “in one embodiment in response to detection of a power failure/unavailable condition, an SMI (System Management Interrupt) is signaled for BIOS to flush all the processor cache(s).”
[0052] “The process flow begins in a start block 702 in which the platform power failure or platform shutdown occurs … In a block 706 the processor cache(s) and the write-pending queue are flushed to flush all of the persistent data (in the cache(s) and write-pending queues to memory (DRAM). If the platform power supply does not have enough capacitance, this operation is ignored and the DMA engine enables the SSD and starts copying data from DRAM to the SSD.”
The Office would next like to draw attention to the Applicant’s specification which recites the following:
[0025] “In some instances, the controller 116 is integrated within the same package of the processing device 118.”
As such, in view of at least the citations above, it has been shown that the “SSD” and “DMA engine” in Nachimuthu respectively teaches the claimed “non-volatile memory” and “at least one controller.” Furthermore, the above citations also show that the “DMA engine” in Nachimuthu copies data from a “DRAM” to the “SSD” when it is detected that the platform power has failed or become unavailable, wherein temporary power is provided and full power loss is impending.
Therefore, for at least the reasons discussed above, the rejection of Claim 1 has been maintained, as the disclosure of Nachimuthu has been shown to teach and anticipate the limitations of Claim 1.
With respect to Applicant’s argument regarding Claim 8, Pages 2-3 of the Remarks, that Sweere does not teach, “in response to detecting that a voltage falls below a threshold, disable the memory interface”, the Office respectfully disagrees. The Applicant argues that “Sweere does not identically teach disabling a memory interface (e.g., the interface to a host 202 of Figure 2) in response to detecting that voltage falls below a threshold, as claimed. Instead, Sweere teaches that the interface to the host is kept in an enabled state,” the Office respectfully disagrees and contends that the system disclosed by Sweere does teach the apparatus recited in Claim 8. The Office would like to draw the Applicant’s attention to the following citations in Sweere:
Col. 7 Ln. 54-55: “The backup/restore circuit 222 may be implemented by one or more controllers.”
Col. 8 Ln. 24-39: “FIG. 3 illustrates a state diagram that may be implemented in a memory module to backup data upon detection of an external triggering event (e.g., power failure, hardware signal, host system command, etc.). In one example, the state diagram may be implemented by the backup/restore logic device 222… The memory module may monitor for (or receive an indicator of) an external triggering event (e.g., a low voltage, loss of power event, etc.).”
Col. 9 Ln. 11-14: “an external triggering event is detected 404 (e.g., voltage to the memory module provided by an external power source falls below a threshold voltage level).”
Col. 5 Ln. 41-43: “In backup mode, the controller may be adapted to decouple the volatile memory from the host system and couple it to the non-volatile memory devices,” and
Col. 18 Ln. 49-52: “in FIG. 2, data bus switch 220 and address/control bus switch 218 may be reconfigured to decouple the volatile memory devices 204 from the interface 202.”
Col. 18 Ln. 19-28: “FIG. 24 is a block diagram illustrating one example of the functional modules of a backup and restore logic device 2400 that may be utilized by a memory module having volatile memory and non-volatile memory. In one implementation, the backup and restore logic device 2400 maybe implemented within a processing circuit, controller, application specific integrated circuit (ASIC), switch, Field Programmable Gate Array (FPGA), etc. In one example, the backup and restore logic device 2400 may be the backup/restore logic device 222 of FIG. 2.”
See Fig. 24 showing “Volatile Memory Controller 2406,” i.e. the “memory interface,” inside “Backup and Restore Logic Device 2400.”
As such, in view of at least the citations above, it has been shown that the “volatile memory” can be decoupled from the “volatile memory controller” in Sweere in response to detecting a “triggering event” indicating that the voltage has fallen below a “threshold voltage level,” wherein the interface between “volatile memory controller” and the “volatile memory” is the claimed “memory interface”. The Office notes that although Sweere does disclose that a further “memory interface,” between the “non-volatile memory controller” and the “non-volatile memory,” is maintained coupled and operational, this does not preclude Sweere from teaching that that the “memory interface” between “volatile memory controller” and the “volatile memory” is decoupled in response to detecting the voltage falling below a threshold.
Therefore, for at least the reasons discussed above, the rejection of Claim 8 has been maintained, as the disclosure of Sweere has been shown to teach and anticipate the limitations of Claim 8.
With respect to Applicant’s argument regarding Claim 15, Pages 3-4 of the Remarks, that Sweere does not teach, “in response to receiving a signal from a power supply, store data received by the cache prior to receiving the signal”, the Office respectfully disagrees. The Applicant argues that “The person of ordinary skill recognizes that the detector [in Sweere] merely senses a voltage level. This does not identically teach receiving a signal from a power supply, as claimed,” and further that “The office action references a cache of a RAID controller at Sweere 6:1-5. However, Sweere does not reference this cache in describing the copying of data,” the Office respectfully disagrees and contends that the system disclosed by Sweere does teach the device recited in Claim 15. The Office would like to draw the Applicant’s attention to the following citations in Sweere:
Col. 6 Ln. 1-5: “the RAID controller 104 may include cache memory storage 106 which may be used to temporarily store data as it is transferred from the host computer 102 to the RAID 108. In one example, the cache memory storage 106 may include may include volatile memory devices arranged as a double data rate (DDR) dual in-line memory modules (DIMM).”
Col. 6 Ln. 50-55: “One or more of these components may allow data stored in the one or more volatile memory devices 204 to be backed up in the one or more non-volatile memory devices 206 when a triggering event (e.g., a power interruption, hardware signal, and/or host system command) is detected, thereby preventing loss of data.”
Col. 17 Ln. 40: “The power circuit 2100 may also include a voltage detector 2114 that is configured to sense changes in voltage from the external power source. The voltage detector 2114 may be adapted to determine when the incoming voltage level falls below a voltage threshold which may indicate a power failure or loss.”
Col. 17 Ln. 51-55: “the voltage detector 2114 may also generate a power failure interrupt signal 2120. When the power failure interrupt signal 2120 is set, this is an indicator of imminent power failure and can be used by other components.”
Col. 21 Ln. 40-46: “Upon receiving a triggering event indicator signal 2802 (e.g., power failure interrupt signal from a voltage detector or an external source indicating imminent loss of power to the memory module), the logic device 2800 may be configured to enter backup mode. In backup mode, the logic device 2800 facilitates data storage from volatile memory into non-volatile memory.”
As such, in view of at least the citations above, it has first been shown that the “cache memory storage” associated with the “RAID controller” may include “volatile memory devices,” and further that the data stored in the “volatile memory devices” are backed up in the “non-volatile memory devices” when a triggering event is detected, such as the voltage level falling below a threshold voltage. Further, the above citations also show that the “power circuit” includes a “voltage detector” that is able to determine when the voltage level falls below a threshold voltage and to in response generate a “power failure interrupt signal” which is used to trigger a “backup mode” which results in data being stored from the “volatile memory devices” to the “non-volatile memory devices”.
Therefore, for at least the reasons discussed above, the rejection of Claim 15 has been maintained, as the disclosure of Sweere has been shown to teach and anticipate the limitations of Claim 15.
With respect to the Applicant’s arguments that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to Claims 1, 8 and 15, and as such the Office directs the Applicant to the responses above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Mukker et al. (US PGPUB 2013/0254457) discloses methods and systems for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory, wherein the offloading in response to a detected power loss.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 May 2, 2026
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