DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-10, 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (US 2014/0153155) in view of Yokomizo (US 2020/0343048).
In regards to claim 1,
Fujii ‘155 discloses a multilayer ceramic capacitor comprising:
a capacitor body (10 – fig. 1; [0026]) including:
a plurality of dielectric layers (fig. 2; [0028]);
a plurality of first inner electrodes (11 – fig. 2; [0028]);
a plurality of second inner electrodes (12 – fig. 2; [0028]);
a first principal surface (1 – fig. 1; [0026]) and a second principal surface (2 – fig. 1; [0026]) opposed to each other in a first direction;
a first side surface (3 – fig. 1; [0026]) and a second side surface (4 – fig. 1; [0026]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (5 – fig. 1; [0026]) and a second end surface (6 – fig. 1; [0026]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (15 – fig. 2; [0028]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (16 – fig. 2; [0028]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 2). Fujii ‘155 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm.
Yokomizo ‘048 discloses a first bump (20a – fig. 1; [0041]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0042]); and a second bump (20b – fig. 1; [0041]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0042]); the first outer electrode includes a first metal layer ([0037] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0037] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0044]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Yokomizo ‘048 with the capacitor of Fujii ‘155 to obtain a capacitor with improved protection from noise.
In regards to claim 3,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein a proportion of an area of a flat region of the second principal surface of the capacitor body relative to an area of the second principal surface is equal to or greater than about 0.8 (fig. 1-2 & 6-7 of Fujii ‘155).
In regards to claim 5,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein the first outer electrode and the second outer electrode are provided only on the first principal surface of the capacitor body (fig. 6-7 of Fujii ‘155).
In regards to claim 6,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein the first outer electrode is provided on the first principal surface and the first end surface; and the second outer electrode is provided on the first principal surface and the second end surface of the capacitor body (fig. 2 of Fujii ‘155).
In regards to claim 7,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein the first outer electrode is provided on the first principal surface, the first end surface, the first side surface, and the second side surface of the capacitor body; and
the second outer electrode is provided on the first principal surface, the second end surface, the first side surface, and the second side surface of the capacitor body (fig. 6-7 of Fujii ‘155).
In regards to claim 8,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a major component ([0032] of Fujii ‘155).
In regards to claim 9,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the major component ([0032] of Fujii ‘155).
In regards to claim 10,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes Ni, Ag, Pd, Au, Cu, Ti, or Cr, or an alloy including any of Ni, Ag, Pd, Au, Cu, Ti, or Cr as a major component ([0033] of Fujii ‘155).
In regards to claim 13,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein the first outer electrode includes a first foundation electrode layer and the first metal layer on the first foundation electrode layer; and the second outer electrode includes a second foundation electrode layer and the second metal layer on the second foundation electrode layer ([0034] of Fujii ‘155).
In regards to claim 14,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the first and second foundation electrode layers is a baked electrode layer including glass and a metal ([0033] & [0081] of Fujii ‘155).
In regards to claim 15,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein the metal includes Cu, Ni, Ag, Pd, Ti, Cr, or Au, or an alloy including any of Cu, Ni, Ag, Pd, Ti, Cr, or Au ([0033] of Fujii ‘155).
In regards to claim 16,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the first and second foundation electrode layers is a resin electrode layer ([0033] of Fujii ‘155).
In regards to claim 17,
Fujii ‘155 as modified by Yokomizo ‘048 further discloses wherein each of the first and second foundation electrode layers is a thin film electrode layer ([0033] of Fujii ‘155).
Claim(s) 1-3, 6, 8-10, 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Togawa (US 2020/0388439) in view of Fujita et al. (US 2019/0287719).
In regards to claim 1,
Togawa ‘439 discloses a multilayer ceramic capacitor comprising:
a capacitor body (12 – fig. 1; [0031]) including:
a plurality of dielectric layers (14 – fig. 3; [0032]);
a plurality of first inner electrodes (16 – fig. 1; [0031]);
a plurality of second inner electrodes (16 – fig. 1; [0031]);
a first principal surface (12b – fig. 1; [0031]) and a second principal surface (12a – fig. 1; [0031]) opposed to each other in a first direction;
a first side surface (12c – fig. 1; [0031]) and a second side surface (12d – fig. 1; [0031]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (12e – fig. 1; [0031]) and a second end surface (12f – fig. 1; [0031]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 1). Togawa ‘439 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm.
Fujita ‘719 discloses a first bump (16 – fig. 1; [0043]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0043]); and a second bump (17 – fig. 1; [0043]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0043]); the first outer electrode includes a first metal layer ([0039] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0039] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0044]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Fujita ‘719 with the capacitor of Togawa ‘439 to obtain a capacitor with improved protection from noise.
In regards to claim 2,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein thicknesses of the first metal layer and the second metal layer are equal to or greater than about 0.3 μm ([0079] of Togawa ‘439).
In regards to claim 3,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein a proportion of an area of a flat region of the second principal surface of the capacitor body relative to an area of the second principal surface is equal to or greater than about 0.8 (fig. 1 of Togawa ‘439).
In regards to claim 6,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein the first outer electrode is provided on the first principal surface and the first end surface; and the second outer electrode is provided on the first principal surface and the second end surface of the capacitor body (fig. 1-3 of Togawa ‘439).
In regards to claim 8,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a major component ([0035] of Togawa ‘439).
In regards to claim 9,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the major component ([0035] of Togawa ‘439).
In regards to claim 10,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes Ni, Ag, Pd, Au, Cu, Ti, or Cr, or an alloy including any of Ni, Ag, Pd, Au, Cu, Ti, or Cr as a major component ([0047] of Togawa ‘439).
In regards to claim 13,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein the first outer electrode includes a first foundation electrode layer (26a– fig. 3; [0057] of Togawa ‘439) and the first metal layer (32a – fig. 3; [0078]) on the first foundation electrode layer; and the second outer electrode includes a second foundation electrode layer (26b – fig. 3; [0057] of Togawa ‘439) and the second metal layer (32b – fig. 3; [0078]) on the second foundation electrode layer.
In regards to claim 14,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the first and second foundation electrode layers is a baked electrode layer including glass and a metal ([0058-0059] of Togawa ‘439).
In regards to claim 15,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein the metal includes Cu, Ni, Ag, Pd, Ti, Cr, or Au, or an alloy including any of Cu, Ni, Ag, Pd, Ti, Cr, or Au ([0058-0059] of Togawa ‘439).
In regards to claim 16,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the first and second foundation electrode layers is a resin electrode layer ([0061] of Togawa ‘439).
In regards to claim 17,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein each of the first and second foundation electrode layers is a thin film electrode layer ([0074] of Togawa ‘439).
In regards to claim 18,
Togawa ‘439 as modified by Fujita ‘719 further discloses wherein the thin film electrode layer has a thickness of equal to or less than about 1 μm ([0074] of Togawa ‘439).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Togawa ‘439 as modified by Fujita ‘719 as applied to claim 1 above, and further in view of Ritter et al. (US 2004/0257748).
In regards to claim 11,
Togawa ‘439 as modified by Fujita ‘719 fails to disclose wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes a same material as the plurality of dielectric layers.
Ritter '748 discloses wherein each of the first inner electrodes and the second inner electrodes includes a same dielectric ceramic material as that included in the plurality of dielectric layers ([0163]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the inner electrodes of Togawa ‘439 as modified by Fujita ‘719using a material as taught by Ritter '748 to control shrinkage of the internal electrodes during firing.
In regards to claim 12,
Togawa ‘439 as modified by Fujita ‘719 and Ritter '748 further discloses wherein a content percentage of the same material is each of the plurality of first inner electrode layers and the plurality of second inner electrode layers is about 20% by volume or less ([0163]).
Claim(s) 1 & 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hattori et al. (US 2014/0268488) in view of Fujita ‘719.
In regards to claim 1,
Hattori ‘488 discloses a multilayer ceramic capacitor comprising:
a capacitor body (10 – fig. 1; [0025]) including:
a plurality of dielectric layers (fig. 3-4; [0027]);
a plurality of first inner electrodes (11 – fig. 3-4; [0027]);
a plurality of second inner electrodes (12 – fig. 3-4; [0027]);
a first principal surface (1 – fig. 1; [0026]) and a second principal surface (2 – fig. 1; [0026]) opposed to each other in a first direction;
a first side surface (3 – fig. 1; [0026]) and a second side surface (4 – fig. 1; [0026]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (5 – fig. 1; [0026]) and a second end surface (6 – fig. 1; [0026]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (15 – fig. 2-4; [0027]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (16 – fig. 2-4; [0027]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 2-4). Hattori ‘488 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm.
Fujita ‘719 discloses a first bump (16 – fig. 1; [0043]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0043]); and a second bump (17 – fig. 1; [0043]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0043]); the first outer electrode includes a first metal layer ([0039] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0039] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0044]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Fujita ‘719 with the capacitor of Hattori ‘488 to obtain a capacitor with improved protection from noise.
In regards to claim 4,
Hattori ‘488 as modified by Yokomizo ‘048 further discloses wherein a Young's modulus of the capacitor body is equal to or greater than about 67 GPa ([0040] of Hattori ‘488).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0202175 – fig. 1 US 2019/0069412 – fig. 1
US 2014/0076621 – fig. 3 US 2016/0093441 – fig. 1
US 2019/0103221 – fig. 3
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2848