DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 September 2026 has been entered.
Response to Arguments
Applicant's arguments filed 17 September 2026 have been fully considered but they are not persuasive.
Applicant argues allowability based on the amendment and further argues the thickness of the bumps is a critical feature to allow for ultrasonic joining to be feasible.
The examiner finds applicants arguments unpersuasive. Firstly, to establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). Secondly, the ultrasonic joining is made feasible by reducing the vibration transfer to the ceramic body. The prior art of record has recognized that incorporating bumps with a thickness of greater than 4.5 microns to reduce vibration transfer to the ceramic body and thus the results would be expected.
New grounds of rejection are further provided.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 8, 10, & 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun et al. (US 2016/0217926).
In regards to claim 1, Jun ‘926 discloses
A multilayer ceramic capacitor comprising:
a capacitor body (110 – fig. 1; [0031]) including:
a plurality of dielectric layers (113 – fig. 2; [0033]);
a plurality of first inner electrodes (111 – fig. 2; [0033]);
a plurality of second inner electrodes (112 – fig. 2; [0033]);
a first principal surface and a second principal surface (opposed to each other in a first direction (seen in fig. 1-2);
a first side surface and a second side surface opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction (seen in fig. 1-2); and
a first end surface (and a second end surface opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction (seen in fig. 1-2);
a first outer electrode (321 – fig. 5; [0066]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (322 – fig. 5; [0066]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
a first bump (131/331 – fig. 1-3 & 5; [0031]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0046]); and
a second bump (132/332 – fig. 1-3 & 5; [0031]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0046]);
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 5; [0066]);
the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump ([0039] – copper);
the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump ([0039] – copper); and
a thickness (A – fig. 3; [0059]) of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm (table 1), and
in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes (fig. 1-3).
In regards to claim 3, Jun ‘926 discloses
The multilayer ceramic capacitor according to claim 1, wherein a proportion of an area of a flat region of the second principal surface of the capacitor body relative to an area of the second principal surface is equal to or greater than about 0.8 (fig. 5).
In regards to claim 6, Jun ‘926 discloses
The multilayer ceramic capacitor according to claim 1, wherein the first outer electrode is provided on the first principal surface and the first end surface; and the second outer electrode is provided on the first principal surface and the second end surface of the capacitor body (fig. 5).
In regards to claim 8, Jun ‘926 discloses
The multilayer ceramic capacitor according to claim 1, discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a major component ([0034]).
In regards to claim 10, Jun ‘926 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes Ni, Ag, Pd, Au, Cu, Ti, or Cr, or an alloy including any of Ni, Ag, Pd, Au, Cu, Ti, or Cr as a major component ([0036]).
In regards to claim 19, Jun ‘926 discloses
A multilayer ceramic capacitor comprising:
a capacitor body (110 – fig. 1; [0031]) including:
a plurality of dielectric layers (113 – fig. 2; [0033]);
a plurality of first inner electrodes (111 – fig. 2; [0033]);
a plurality of second inner electrodes (112 – fig. 2; [0033]);
a first principal surface and a second principal surface (opposed to each other in a first direction (seen in fig. 1-2);
a first side surface and a second side surface opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction (seen in fig. 1-2); and
a first end surface (and a second end surface opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction (seen in fig. 1-2);
a first outer electrode (321 – fig. 5; [0066]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (322 – fig. 5; [0066]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
a first bump (131/331 – fig. 1-3 & 5; [0031]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0046]); and
a second bump (132/332 – fig. 1-3 & 5; [0031]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0046]);
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 5; [0066]);
the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump ([0039] – copper);
the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump ([0039] – copper); and
a thickness (A – fig. 3; [0059]) of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm (table 1), and
in a sectional view in the first direction and the third direction, an entirety of the first bump overlaps the first outer electrode in the first direction, and an entirety of the second bump overlaps the second outer electrode in the first direction (fig. 1-3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-10, 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (US 2014/0153155) in view of Nishimura et al. (US 2017/0042029).
In regards to claim 1,
Fujii ‘155 discloses a multilayer ceramic capacitor comprising:
a capacitor body (10 – fig. 1; [0026]) including:
a plurality of dielectric layers (fig. 2; [0028]);
a plurality of first inner electrodes (11 – fig. 2; [0028]);
a plurality of second inner electrodes (12 – fig. 2; [0028]);
a first principal surface (1 – fig. 1; [0026]) and a second principal surface (2 – fig. 1; [0026]) opposed to each other in a first direction;
a first side surface (3 – fig. 1; [0026]) and a second side surface (4 – fig. 1; [0026]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (5 – fig. 1; [0026]) and a second end surface (6 – fig. 1; [0026]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (15 – fig. 2; [0028]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (16 – fig. 2; [0028]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 2). Fujii ‘155 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm, and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes.
Nishimura ‘029 discloses a first bump (4 – fig. 4; [0040]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0048]); and a second bump (5 – fig. 4; [0040]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0048]); the first outer electrode includes a first metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0070]), and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes (fig. 4), and further teaches a thickness of the first bump and a thickness of the second bump in the first direction is a result effective variable, particularly for reducing equivalent series resistance and equivalent series inductance, particularly for reducing vibrations ([0095]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Nishimura ‘029 with the capacitor of Fujii ‘155 and to form said bumps to have a thickness of about 4.5 μm or more to obtain a capacitor with improved protection from vibration. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 3,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein a proportion of an area of a flat region of the second principal surface of the capacitor body relative to an area of the second principal surface is equal to or greater than about 0.8 (fig. 1-2 & 6-7 of Fujii ‘155).
In regards to claim 5,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein the first outer electrode and the second outer electrode are provided only on the first principal surface of the capacitor body (fig. 6-7 of Fujii ‘155).
In regards to claim 6,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein the first outer electrode is provided on the first principal surface and the first end surface; and the second outer electrode is provided on the first principal surface and the second end surface of the capacitor body (fig. 2 of Fujii ‘155).
In regards to claim 7,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein the first outer electrode is provided on the first principal surface, the first end surface, the first side surface, and the second side surface of the capacitor body; and
the second outer electrode is provided on the first principal surface, the second end surface, the first side surface, and the second side surface of the capacitor body (fig. 6-7 of Fujii ‘155).
In regards to claim 8,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a major component ([0032] of Fujii ‘155).
In regards to claim 9,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the major component ([0032] of Fujii ‘155).
In regards to claim 10,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes Ni, Ag, Pd, Au, Cu, Ti, or Cr, or an alloy including any of Ni, Ag, Pd, Au, Cu, Ti, or Cr as a major component ([0033] of Fujii ‘155).
In regards to claim 13,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein the first outer electrode includes a first foundation electrode layer and the first metal layer on the first foundation electrode layer; and the second outer electrode includes a second foundation electrode layer and the second metal layer on the second foundation electrode layer ([0034] of Fujii ‘155).
In regards to claim 14,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a baked electrode layer including glass and a metal ([0034] & [0081] of Fujii ‘155).
In regards to claim 15,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein the metal includes Cu, Ni, Ag, Pd, Ti, Cr, or Au, or an alloy including any of Cu, Ni, Ag, Pd, Ti, Cr, or Au ([0034] of Fujii ‘155).
In regards to claim 16,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a resin electrode layer ([0034] of Fujii ‘155).
In regards to claim 17,
Fujii ‘155 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a thin film electrode layer ([0034] of Fujii ‘155).
Claim(s) 1-3, 6, 8-10, 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Togawa (US 2020/0388439) in view of Nishimura ‘029.
In regards to claim 1,
Togawa ‘439 discloses a multilayer ceramic capacitor comprising:
a capacitor body (12 – fig. 1; [0031]) including:
a plurality of dielectric layers (14 – fig. 3; [0032]);
a plurality of first inner electrodes (16 – fig. 1; [0031]);
a plurality of second inner electrodes (16 – fig. 1; [0031]);
a first principal surface (12b – fig. 1; [0031]) and a second principal surface (12a – fig. 1; [0031]) opposed to each other in a first direction;
a first side surface (12c – fig. 1; [0031]) and a second side surface (12d – fig. 1; [0031]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (12e – fig. 1; [0031]) and a second end surface (12f – fig. 1; [0031]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 1). Togawa ‘439 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm, and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes.
Nishimura ‘029 discloses a first bump (4 – fig. 4; [0040]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0048]); and a second bump (5 – fig. 4; [0040]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0048]); the first outer electrode includes a first metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0070]), and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes (fig. 4), and further teaches a thickness of the first bump and a thickness of the second bump in the first direction is a result effective variable, particularly for reducing equivalent series resistance and equivalent series inductance, particularly for reducing vibrations ([0095]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Nishimura ‘029 with the capacitor of Togawa ‘439 and to form said bumps to have a thickness of about 4.5 μm or more to obtain a capacitor with improved protection from vibration. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 2,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein thicknesses of the first metal layer and the second metal layer are equal to or greater than about 0.3 μm ([0079] of Togawa ‘439).
In regards to claim 3,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein a proportion of an area of a flat region of the second principal surface of the capacitor body relative to an area of the second principal surface is equal to or greater than about 0.8 (fig. 1 of Togawa ‘439).
In regards to claim 6,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein the first outer electrode is provided on the first principal surface and the first end surface; and the second outer electrode is provided on the first principal surface and the second end surface of the capacitor body (fig. 1-3 of Togawa ‘439).
In regards to claim 8,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a major component ([0035] of Togawa ‘439).
In regards to claim 9,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the major component ([0035] of Togawa ‘439).
In regards to claim 10,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes Ni, Ag, Pd, Au, Cu, Ti, or Cr, or an alloy including any of Ni, Ag, Pd, Au, Cu, Ti, or Cr as a major component ([0047] of Togawa ‘439).
In regards to claim 13,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein the first outer electrode includes a first foundation electrode layer (26a– fig. 3; [0057] of Togawa ‘439) and the first metal layer (32a – fig. 3; [0078]) on the first foundation electrode layer; and the second outer electrode includes a second foundation electrode layer (26b – fig. 3; [0057] of Togawa ‘439) and the second metal layer (32b – fig. 3; [0078]) on the second foundation electrode layer.
In regards to claim 14,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a baked electrode layer including glass and a metal ([0058-0059] of Togawa ‘439).
In regards to claim 15,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein the metal includes Cu, Ni, Ag, Pd, Ti, Cr, or Au, or an alloy including any of Cu, Ni, Ag, Pd, Ti, Cr, or Au ([0058-0059] of Togawa ‘439).
In regards to claim 16,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a resin electrode layer ([0061] of Togawa ‘439).
In regards to claim 17,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein each of the first and second foundation electrode layers is a thin film electrode layer ([0074] of Togawa ‘439).
In regards to claim 18,
Togawa ‘439 as modified by Nishimura ‘029 further discloses wherein the thin film electrode layer has a thickness of equal to or less than about 1 μm ([0074] of Togawa ‘439).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Togawa ‘439 as modified by Nishimura ‘029 as applied to claim 1 above, and further in view of Ritter et al. (US 2004/0257748).
In regards to claim 11,
Togawa ‘439 as modified by Nishimura ‘029 fails to disclose wherein each of the plurality of first inner electrodes and the plurality of second inner electrodes includes a same material as the plurality of dielectric layers.
Ritter '748 discloses wherein each of the first inner electrodes and the second inner electrodes includes a same dielectric ceramic material as that included in the plurality of dielectric layers ([0163]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the inner electrodes of Togawa ‘439 as modified by Nishimura ‘029 using a material as taught by Ritter '748 to control shrinkage of the internal electrodes during firing.
In regards to claim 12,
Togawa ‘439 as modified by Nishimura ‘029 and Ritter '748 further discloses wherein a content percentage of the same material is each of the plurality of first inner electrode layers and the plurality of second inner electrode layers is about 20% by volume or less ([0163]).
Claim(s) 1 & 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hattori et al. (US 2014/0268488) in view of Nishimura ‘029.
In regards to claim 1,
Hattori ‘488 discloses a multilayer ceramic capacitor comprising:
a capacitor body (10 – fig. 1; [0025]) including:
a plurality of dielectric layers (fig. 3-4; [0027]);
a plurality of first inner electrodes (11 – fig. 3-4; [0027]);
a plurality of second inner electrodes (12 – fig. 3-4; [0027]);
a first principal surface (1 – fig. 1; [0026]) and a second principal surface (2 – fig. 1; [0026]) opposed to each other in a first direction;
a first side surface (3 – fig. 1; [0026]) and a second side surface (4 – fig. 1; [0026]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (5 – fig. 1; [0026]) and a second end surface (6 – fig. 1; [0026]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (15 – fig. 2-4; [0027]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (16 – fig. 2-4; [0027]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 2-4). Hattori ‘488 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm, and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes.
Nishimura ‘029 discloses a first bump (4 – fig. 4; [0040]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0048]); and a second bump (5 – fig. 4; [0040]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0048]); the first outer electrode includes a first metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm ([0070]), and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes (fig. 4), and further teaches a thickness of the first bump and a thickness of the second bump in the first direction is a result effective variable, particularly for reducing equivalent series resistance and equivalent series inductance, particularly for reducing vibrations ([0095]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Nishimura ‘029 with the capacitor of Hattori ‘488 and to form said bumps to have a thickness of about 4.5 μm or more to obtain a capacitor with improved protection from vibration. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 4,
Hattori ‘488 as modified by Nishimura ‘029 further discloses wherein a Young's modulus of the capacitor body is equal to or greater than about 67 GPa ([0040] of Hattori ‘488).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Togawa (US 2020/0388439) in view of Nishimura ‘029.
In regards to claim 19,
Togawa ‘439 discloses a multilayer ceramic capacitor comprising:
a capacitor body (12 – fig. 1; [0031]) including:
a plurality of dielectric layers (14 – fig. 3; [0032]);
a plurality of first inner electrodes (16 – fig. 1; [0031]);
a plurality of second inner electrodes (16 – fig. 1; [0031]);
a first principal surface (12b – fig. 1; [0031]) and a second principal surface (12a – fig. 1; [0031]) opposed to each other in a first direction;
a first side surface (12c – fig. 1; [0031]) and a second side surface (12d – fig. 1; [0031]) opposed to each other in a second direction orthogonal or substantially orthogonal to the first direction; and
a first end surface (12e – fig. 1; [0031]) and a second end surface (12f – fig. 1; [0031]) opposed to each other in a third direction orthogonal or substantially orthogonal to the first direction and the second direction;
a first outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the first inner electrodes;
a second outer electrode (24 – fig. 1-3; [0049-0051]) on at least the first principal surface, and electrically coupled to the second inner electrodes;
wherein the first outer electrode and the second outer electrode are not provided on the second principal surface of the capacitor body (fig. 1). Togawa ‘439 fails to disclose a first bump on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al; and a second bump on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump; the first outer electrode includes a first metal layer on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction are equal to or greater than about 4.5 μm, and in a sectional view in the first direction and the third direction, an entirety of the first bump overlaps the first outer electrode in the first direction, and an entirety of the second bump overlaps the second outer electrode in the first direction..
Nishimura ‘029 discloses a first bump (4 – fig. 4; [0040]) on a surface on a first principal surface side of the capacitor body, and including one of Au, Cu, or Al ([0048]); and a second bump (5 – fig. 4; [0040]) on a surface on the first principal surface side of the capacitor body, and including a same material as the first bump ([0048]); the first outer electrode includes a first metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the first bump, and includes the same material as the first bump; the second outer electrode includes a second metal layer ([0058] – Sn plating layer) on at least a position that comes into contact with the second bump, and includes the same material to the second bump; and a thickness of the first bump and a thickness of the second bump in the first direction is a result effective variable, particularly for reducing equivalent series resistance and equivalent series inductance, particularly for reducing vibrations ([0095]), and in a sectional view in the first direction and the third direction, the first and second bumps do not overlap in the first direction any portion of the first principal surface that is exposed from each of the first and second outer electrodes and is provided between the first and second outer electrodes (fig. 4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate bumps as taught by Nishimura ‘029 with the capacitor of Togawa ‘439 and to form said bumps to have a thickness of about 4.5 μm or more to obtain a capacitor with improved protection from vibration. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP2015204451A – fig. 1-2
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/David M Sinclair/Primary Examiner, Art Unit 2847
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