DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/30/2024 and 10/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 9, 11-14, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mazumder (US 2019/0287581 A1) in view of Cox (US 2019/0392886 A1).
Regarding claim 1, Mazumder teaches a memory device (Fig. 1, [0037] memory device 10), comprising:
a first data pin configured to communicate a data signal (Fig. 1, DQ, [0037] data output (DQ));
a second data pin for communicating a read data strobe signal (Fig. 1, DQS, [0037] data strobe (DQS) signal); and
an ODT control circuit configured to asynchronously control the first termination resistance and the second termination resistance in response to the memory device receiving a read command (Fig. 3, RTT-ON/OFF for DQS, RTT-ON/OFF for DQ, not in sync).
Mazumder does not explicitly teach the memory device comprising:
a first on-die termination (ODT) circuit connected to the first data pin, the first ODT circuit configured to provide a first termination resistance through the first data pin; and
a second ODT circuit connected to the second data pin, the second ODT circuit configured to provide a second termination resistance through the second data pin.
Cox teaches a memory device comprising:
a first on-die termination (ODT) circuit (Fig. 7, ODT 730, [0103]) connected to the first data pin (Fig. 7, DQ), the first ODT circuit configured to provide a first termination resistance through the first data pin (Fig. 7, RTT); and
a second ODT circuit (Fig. 7, ODT 730) connected to the second data pin (Fig. 7, DQS), the second ODT circuit configured to provide a second termination resistance through the second data pin (Fig. 7, RTT).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the separate ODT circuits for each signal line of a data bus as taught by Cox to the teachings of Mazumder in order to provide features including independently changing termination resistance per pin, independent timing support, and allow adjusting the delay common in an unmatched architecture (Cox, [0106]).
Regarding claim 2, all the limitations of claim 1 are taught by Mazumder in view of Cox.
Mazumder further teaches the memory device, wherein, in response to the memory device receiving the read command ([0042] CL 54 is the delay between a read command and the first reading of the data, i.e. RD in Fig. 3 is the start of the read command), the ODT control circuit is configured to:
disable the second ODT circuit (Fig. 3, 90) in an enable state (Fig. 3, RTT-ON for DQS) in response to lapsing of a first time period from the memory device receiving the read command (Fig. 3, RD to 90); and
disable the first ODT circuit (Fig. 3, 86) in an enable state (Fig. 3, RTT-ON for DQ) in response to lapsing of a second time period from the memory device receiving the read command (Fig. 3, RD to 86), wherein the second time period is greater than the first time period (Fig. 3, 86 occurs later than 90).
Regarding claim 3, all the limitations of claim 2 are taught by Mazumder in view of Cox.
Mazumder further teaches the memory device, wherein a difference between the first time period and the second time period is greater than or equal to a read data strobe signal preamble time (Fig. 3, 56 is equal to (90-86)).
Regarding claim 4, all the limitations of claim 1 are taught by Mazumder in view of Cox.
Mazumder further teaches the memory device, wherein the memory device is further configured to: transmit at least a portion of the data signal through the first data pin in response to disabling the first ODT circuit, and transmit the read data strobe signal through the second data pin in response to disabling the second ODT circuit (Fig. 3, [0047] DQ starting from 72).
Regarding claim 8, all the limitations of claim 1 are taught by Mazumder in view of Cox.
Mazumder further teaches the memory device, wherein the memory device is further configured to set at least one bit of a mode register, the at least one bit of the mode register configured to represent an ability of the memory device to asynchronously control the first ODT circuit and the second ODT circuit (Fig. 8, [0056]).
Regarding claim 9, all the limitations of claim 1 are taught by Mazumder in view of Cox.
Mazumder further teaches the memory device, wherein the ODT control circuit is configured to asynchronously control the first ODT circuit and the second ODT circuit based on a read latency (Fig. 8, [0056]).
Regarding claim 11, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 11 is rejected under the same rationale as claim 1 above.
Regarding claim 12, this claim has substantially the same subject matter as that in claim 2. Therefore, claim 12 is rejected under the same rationale as claim 2 above.
Regarding claim 13, this claim has substantially the same subject matter as that in claim 3. Therefore, claim 13 is rejected under the same rationale as claim 3 above.
Regarding claim 11, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 14 is rejected under the same rationale as claim 4 above.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 18 is rejected under the same rationale as claim 8 above.
Regarding claim 19, this claim has substantially the same subject matter as that in claim 9. Therefore, claim 19 is rejected under the same rationale as claim 9 above.
Allowable Subject Matter
Claims 5-7, 10, 15-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior arts fail to teach or reasonably suggest a memory device, wherein the fourth time period is greater than the third time period, in combination with the other limitations of the claim.
Claims 6 and 7 are objected to due to their dependencies to claim 5 above.
Regarding claim 10, the prior arts fail to teach or reasonably suggest a memory device, wherein the memory device is further configured to: receive at least a portion of the data signal through the first data pin between the enabled state of the second ODT and the disabled state of the second ODT, in combination with the other limitations of the claim.
Regarding claim 15, this claim has substantially the same subject matter as that in claim 5. Therefore, claim 15 is allowed under the same rationale as claim 5 above.
Claims 16 and 17 are objected to due to their dependencies to claim 15 above.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 10. Therefore, claim 20 is allowed under the same rationale as claim 10 above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H. Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEOKJIN KIM/Primary Examiner, Art Unit 2844
Prosecution Insights