Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/30/24, 9/10/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 is misleading and seems to be incomplete. The claim does not specify what circuit element or how the control will be adjusted. Dependent claims 17-20 depend therefrom and inherit the deficiencies and are also rejected as a result. Please complete or clarify.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 9, 16, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (US 10,594,308).
With regard to claim 1 Sun discloses:
A device, comprising: a first digital to analog conversion (DAC) circuit comprising a plurality of first capacitors (DAC 504 Fig. 5), wherein the digital to analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal (The processing system 528 may adjust control signals applied to the DAC 504 based on the output of the second comparator 524. As shown, a set of digital control signal outputs 542 may be coupled to the second terminals 522 of the capacitive arrays 512, 514, 516, and 518) and a first comparator (524 Fig. 5).
configured to receive an adjusted input voltage (from DAC 504 VCM sense) from the digital to analog conversion (DAC) circuit (504 Fig. 5), wherein the first control signal is provided in response to a target input voltage (532 Fig. 5) and a sensed input voltage (530 Fig. 5) and adjusts the first input voltage using the first capacitors (DAC capacitors array 512-518).
With regard to claim 2, Sun discloses:
The device of claim 1, wherein the sensed input voltage is provided by a replica circuit (replica Fig. 5).
With regard to claim 9 Sun discloses:
The device of claim 1, wherein the first input voltage is an input common mode voltage (536 Vcm=VTh Fig. 5).
With regard to claim 16, Sun discloses:
An analog-to-digital conversion device, comprising: a plurality of units, each unit comprising: a first digital to analog conversion (DAC) circuit comprising a plurality of capacitors (504 Fig. 5), wherein the digital to analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal (The processing system 528 may adjust control signals applied to the DAC 504 based on the output of the second comparator 524. As shown, a set of digital control signal outputs 542 may be coupled to the second terminals 522 of the capacitive arrays 512, 514, 516, and 518) and; and a first comparator (524 Fig. 5) configured to receive an adjusted input voltage from the digital to analog conversion (DAC) circuit (from DAC 504 Vcm sense), wherein the first control signal is provided in response to a target input voltage (532 Fig. 5) and a sensed input voltage (530 Fig. 5) and adjusts the first input voltage using.
With regard to claim 20 Sun discloses:
The device of claim 16, wherein the first input voltage is an input common mode voltage (Fig. 5 536-Vth=Vtm).
Allowable Subject Matter
Claims 10-15 are allowed.
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845