CTNF 18/788,595 CTNF 100249 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election of “Species I, Subspecies IA, Sub-subspecies 2 with at least claims 1-3, 6-7 and 9-10” in the reply filed on 06/04/2026 is acknowledged. However, the Applicant has failed to mention whether the election is made with or without traverse. Therefore, the above election is treated as an election without traverse. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 and 6-7 are rejected under 35 U.S.C. 102 ( a)(1 ) as being anticipated by Dornbusch (US Publication No. 20070133137) . Regarding claim 1 , Dornbusch discloses an electrostatic discharge (ESD) protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]) comprising: a first pad (i.e., such as first pad VDD; see for example fig. 6, para. [0060]- [0063]) configured to provide (i.e., such as configured to provide the first voltage VDD; see for example fig. 6, para. [0060]- [0063]) a first voltage (i.e., such as first voltage VDD; see for example fig. 6, para. [0060]- [0063]); a second pad (i.e., such as second pad 302; see for example fig. 6, para. [0060]- [0063]) configured to provide (i.e., such as configured to provide the second voltage 302; see for example fig. 6, para. [0060]- [0063]) a second voltage (i.e., such as second voltage 302; see for example fig. 6, para. [0060]- [0063]); an equalizing circuit (i.e., such as equalizing circuit 116, 118, 608; see for example fig. 6, para. [0060]- [0063]) comprising a first inductor (i.e., such as first inductor 116; see for example fig. 6, para. [0060]- [0063]), a second inductor (i.e., such as second inductor 118; see for example fig. 6, para. [0060]- [0063]), and a third inductor (i.e., such as third inductor 608; see for example fig. 6, para. [0060]- [0063]); and a diode circuit (i.e., such as diode circuit 610, 612; see for example fig. 6, para. [0060]- [0063]) comprising a first diode (i.e., such as first diode 610; see for example fig. 6, para. [0060]- [0063]) and a second diode (i.e., such as second diode 612; see for example fig. 6, para. [0060]- [0063]), wherein an end (i.e., such as end cathode of 610; see for example fig. 6, para. [0060]- [0063]) of the first diode (i.e., such as first diode 610; see for example fig. 6, para. [0060]- [0063]) is connected to the first pad (i.e., such as first pad VDD; see for example fig. 6, para. [0060]- [0063]) and another end (i.e., such as another end anode of 610; see for example fig. 6, para. [0060]- [0063]) of the first diode (i.e., such as first diode 610; see for example fig. 6, para. [0060]- [0063]) is connected to the equalizing circuit (i.e., such as equalizing circuit 116, 118, 608; see for example fig. 6, para. [0060]- [0063]), and an end (i.e., such as end cathode of 612; see for example fig. 6, para. [0060]- [0063]) of the second diode (i.e., such as second diode 612; see for example fig. 6, para. [0060]- [0063]) is connected to the equalizing circuit (i.e., such as equalizing circuit 116, 118, 608; see for example fig. 6, para. [0060]- [0063]) and the first diode (i.e., such as first diode 610; see for example fig. 6, para. [0060]- [0063]), and another end (i.e., such as another end anode of 612; see for example fig. 6, para. [0060]- [0063]) of the second diode (i.e., such as second diode 612; see for example fig. 6, para. [0060]- [0063]) is connected to the second pad (i.e., such as second pad 302; see for example fig. 6, para. [0060]- [0063]). Regarding claim 2 , Dornbusch discloses the ESD protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]); wherein the first inductor (i.e., such as first inductor 116; see for example fig. 6, para. [0060]- [0063]), the second inductor (i.e., such as second inductor 118; see for example fig. 6, para. [0060]- [0063]), and the third inductor (i.e., such as third inductor 608; see for example fig. 6, para. [0060]- [0063]) construct a three-terminal inductor (i.e., such as three-terminal inductor 604, 606, 609; see for example fig. 6, para. [0060]- [0063]) having a common node (i.e., such as common node 120; see for example fig. 6, para. [0060]- [0063]), and the third inductor (i.e., such as third inductor 608; see for example fig. 6, para. [0060]- [0063]) is connected to the first diode (i.e., such as first diode 610; see for example fig. 6, para. [0060]- [0063]) and the second diode (i.e., such as second diode 612; see for example fig. 6, para. [0060]- [0063]). Regarding claim 6 , Dornbusch discloses the ESD protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]); further comprising an input/output pad (i.e., such as input/output pad 604; see for example fig. 6, para. [0060]- [0063]) configured to receive (i.e., such as configured to receive via pin 604; see for example fig. 6, para. [0060]- [0063]) a signal (i.e., such as signal at pin 604; see for example fig. 6, para. [0060]- [0063]) and transmit (i.e., such as transmit via pin 604; see for example fig. 6, para. [0060]- [0063]) the signal (i.e., such as signal at pin 604; see for example fig. 6, para. [0060]- [0063]) to the equalizing circuit (i.e., such as equalizing circuit 116, 118, 608; see for example fig. 6, para. [0060]- [0063]), wherein the input/output pad (i.e., such as input/output pad 604; see for example fig. 6, para. [0060]- [0063]) is connected in series (i.e., such as connected in series via pin 604; see for example fig. 6, para. [0060]- [0063]) with the first inductor (i.e., such as first inductor 116; see for example fig. 6, para. [0060]- [0063]). Regarding claim 7 , Dornbusch discloses the ESD protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]); further comprising an input/output pad (i.e., such as input/output pad 606; see for example fig. 6, para. [0060]- [0063]) configured to receive (i.e., such as configured to receive via pin 606; see for example fig. 6, para. [0060]- [0063]), from the equalizing circuit (i.e., such as equalizing circuit 116, 118, 608; see for example fig. 6, para. [0060]- [0063]), a signal (i.e., such as signal at pin 606; see for example fig. 6, para. [0060]- [0063]), which is to be output (i.e., such as output at pin 606; see for example fig. 6, para. [0060]- [0063]), wherein the input/output pad (i.e., such as input/output pad 606; see for example fig. 6, para. [0060]- [0063]) is connected in series (i.e., such as connected in series via pin 606; see for example fig. 6, para. [0060]- [0063]) with the second inductor (i.e., such as second inductor 118; see for example fig. 6, para. [0060]- [0063]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Dornbusch (US Publication No. 20070133137) in view of Yuan et al (US Publication No. 20190123551) . Regarding claim 3 , Dornbusch discloses the ESD protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]). Dornbusch does not explicitly disclose wherein the diode circuit further comprises a first variable resistor, and the first variable resistor is connected in parallel with the first diode. Yuan discloses an ESD protection circuit (i.e., see for example fig. 4, para. [0029]- [0032]); wherein the diode circuit (i.e., such as the diode circuit 410A; see for example fig. 4, para. [0029]- [0032]) further comprises a first variable resistor (i.e., such as first variable resistor 436A; see for example fig. 4, para. [0029]- [0032]), and the first variable resistor (i.e., such as first variable resistor 436A; see for example fig. 4, para. [0029]- [0032]) is connected in parallel (i.e., such as the top/first variable resistor in string 436A is connected in parallel with the top/first diode of string 410A, similarly, the bottom/second variable resistor in string 436A is connected in parallel with the bottom/second diode of string 410A; see for example fig. 4, para. [0029]- [0032]) with the first diode (i.e., such as the first diode top/first diode of string 410A; see for example fig. 4, para. [0029]- [0032]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the variable resistor in Dornbusch, as taught by Yuan, as it provides the advantage of optimizing the circuit design towards preventing circuit malfunctions, and establishing predictable DC biasing . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Dornbusch (US Publication No. 20070133137) in view of Crawley et al (US Publication No. 20090207538) . Regarding claim 9 , Dornbusch discloses the ESD protection circuit (i.e., such as ESD protection circuit 600; see for example fig. 6, para. [0060]- [0063]). Dornbusch does not explicitly disclose wherein at least one of the first diode and the second diode comprises a transient voltage suppressor (TVS) diode. Crawley discloses an ESD protection circuit (i.e., see for example fig. 13, para. [0101]); wherein at least one of the first diode (i.e., such as the first diode in diodes 1360; see for example fig. 13, para. [0101]) and the second diode (i.e., such as the second diode in diodes 1360; see for example fig. 13, para. [0101]) comprises a transient voltage suppressor (TVS) diode (i.e., such as transient voltage suppressor (TVS) diodes 1360; for instance, referring to FIG. 13, a schematic block diagram illustrates an example of an ESD protection implementation 1300 that uses external transient voltage suppression (TVS) diodes 1360 to supply ESD protection; see for example fig. 13, para. [0101]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the TVS diodes in Dornbusch, as taught by Crawley, as it provides the advantage of optimizing the circuit design towards absorbing and diverting high-voltage spikes away from sensitive circuitries and preventing permanent hardware failure while maintaining normal circuit performance . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10 , Dornbusch teaches the invention set forth above. However, Dornbusch does not particularly teach wherein at least one of inductances of the first inductor, the second inductor, and the third inductor and coupling coefficients between two of the first inductor, the second inductor, and the third inductors is adjustable. Hence claim 10 will be deemed allowable if rewritten in an independent form. Claims 4-5, 8 and 11-20 are not elected . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838 Application/Control Number: 18/788,595 Page 2 Art Unit: 2838 Application/Control Number: 18/788,595 Page 3 Art Unit: 2838 Application/Control Number: 18/788,595 Page 4 Art Unit: 2838 Application/Control Number: 18/788,595 Page 5 Art Unit: 2838 Application/Control Number: 18/788,595 Page 6 Art Unit: 2838 Application/Control Number: 18/788,595 Page 7 Art Unit: 2838
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