DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication filed on 07/30/2024. Claims 1 – 20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-4, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. U.S. patent No. 10,608,655.
Regarding claim 1. Fig. 5 of Li et al. discloses a method of calibrating a residue amplifier (RGA 116; Col. 1 lines 34-36) in a pipelined analog-to-digital converter (Col. 9 lines 37-38), comprising: obtaining a first calibrated gain (Col. 9 lines 59-60) of a residue amplifier (116) that amplifies a first residue voltage (Col. 9 lines 59-60), which is output from a capacitive digital-to-analog converter (112; see Fig. 2) of a first stage (Col. 9 lines 40-42) of the pipelined ADC (Col. 9 lines 37-38), to a voltage output (first output voltage of 116) corresponding to a first output code (D1) of a second stage (162, 164) of the pipelined ADC (Col. 9 lines 37-38); obtaining a second calibrated gain (Col. 9 lines 62-64) of the residue amplifier (119) that amplifies a second residue voltage (Col. 9 lines 62-64), which is output from the CDAC (DAC 112) of the first stage of the pipelined ADC (Col. 9 lines 40-42), to a voltage (second voltage output of 116 ) corresponding to a second output code (D2) of the second stage (162, 164) of the pipelined ADC (Col. 9 lines 40-42); and determining a final calibrated gain (determining 166 and CAL ENGINE) of the residue amplifier (RGA 116, Col. 1 lines 34-36) based on the first calibrated gain (Col. 9 lines 59-60) and the second calibrated gain (Col. 9 lines 62-64).
Regarding claim 2. The method of claim 1, Fig. 10 and Fig. 11 of Li et al. further discloses wherein the first residue voltage (Col. 9 lines 59-60) is a positive voltage (VREFP) and the second residue voltage (Col. 9 lines 62-64) is a negative voltage (VREFN).
Regarding claim 3. The method of claim 2, Fig. 3 of Li et al. further discloses wherein the first residue voltage (Col. 9 lines 59-60) corresponds to 1 least significant bit (LSB b0 connected to positive reference Vrp) and the second residue voltage (Col. 9 lines 62-64) corresponds to -1 LSB (LSB b0 connected to negative reference Vrn)
Regarding claim 4. The method of claim 1, Fig. 5 further discloses wherein determining the final calibrated gain (determining 166 and CAL ENGINE) comprises calculating an average (Col. 9 lines 15-17) of the first calibrated gain (Col. 9 lines 59-60) and the second calibrated gain (Col. 9 lines 62-64).
Regarding claim 15. Fig. 5 of Li et al. discloses an apparatus (160) for calibrating a residue amplifier (RGA 116; Col. 1 lines 34-36) in a pipelined analog-to-digital converter (Col. 9 lines 37-38), the apparatus (160) being a controller (Col. 3 lines 50-55) , comprising: a memory (Co. 14 lines 50-60); and at least one processor (Col. 14 lines 50-60) coupled to the memory (Col. 14 line 50-60) and configured to: obtaining a first calibrated gain (Col. 9 lines 59-60) of a residue amplifier (116) that amplifies a first residue voltage (Col. 9 lines 59-60), which is output from a capacitive digital-to-analog converter (112; see Fig. 2) of a first stage (Col. 9 lines 40-42) of the pipelined ADC (Col. 9 lines 37-38), to a voltage output (first output voltage of 116) corresponding to a first output code (D1) of a second stage (162, 164) of the pipelined ADC (Col. 9 lines 37-38); obtaining a second calibrated gain (Col. 9 lines 62-64) of the residue amplifier (119) that amplifies a second residue voltage (Col. 9 lines 62-64), which is output from the CDAC (DAC 112) of the first stage of the pipelined ADC (Col. 9 lines 40-42), to a voltage (second voltage output of 116 ) corresponding to a second output code (D2) of the second stage (162, 164) of the pipelined ADC (Col. 9 lines 40-42); and determining a final calibrated gain (determining 166 and CAL ENGINE) of the residue amplifier (RGA 116, Col. 1 lines 34-36) based on the first calibrated gain (Col. 9 lines 59-60) and the second calibrated gain (Col. 9 lines 62-64).
Regarding claim 16. The apparatus of claim 15, Fig. 10 and Fig. 11 of Li et al. further discloses wherein the first residue voltage (Col. 9 lines 59-60) is a positive voltage (VREFP) and the second residue voltage (Col. 9 lines 62-64) is a negative voltage (VREFN).
Regarding clam 17. The apparatus of claim 16, Fig. 3 of Li et al. further discloses wherein the first residue voltage (Col. 9 lines 59-60) corresponds to 1 least significant bit (LSB b0 connected to positive reference Vrp) and the second residue voltage (Col. 9 lines 62-64) corresponds to -1 LSB (LSB b0 connected to negative reference Vrn)
Regarding claim 18. The apparatus of claim 15, Fig. 5 further discloses wherein determining the final calibrated gain (determining 166 and CAL ENGINE) comprises calculating an average (Col. 9 lines 15-17) of the first calibrated gain (Col. 9 lines 59-60) and the second calibrated gain (Col. 9 lines 62-64).
Regarding claim 20. Fig. 5 of Li et al discloses a computer-readable medium storing computer executable code for operation of a controller (Co. 14 lines 50-60), comprising code to: obtaining a first calibrated gain (Col. 9 lines 59-60) of a residue amplifier (116) that amplifies a first residue voltage (Col. 9 lines 59-60), which is output from a capacitive digital-to-analog converter (112; see Fig. 2) of a first stage (Col. 9 lines 40-42) of the pipelined ADC (Col. 9 lines 37-38), to a voltage output (first output voltage of 116) corresponding to a first output code (D1) of a second stage (162, 164) of the pipelined ADC (Col. 9 lines 37-38); obtaining a second calibrated gain (Col. 9 lines 62-64) of the residue amplifier (119) that amplifies a second residue voltage (Col. 9 lines 62-64), which is output from the CDAC (DAC 112) of the first stage of the pipelined ADC (Col. 9 lines 40-42), to a voltage (second voltage output of 116 ) corresponding to a second output code (D2) of the second stage (162, 164) of the pipelined ADC (Col. 9 lines 40-42); and determining a final calibrated gain (determining 166 and CAL ENGINE) of the residue amplifier (RGA 116, Col. 1 lines 34-36) based on the first calibrated gain (Col. 9 lines 59-60) and the second calibrated gain (Col. 9 lines 62-64).
Allowable Subject Matter
5. Claims 5-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: amplifying, by the residue amplifier, a third residue voltage output from the CDAC of the first stage of the pipelined ADC using the final calibrated gain to obtain a third amplified residue voltage; determining a third output code of the second stage of the pipelined ADC corresponding to the third amplified residue voltage; amplifying, by the residue amplifier, a fourth residue voltage output from the CDAC of the first stage of the pipelined ADC using the final calibrated gain to obtain a fourth amplified residue voltage; determining a fourth output code of the second stage of the pipelined ADC corresponding to the fourth amplified residue voltage; and determining an offset of the residue amplifier based on the third output code and the fourth output code.
6. Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the at least one processor is further configured to: amplify, by the residue amplifier, a third residue voltage output from the CDAC of the first stage of the pipelined ADC using the final calibrated gain to obtain a third amplified residue voltage; determine a third output code of the second stage of the pipelined ADC corresponding to the third amplified residue voltage; amplify, by the residue amplifier, a fourth residue voltage output from the CDAC of the first stage of the pipelined ADC using the final calibrated gain to obtain a fourth amplified residue voltage; determine a fourth output code of the second stage of the pipelined ADC corresponding to the fourth amplified residue voltage; and determine an offset of the residue amplifier based on the third output code and the fourth output code.
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/11/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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