Detailed Action
1Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 08/22/2023 and 01/10/24. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0110072 and KR10-2024-0004487 applications as required by 37 CFR 1.55.
Therefore, the foreign priority dates have not been perfected because the certified copies have not been filed.
However, even in comparison to the earliest foreign priority date (08/22/2023) of the instant application, the prior art (Jin, et al., “A 4nm 16Gb/s/pin Single-Ended PAM4 parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization", ISSCC 2023, Session 28, High-Density Memories and High-Speed Interface, 28.3, 5 pages) was published on 02/19/2023, prior to the earliest foreign priority date but within one year from the earliest foreign priority date. However, the prior art has 10 authors/inventors and the instant application has 6 inventors. Only 4 of the inventors are common/shared between the instant application and the prior art. Therefore, the inventorships of the instant application and the prior art are different. The 102(b)(1), specifically 102(b)(1)(A) exception does not apply. The prior art is applied as 102(a)(1) reference (see rejection below)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4,15 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(i) Claims 4 and 15 recites “- - -wherein the edge adjustment circuit is configured to adjust the falling edge timing and the rising edge timing by advancing the same by an adjustment timing value.” It is not clear what is meant by “by advancing the same by an adjustment timing value”.
For examination purposes, Examiner interprets this as “-- - adjust the falling edge timing and the rising edge timing by a same adjustment timing value”.
(ii) Claim19 recites, “wherein the transmitter is configured to adjust the falling edge timing of the encoded signal corresponding to the most significant bit and the rising edge timing of the encoded signal corresponding to the least significant bit by advancing the same by an adjustment timing value”. It is not clear what is meant by “- - - by advancing the same by an adjustment timing value”.
For examination purposes, Examiner interprets this as “-- - by a same adjustment timing value”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 11, 17,18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin, et al. ("A 4nm 16Gb/s/pin Single-Ended PAM4 parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization", ISSCC 2023, Session 28, High-Density Memories and High-Speed Interface, 28.3, 5 pages) (See IDS).
With regards to claim 1, A transmitter (see title, Transceiver with switching-jitter compensation and transmitter optimization), comprising:
an encoder configured to encode an input signal representable by X levels, where X is a natural number of 3 or more, (See Jin et al, page 404, col. 1, left side, last paragraph, TX DQ generates and transmits PAM4 signals Figure 28.3.2(top-right) shows the TX DQ block diagram. Three identical thermometer output stages are used to obtain a high ratio of level mismatch (RLM). The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600 Figure (center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance), and output a plurality of encoded signals forming a multi-bit binary number including a most significant bit and a least significant bit; (A source-synchronous clock signal (DQS) is used to sample the data. In PAM4 mode
the Gray-coded 2b data (*MSB and *LSB) are obtained from the serializer, which is
implemented in the synthesized PHY, and provided to a TX I/O circuit (TX DQ). TX DQ
generates and transmits PAM4 signals, the Gray-coded 2b data being the claimed
multi-bit binary number)
an edge adjustment circuit configured to generate a plurality of adjusted encoded signals by adjusting a falling edge timing of a first one of the encoded signals corresponding to the most significant bit, and adjusting a rising edge timing of a second one of the encoded signals corresponding to the least significant bit; and ( See Jin et al, page 404, col. 1, left side, third paragraph, In a conventional RX, three comparators convert a PAM4 signal into thermometer-coded signals (DH, DM, and DL), and the thermometer-to-binary (T2B) decoder converts them into a 2b output (MSB and LSB). In the proposed RX, the SWJ of the thermometer signals are compensated by the proposed SWJC circuit before being converted into 2b output Considering the DH and its SWJ (SWJ_H), the falling edges come earlier than the rising edges, and vice-versa DL and it's SWJ (SWJ_L). SWJC adjusts the transitions of the thermometer signals so that the falling edges and rising edges are aligned. In the case of DH, the falling edges would be delayed until the
leftmost falling edge crosses the leftmost rising edge)
a driver circuit configured to generate and output an output signal having the X levels, based on the plurality of adjusted encoded signals (See Jin et al, page 404, col. 1, left side, last paragraph, The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600. The TX performs a 1-tap FS-FFE using a tap spacing (At) of 0.8UI, and a 3b controllable C-peaking driver is used. Figure 8.3.2(center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance).
With regards to claim 2, The transmitter of claim 1, wherein the encoder is configured to encode the input signal in a thermometer code manner (See Jin et al, page 404, col. 1, left side, last paragraph, TX DQ generates and transmits PAM4 signals Figure 28.3.2(top-right) shows the TX DQ block diagram. Three identical thermometer output stages are used to obtain a high ratio of level mismatch (RLM). The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600 Figure (center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance)
With regards to claim 3, The transmitter of claim 1, wherein the falling edge timing includes transition times at which the plurality of encoded signals transition from a highest level among the x levels to remaining levels among the x levels, and the rising edge timing includes transition times at which the plurality of encoded signals transition from a lowest level among the x levels to remaining levels among the x levels (See in Jin, et al., page 404, col. 1, left side, third paragraph SWJC adjusts the transitions of the thermometer signals so that the falling edges and rising edges are aligned. In the case of DH, the falling edges would be delayed until the leftmost falling edge crosses the leftmost rising edge. Hence, the SWJC circuit generates jitter reduced thermometer
signals: DH1, DM1, and DL1).
With regards to claim 4, The transmitter of claim 1, wherein the edge adjustment circuit is configured to adjust the falling edge timing and the rising edge timing by advancing the same by an adjustment timing value (See in Jin, et al., page 404, col. 2, right side, first paragraph, In the SWJC circuit, the strength of each pull-up/down path is controlled by separate thermometer controls to control the transition time. Essentially, when the code goes up, the propagation delay of the rising edge (tRISE) decreases while that of falling edge (tFALL) increase)
With regards to claim 11, The transmitter of claim 1, wherein the driver circuit includes: a first driver configured to perform pull-up and pull-down operations according to a first adjusted encoded signal corresponding to the first one of the encoded signals corresponding to the most significant bit; a second driver configured to perform pull-up and pull-down operations according to a second adjusted encoded signal corresponding to a third one of the encoded signals corresponding to a middle bit of the multi-bit binary number; and a third driver configured to perform pull-up and pull-down operations according to a third adjusted encoded signal corresponding to the second one of the encoded signals corresponding to the least significant bit (See in Jin, et al, page 404, col. 2, right side, first paragraph In the SWJC circuit, the strength of each pull-up/down path is controlled by separate thermometer controls to control the transition time. Essentially, when the code goes up, the propagation delay of the rising edge (tRISE) decreases while that of falling edge (tFALL) increase, as shown by the simulation results)
With regards to claim 17, A data communication system comprising: a transmitter configured to output an output signal having x levels based on adjusting falling edge timing of an encoded signal corresponding to a most significant bit and rising edge timing of an encoded signal corresponding to a least significant bit among bits of a multi-bit binary number represented by a plurality of encoded signals encoded from an input signal represented by the x levels, where x is a natural number of 3 or more; , (See Jin et al, page 404, col. 1, left side, last paragraph, TX DQ generates and transmits PAM4 signals Figure 28.3.2(top-right) shows the TX DQ block diagram. Three identical thermometer output stages are used to obtain a high ratio of level mismatch (RLM). The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600 Figure (center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance) and
a receiver connected to the transmitter through a channel to receive the output signal and obtain the input signal from the output signal. (See in Jin, et al., page 404, col. 2, right side, first paragraph, The receiver side is anticipated in Jin, et al by The RX DQ on the receiver side converts the PAM4 signal into the transmitted binary data).
With regards to claim 18, The data communication system of claim 17, wherein the transmitter includes: an encoder configured to encode the input signal to generate the plurality of encoded signals; See Jin et al, page 404, col. 1, left side, last paragraph, TX DQ generates and transmits PAM4 signals Figure 28.3.2(top-right) shows the TX DQ block diagram. Three identical thermometer output stages are used to obtain a high ratio of level mismatch (RLM). The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600 Figure (center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance)
an edge adjustment circuit configured to adjust the falling edge timing of the encoded signal corresponding to the most significant bit and the rising edge timing of the encoded signal corresponding to the least significant bit; ( See Jin et al, page 404, col. 1, left side, third paragraph, In a conventional RX, three comparators convert a PAM4 signal into thermometer-coded signals (DH, DM, and DL), and the thermometer-to-binary (T2B) decoder converts them into a 2b output (MSB and LSB). In the proposed RX, the SWJ of the thermometer signals are compensated by the proposed SWJC circuit before being converted into 2b output Considering the DH and its SWJ (SWJ_H), the falling edges come earlier than the rising edges, and vice-versa DL and it's SWJ (SWJ_L). SWJC adjusts the transitions of the thermometer signals so that the falling edges and rising edges are aligned. In the case of DH, the falling edges would be delayed until the
leftmost falling edge crosses the leftmost rising edge)
and
a driver circuit configured to output the output signal (See Jin et al, page 404, col. 1, left side, last paragraph, The binary-to-thermometer converter (B2T) converts the Gray-coded binary signals to three thermometer-coded signals, DH, DM, and DL, and passes them to each output stage. Each output stage includes a segmented source-series terminated driver terminated to 600. The TX performs a 1-tap FS-FFE using a tap spacing (At) of 0.8UI, and a 3b controllable C-peaking driver is used. Figure 8.3.2(center-right) shows how the thermometer driver generates the four levels while maintaining the same impedance).
With regards to claim 20, The data communication system of claim 17, wherein the receiver includes: a comparison circuit configured to output a plurality of comparison signals each having two signal levels, based on comparing the output signal with a plurality of reference signals; an edge delay circuit configured to output a plurality of delayed comparison signals by delaying falling edge timing of a comparison signal corresponding to the most significant bit and rising edge timing of a comparison signal corresponding to the least significant bit among the plurality of comparison signals; and a decoder configured to obtain the input signal by decoding the plurality of delayed comparison signals. (See in Jin, et al Figure 28.3.1 shows a diagram of the proposed SWJC for a PAM4 RX. In a conventional RX, three comparators convert a PAM4 signal
into thermometer-coded signals (DH, DM, and DL), and the thermometer-
to-binary (T2B) decoder converts them into a 2b output (MSB and LSB). In
the proposed RX, the SWJ of the thermometer signals are compensated by
the proposed SWJC circuit before being converted into 2b output. Since
PAM4 eyes are asymmetrical in shape, the thermometer signals have
different SWJ)
Allowable Subject Matter
7. Claims 13, 14 and 16 are allowed.
8. The following is an examiner’s statement of reasons for allowance: Claims 13, 14 and 16 are allowable over prior art of record. The prior art of record failed to teach, alone or in combination, a transmitter comprising: an encoder configured to encode an input signal representable by x levels, where x is a natural number of 3 or more, and output a plurality of encoded signals representing a multi-bit binary number including a most significant bit, a middle bit, and a least significant bit; an edge adjustment circuit configured to generate a plurality of adjusted encoded signals by adjusting a falling edge timing of a first one of the encoded signals corresponding to the most significant bit and a rising edge timing of a second one of the encoded signals corresponding to the least significant bit by a first adjustment timing value, and adjusting edge timing of a third one of the encoded signals corresponding to the middle bit by a second adjustment timing value different from the first adjustment timing value; and a driver circuit configured to generate and output an output signal having the x levels based on the plurality of adjusted encoded signals as recited in claim 13 and other limitations as recited in claims 14 and 16.
9. Claims 5-9, 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome 112(b) rejection above..
10. The following is a statement of reasons for the indication of allowable subject matter: none of the prior arts cited alone or in combination provides the motivation to teach the transmitter of claim 1, wherein the x levels include a highest level, a first intermediate level, a second intermediate level lower than the first intermediate level, and a lowest level as recited in claim 5;
The transmitter of claim 5, wherein the edge adjustment circuit is configured to adjust the falling edge timing and the rising edge timing such that a first intersection point between a (4-1)-th transition from the highest level to the lowest level and a (1- 4)-th transition from the lowest level to the highest level is located later in an eye diagram representing a plurality of transitions in a time domain than a second intersection point between a (3-1)-th transition from the first intermediate level to the lowest level and a (2-4)-th transition from the second intermediate level to the highest level as recited in claim 6;
The transmitter of claim 6, wherein the edge adjustment circuit is configured to adjust the falling edge timing and the rising edge timing such that the (4-1)-th transition is located later in the time domain than the (3-1)-th transition as recited in claim 7;
The transmitter of claim 7, wherein the edge adjustment circuit is configured to adjust the falling edge timing and the rising edge timing such that the (1-4)-th transition occurs later than the (2-4)-th transition. as recited in claim 8;
The transmitter of claim 1, wherein the multi-bit binary number represented by the plurality of encoded signals has a size of (x-1) bits as recited in claim 9;
The transmitter of claim 1, wherein the edge adjustment circuit includes: a first unit edge adjustment circuit configured to receive the first one of the encoded signals corresponding to the most significant bit and adjust the falling edge timing; a second unit edge adjustment circuit configured to adjust edge timing of a third one of the encoded signals corresponding to a middle bit of the multi-bit binary number; and a third unit edge adjustment circuit configured to receive the second one of the encoded signals corresponding to the least significant bit and adjust the rising edge timing as recited in claim 10;
The transmitter of claim 9, wherein the edge adjustment circuit includes (x-1) unit edge adjustment circuits as recited in claim 12;
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sudhakaran et al (US 12,347,508B2) discloses Encoding schemes to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HELENE E TAYONG whose telephone number is (571)270-1675. The examiner can normally be reached 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah S Wang can be reached at 571-272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HELENE E TAYONG/Primary Examiner, Art Unit 2631