DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 07/30/2024 & 02/12/2025 has been considered and placed in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (U.S. 2012/0154045).
Regarding claim 1, Tsai et al. (hereinafter, Ref~045) discloses (please see Figs. 1-12 and related text for details) a unit amplification circuit (11100 of Fig. 11) comprising:
a push-pull circuit (e.g., MP1/NN1 or MP2/MN2 of Fig. 11) having a transistor (e.g., MP1) with a gate connected to an input terminal (Sin2/Sn1 of Fig. 11);
a symmetrical circuit (MP2/MN2 or MP1/MN1 of Fig. 11) connected symmetrically to the push-pull circuit and configured to be turned off in a first operation mode (e.g., high gain mode) and turned on in a second operation mode (low gain mode); and
a path control circuit (see bypass stage from Fig. 11) connected to a drain of the transistor and configured to connect the drain and an output terminal (Sout of Figs. 11-12) in the first operation mode and to disconnect the drain and the output terminal in the second operation mode as seen/described throughout the disclosure, meeting claim 1.
Regarding claim 2, Ref~045 discloses the unit amplification circuit of claim 1, wherein the push-pull circuit comprises:
a first N-type transistor (see those NMOS from Fig. 12) having a gate, connected to the input terminal through a first capacitor (see coupling capacitor disposed between Sin and said NMOS), and a source grounded as seen from Fig. 12; and
a first P-type transistor (see PMOS from Fig. 12) having a gate, connected to the input terminal through a second capacitor (see coupling capacitor disposed between Sin and said PMOS), and a source from which a power supply voltage (see power supply from Fig. 12) is supplied, wherein the transistor with a gate connected to the input terminal is one of the first N-type transistor or the first P-type transistor as seen, meeting claim 2.
Regarding claim 3, Ref~045 discloses the unit amplification circuit of claim 2, wherein the symmetrical circuit comprises:
a second N-type transistor (see NMOS from Fig. 12 for details) connected (in parallel) symmetrically to the first N-type transistor and configured to be turned off in the first operation mode (during high gain mode) and turned on in the second operation mode (during low gain mode); and
a second P-type transistor (see PMOS from Fig. 12 for details) connected (in parallel) symmetrically to the first P-type transistor and configured to be turned off in the first operation mode and turned on in the second operation mode as described throughout the disclosure, meeting claim 3.
Regarding claim 5, Ref~045 discloses the unit amplification circuit of claim 3, wherein the path control circuit comprises:
a third N-type transistor (see NMOS from the loading stage from Figs. 11-12) having a source connected to a drain of the first N-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode; and
a third P-type transistor (see NMOS from the loading stage from Figs. 11-12) having a source connected to a drain of the first P-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode, meeting claim 5.
Regarding claim 6, Ref~045 discloses the unit amplification circuit of claim 1, further comprising:
a first compensation circuit (11200 and/or 11300 of Fig. 11) connected to the input terminal and configured to compensate for an impedance change defined on the input terminal, from an input impedance in the first operation mode to an input impedance the second operation mode, meeting claim 6.
Regarding claim 10, Ref~045 discloses the unit amplification circuit of claim 1, wherein the push-pull circuit is configured to amplify an input signal applied to the input terminal and output the amplified signal to the output terminal, in the first operation mode (high gain mode), and to be deactivated in the second operation mode (low gain mode) as descried throughout the disclosure, meeting claim 10.
Regarding claim 11, Ref~045 discloses (please see Figs. 1-12 and related text for details) an amplifier (e.g., 11100 of Fig. 11) comprising:
a plurality of unit amplification circuits (see driving stages), each configured to operate with a respective gain in a first operation mode (high gain mode) and with a different respective gain in a second operation mode (low gain mode), wherein, each of the plurality of unit amplification circuits (MP1/MN1 and MP2/MN2 of Figs. 11-12) comprises:
a push-pull circuit having a transistor (PMOS or NMOS of Fig. 12) with a gate connected to an input terminal (SIN of Fig. 12);
a symmetrical circuit (another PMOS or NMOS of Fig. 12) connected (in parallel) symmetrically to the push-pull circuit and configured to be turned off in the first operation mode and turned on in the second operation mode; and
a path control circuit (see bypass stage from Fig. 11) connected to a drain of the transistor and configured to connect the drain to an output terminal in the first operation mode and to disconnect the drain from the output terminal in the second operation mode, meeting claim 11.
Regarding claim 12, Ref~045 discloses the amplifier of claim 11, wherein the input terminal and the output terminal are commonly connected to the plurality of unit amplification circuits as seen from Figs. 11-12, meeting claim 12.
Regarding claim 13, Ref~045 discloses the amplifier of claim 11, wherein each of the plurality of unit amplification circuits is configured to amplify an input signal (Sin of Figs. 11-12) applied to the input terminal and output the amplified signal to the output terminal, in the first operation mode as seen/described from embodiments of Figs. 11-12, meeting claim 13.
Regarding claim 14, Ref~045 discloses the amplifier of claim 11, further comprising: an impedance matching circuit (11200 and/or 11300 of Figs. 11-12) connected to the input terminal for impedance matching, meeting claim 14.
Regarding claim 15, Ref~045 discloses the amplifier of claim 11, wherein:
the push-pull circuit comprises:
a first N-type transistor (see the first NMOS from Figs. 11-12) having a gate, connected to the input terminal through a first capacitor (see coupling capacitor of Fig. 12 for details), and a source grounded; and
a first P-type transistor (see the first PMOS from Figs. 11-12) having a gate, connected to the input terminal through a second capacitor (see coupling capacitor of Fig. 12 for details), and a source from which a power supply voltage (see power supply from Fig. 12) is supplied, wherein the transistor with a gate connected to the input terminal is one of the first N-type transistor or the first P-type transistor; and
the symmetrical circuit (see the mirror/parallel driving stage with bypass stage from Figs. 11-12 for details) comprises:
a second N-type transistor (see the second NMOS from Figs. 11-12 for details) connected symmetrically to the first N-type transistor and configured to be turned off in the first operation mode and turned on in the second operation mode; and
a second P-type transistor (see the second PMOS from Figs. 11-12 for details) connected symmetrically to the first P-type transistor and configured to be turned off in the first operation mode and turned on in the second operation mode, meeting claim 15.
Regarding claim 16, Ref~045 discloses the amplifier of claim 15, wherein: the path control circuit comprises:
a third N-type transistor (see the NMOS from loading stage of Figs. 11-12 for details) having a source connected to a drain of the first N-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode; and
a third P-type transistor (see the PMOS from loading stage of Fig. 11-12 for details) having a source connected to a drain of the first P-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode, meeting claim 16.
Regarding claim 17, Ref~045 discloses the amplifier of claim 11, wherein: each of the plurality of unit amplification circuits further comprises: a first compensation circuit (11200 and/or 11300 of Figs. 11-12) connected to the input terminal and configured to compensate for an impedance change defined on the input terminal in the second operation mode, meeting claim 17.
Regarding claims 18-20, limitations from these claims can be rejected in the same manner as described above, since all limitations with similar language are being presented here including the generically claimed receiving circuit having mixer with local oscillator, since Ref~045 is part of a wireless receivers as described in paragraph [0005], thus said mixer with LO and baseband filter would be required to at least provide up-converting/down-converting between antenna and baseband, meeting claims 18-20.
Allowable Subject Matter
Claim 4 and 7-9 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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