DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaltalioglu (US 20110074033 A1).
Regarding claim 1, Kaltalioglu teaches a method (method, [0009], Fig 9) for singulating semiconductor dies (2, Fig 1b) from a wafer (W: wafer, [0012], Fig 1), the method comprising:
forming a metallic layer (ML: 57/58, Fig 8) on (shown ion) an upper surface (3T: top surface of 3) of the wafer (W) and over (shown over) at least a portion of planned scribe regions (21) of the wafer (W);
patterning (shown patterned) the metallic layer (ML) to form a plurality of isolated lines (57/58) over (shown over) the planned scribe regions (21) of the wafer (W), wherein
adjacent isolated lines (57/58) in the plurality of isolated lines (57/58) are separated (shown separated) by a distance (D1: horizontal distance between 57 and 58);
depositing a passivation material (4) over (shown over) the plurality of isolated lines (57/58), wherein
the distance (D1) between each of the adjacent isolated lines (57/58) small enough to create a gap (G: gap between horizontally adjacent portions of 4 in Fig 8c) in the passivation material (4) between (shown between) each of the adjacent isolated lines (57/58); and
stealth dicing (SD: laser cutting, [0036]) the planned scribe regions (21) of the wafer (W),
wherein stealth dicing (SD) includes:
directing a laser (laser cutting, [0036]) toward a lower surface (1B: bottom of 1) of the wafer (W) to form one or more stress regions (1M: horizontal center of 1) proximate (shown proximate) the lower surface (1B) along the planned scribe regions (21); and
causing one or more cracks (cracks, [0025]) to propagate (causing cracks; paragraphs [0024-0025] disclose minimizing any propagation of cracks formed as the laser cuts the wafer because the laser cutting would create a crack that is intended to propagate from the stress region to the isolated lines) from the one or more stress regions (1M) toward the plurality of isolated lines (57/58) on the upper surface (1T) of the wafer (W).
Regarding claim 2, Kaltalioglu teaches the method of claim 1 and goes on to teach further comprising etching (etched; deposited and patterned; plasma etch, [0050]) the passivation material (4, Fig 8) and at least a portion of the upper surface (3T) of the wafer (W) to form a trench (10) in the upper surface (3T) between (shown between) each of the adjacent isolated lines (57/58).
Regarding claim 4, Kaltalioglu teaches the method of claim 1 and goes on to teach wherein the upper surface (3T, Fig 8) of the wafer (W) has a plurality of die regions (2), wherein
the planned scribe regions (21) are positioned in a grid shape (shown in a grid) around (shown around) the plurality of die regions (2), and wherein
the method (method) further comprises forming one or more metallization layers (3) on (shown on) the upper surface (3T) of the wafer (W) and over (shown over) the plurality of die regions (2).
Regarding claim 5, Kaltalioglu teaches the method of claim 4 and goes on to teach wherein at least one of the one or more metallization layers (3, Fig 8) is coplanar (shown coplanar) with at least a portion of the plurality of isolated lines (57/58).
Regarding claim 7, Kaltalioglu teaches the method of claim 1 and goes on to teach wherein the planned scribe regions (21, Fig 8) have a width (D2: width of 21), and wherein
the plurality of isolated lines (57/58) are positioned over about 60 percent (shown over approximately 60%) of the width (D2).
Regarding claim 8, Kaltalioglu teaches a semiconductor device (W: wafer, [0012], Fig 1), comprising:
a base substrate (1) having an upper surface (1T: top of 1) that includes a central region (CA: central region including chips 2) and a peripheral region (PA: peripheral region around the outside of the chips 2);
a circuitry layer (3) carried (shown carried) by the central region (CA) of the upper surface (1T), wherein
the circuitry layer (3) includes one or more metallization layers (m1-mt, [0032]) establishing signal route lines (connect various active devices on the chip, [0032]) for the semiconductor device (W); and
one or more isolated lines (57/58) carried by (shown carried by) the peripheral region (PA) of the upper surface (1T), wherein
the one or more isolated lines (57/58) are at least partially coplanar (shown coplanar) with the circuitry layer (3).
Regarding claim 9, Kaltalioglu teaches the device of claim 8 and goes on to teach wherein the one or more isolated lines (57/58, Fig 8) includes two or more isolated lines (57/58), wherein
the two or more isolated lines (57/58) are positioned in (shown in) a passivation layer (4) carried (shown carried) by the upper surface (1T), and wherein
the passivation layer (4) includes a gap (G: gap between horizontally adjacent portions of 4 in Fig 8c) positioned between (shown between) each pair of adjacent isolated lines (57/58) in the two or more isolated lines (57/58).
Regarding claim 10, Kaltalioglu teaches the device of claim 9 and goes on to teach wherein the passivation layer (4, Fig 8) further includes a concave shape (shown concave) along at least a portion of an outer sidewall (4SW: sidewall of 4 above 57/58 in Fig 8c) of the passivation layer (4).
Regarding claim 11, Kaltalioglu teaches the device of claim 8 and goes on to teach wherein the one or more isolated lines (57/58, Fig 8) includes two or more isolated lines (57/58), wherein
the circuitry layer (3) is a third circuitry layer (m3, Fig 1c), and
wherein the semiconductor device (W) further comprises:
a first circuitry layer (m1) carried (shown carried) by the upper surface (1T) of the base substrate (1) beneath (shown beneath) the third circuitry layer (m3); and
a second circuitry layer (m2) carried (shown carried) by the upper surface (1T) of the base substrate (1) over (shown over) the first circuitry layer (m1) and beneath (shown beneath) the third circuitry layer (m3), wherein
the second circuitry layer (m2) includes a top surface (m2T: top of m2), wherein
the top surface (m2T) of the second circuitry layer (m2) includes one or more trenches (10) positioned between (shown between, Fig 8) each pair of adjacent isolated lines (57/58) in the two or more isolated lines (57/58).
Regarding claim 12, Kaltalioglu teaches the device of claim 11 and goes on to teach wherein the top surface (m2T, Fig 1c) of the second circuitry layer (m2) further includes a portion of a trench (10) along (shown along) a peripheral-most edge (11R: outer edge of periphery of metal layers) of the second circuitry layer (m2).
Regarding claim 13, Kaltalioglu teaches the device of claim 8 and goes on to teach wherein the circuitry layer (3, Fig 1c) is an uppermost circuitry layer (mt: top metallization layer of 3), wherein
the semiconductor device (W) further comprises a second uppermost circuitry layer (m5), wherein
the second uppermost circuitry layer (m5) includes one or more sacrificial components (11), and wherein
the one or more isolated lines (57/58, Fig 8) are at least partially vertically aligned (shown vertically aligned) with the sacrificial components (11).
Regarding claim 14, Kaltalioglu teaches the device of claim 8 and goes on to teach wherein none of the one or more isolated lines (57/58, Fig 8) is electrically coupled (shown with none electrically coupled) to another structure in the semiconductor device (W).
Regarding claim 16, Kaltalioglu teaches a semiconductor wafer (W: wafer, [0012], Fig 1), comprising:
a base substrate (1) having an upper surface (1T: top of 1) that includes a plurality of scribe regions (21) forming a grid (shown forming a grid) on (shown on) the upper surface (1T) and a circuitry region (2) in each open location in the grid;
a plurality of circuitry layers (3) carried (shown carried) by the upper surface (1T) of the base substrate (1), wherein
the plurality of circuitry layers (3) form a semiconductor die (2, chips, [0028]) in (shown in) each open location in the grid; and
a plurality of isolated lines (57/58, Fig 8) carried (shown carried) by the upper surface (1T) of the base substrate (1) over (shown over) at least a portion of the plurality of scribe regions (21).
Regarding claim 17, Kaltalioglu teaches the wafer of claim 16 and goes on to teach further comprising a crack (cracks, [0025]) extending (extending; paragraphs [0024-0025] disclose minimizing any propagation of cracks formed as the laser cuts the wafer because the laser cutting would create a crack that is intended to propagate from the bottom of the wafer to the top) from a lower surface (1B: bottom of 1) of the base substrate (1) to a top surface (3T: top of 3) an uppermost circuitry layer (mt) from the plurality of circuitry layers (3) and between (shown between) two adjacent isolated lines (57/58) from the plurality of isolated lines (57/58).
Regarding claim 18, Kaltalioglu teaches the wafer of claim 16 and goes on to teach wherein the plurality of isolated lines (57/58, Fig 8) is at least partially coplanar (shown coplanar) with an uppermost circuitry layer (mt, Fig 1c) from the plurality of circuitry layers (3).
Regarding claim 19, Kaltalioglu teaches the wafer of claim 16 and goes on to teach wherein the plurality of circuitry layers (3, Fig 1c) includes an uppermost circuitry layer (m5) and a second uppermost circuitry layer (m4), wherein
the plurality of isolated lines (57/58, Fig 8) is carried (shown carried) by the second uppermost circuitry layer (m4), and wherein
a top surface (m4T: top of m4) of the second uppermost circuitry layer (m4) includes a trench (10) positioned between (shown between) each pair of adjacent isolated lines (57/58) from the plurality of isolated lines (57/58).
Regarding claim 20, Kaltalioglu teaches the wafer of claim 16 and goes on to teach wherein each of the plurality of isolated lines (57/58, Fig 8) is positioned in (shown in) a passivation material (4), and wherein
the passivation material (4) includes a gap (G: gap between horizontally adjacent portions of 4 in Fig 8c) positioned between (shown between) each pair of adjacent isolated lines (57/58) in the plurality of isolated lines (57/58).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu (US 20110074033 A1) as applied to claim 1 above, and further in view of Menath (US 20170084468 A1).
Regarding claim 3, Kaltalioglu teaches the method of claim 1, the plurality of isolated lines (57/58), and goes on to teach a portion (4C: portion of passivation 4 above 57/58) of the passivation material (4, Fig 8).
Kaltalioglu fails to explicitly teach depositing a polyimide over at least a portion of the passivation material corresponding to the plurality of isolated lines; and etching the passivation material not covered by the polyimide.
However, Menath teaches further comprising:
depositing a polyimide (512, Fig 5, polyimide, [0037]) over (over; when combined with Kaltalioglu the polyimide layer 512 of Menath would be deposited on top of the passivation 4 of Kaltalioglu) at least a portion of the passivation material corresponding (shown corresponding) to the plurality of isolated lines; and
etching (etching, [0113], Fig 6C) the passivation material not covered (shown not covered) by the polyimide (512).
Kaltalioglu and Menath are considered analogous to the claimed invention because both are from the same field of endeavor of methods of singulating semiconductor dies. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Kaltalioglu with the features of Menath to create a method depositing a polyimide over at least a portion of the passivation material corresponding to the plurality of isolated lines; and etching the passivation material not covered by the polyimide so the protecting layer may be configured to protect the at least one metallization during dicing (Menath, [0119]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kaltalioglu (US 20110074033 A1) as applied to claims 1 and 8 above, and further in view of Yamamoto (US 5900735 A).
Regarding claim 6, Kaltalioglu teaches the method of claim 1 and the distance (D1, Fig 8) between each of the adjacent isolated lines (57/58).
Kaltalioglu fails to explicitly teach the distance between each of the adjacent isolated lines is between 2 micrometers and 4 micrometers.
However, Yamamoto teaches wherein the distance between each of the adjacent isolated lines is between 2 micrometers and 4 micrometers (3 micrometers; several micrometers, [Col 1, Ln 31]).
Kaltalioglu and Yamamoto are considered analogous to the claimed invention because both are from the same field of endeavor of wires in semiconductors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Kaltalioglu with the features of Yamamoto to create a method wherein the distance between each of the adjacent isolated lines is between 2 micrometers and 4 micrometers because spacing between wires (described by Yamamoto as holes) as short as several micrometers result in the creation of voids which causes disconnection (Yamamoto, [Col 1, Ln 30-40]).
Regarding claim 15, Kaltalioglu teaches the device of claim 8 and goes on to teach wherein the one or more isolated lines (57/58, Fig 8) includes two or more isolated lines (57/58), and wherein
each pair of adjacent isolated lines (57/58) in the two or more isolated lines (57/58) is spaced apart (shown spaced apart) by a distance (D1: horizontal distance between 57 and 58).
Kaltalioglu fails to explicitly teach each pair of adjacent isolated lines in the two or more isolated lines is spaced apart by a distance between 2 micrometers and 4 micrometers.
However, Yamamoto teaches each pair of adjacent isolated lines in the two or more isolated lines is spaced apart by a distance between 2 micrometers and 4 micrometers (3 micrometers; several micrometers, [Col 1, Ln 31]).
Kaltalioglu and Yamamoto are considered analogous to the claimed invention because both are from the same field of endeavor of wires in semiconductors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Kaltalioglu with the features of Yamamoto to create a method wherein each pair of adjacent isolated lines in the two or more isolated lines is spaced apart by a distance between 2 micrometers and 4 micrometers because spacing between wires (described by Yamamoto as holes) as short as several micrometers result in the creation of voids which causes disconnection (Yamamoto, [Col 1, Ln 30-40]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Joshi (US 7087452 B2) - a1, metal wall around trench with gaps
Sugioka (US 20230090041 A1) - a1, stealth laser dicing and voids around metal lines in dicing region
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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