DETAILED ACTION
Status of Application
Claims 1-21 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The objection to claim 3 was not addressed in applicant’s argument. Claim 3 remains objected to because of the following informalities: Claim 3 is directed towards “according to the updated of the data structure” on page 3, line 1. The examiner believes this should amended to “according to the updated [[of the]] data structure.” Appropriate correction is required.
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered but they are not persuasive, for the reasons set forth below.
Applicant argues: (1) the core currently in the critical section directly designates the next core that will enter [remarks, p. 1]; (2) the designation is a “core- level, non-delegating, non-hierarchical, routing-aware successor designation mechanism” remarks, p. 1]; (3) “the lock-owning CPU executes the critical-section functions on behalf of losing CPUs” [remarks, p. 2]; (4) reference 1 does not teach “next-thread designation by the active core” [remarks, p. 2]; (5) reference 1 “actively teaches away from” the claimed mechanism [remarks, p. 2]; (6) the claimed invention requires “distributed, per-core execution with no delegation” [remarks, p. 2]; (7) reference 1 cannot be modified to behave like the claimed invention [remarks, pp. 2-3]; (8) reference 1 teaches away while the claimed invention expressly forbids delegation and mandates core-local execution [remarks, p. 3]; (9) the design goals of reference 2 and the claimed invention are mutually exclusive, and therefore reference 2 teaches away [remarks, p. 4]; (10) reference 2 cannot be modified to achieve applicant’s per-core scheme [remarks, pp. 4-5]; (11) reference 3 cannot be modified because reference 3 does not provide per-core routing, successor designation, cache-migration minimization, core-level serialization, any mechanism to determine the ‘next core’, any awareness of system topology; (12) the combined references do not render claim 1 obvious [remarks, pp. 6-7]; (13) claim 2 is non-obvious [remarks, p. 7]; (14) a POSITA would not combine references that contradict each other’s fundamental operation [remarks, p. 7].
The examiner respectfully disagrees with these arguments.
Regarding the first argument, applicant states that the above feature is “explicitly reflected in claim 1” [remarks, p. 1]. The examiner does not find any language in claim 1 that explicitly reflects “the core currently in the critical section directly designates the next core that will enter.” Claim 1 is reproduced below for reference:
A method for managing mutual exclusion access to a critical section in a multi-core processor, the multi-core processor processing managing steps comprising:
using a multicore-lock-unlock module that permits only one core of the multi-core processor to access a critical section at any given time; and
using a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time.
The examiner finds no mention of designating the next core that will enter and notes that the features upon which applicant relies (i.e., the core currently in the critical section directly designates the next core that will enter) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the second argument, the examiner notes that the features upon which applicant relies (i.e., core- level, non-delegating, non-hierarchical, routing-aware successor designation mechanism) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the third argument, the examiner argues that reference 1 does not require such language because claim 1 does not recite such language. The examiner finds no mention of the feature: “the lock-owning CPU executes the critical-section functions on behalf of losing CPUs,” recited in claim 1. Claim 1 is directed towards
permitting only one core of the multi-core processor to access a critical section at any given time; and using a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time. There is no mention of critical section functions on behalf of losing CPUs.
Regarding the fourth argument, the examiner notes that the features upon which applicant relies (i.e., next-thread designation by the active core) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the fifth argument, the examiner notes that the “mechanism” applicant refers to, is not recited in claim 1. The examiner notes that the features upon which applicant relies (i.e., next-thread designation by the active core) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Since next-thread designation by the active core, is not recited in claim 1, applicant’s argument in regards to “teaching away” is rendered moot.
Regarding the sixth argument, the examiner notes that the features upon which applicant relies (i.e., distributed, per-core execution with no delegation) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the seventh argument, applicant argues that reference 1 cannot be modified to fit the present invention because:
A thread’s local execution state cannot be moved across cores.
The examiner disagrees. The examiner argues that this reasoning is irrelevant because the prior are rejection under obviousness, is directed towards the limitation “a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time.” The examiner finds no correlation between: moving a thread’s local execution state across cores AND ensuring only one thread on the core of the multi-core processor can access the critical section at a time. The claimed limitation does not even mention moving execution state across cores. In fact, said limitation is directed towards ensuring “only one thread on the core of the multi-core processor can access the critical section at a time.”
Applicant argues that reference 1 cannot be modified to fit the present invention because:
Modern OS and hardware architectures bind thread-local state to a specific CPU [remarks, pp. 2-3].
Delegated execution breaks when the delegate cannot reproduce the current thread’s register-based local state exactly the problem here” [remarks, p. 3].
The examiner disagrees. The examiner does not see any relevance between the above bullet points and the claimed invention, specifically, the limitation rejected under Calciu. Again, the limitation recited in claim 1 and taught by Calciu is “ensures only one thread on the core of the multi-core processor can access the critical section at a time.” The examiner disagrees with applicant’s statement that “delegated execution breaks when the delegate cannot reproduce the current thread’s register-based local state exactly the problem here.” Nowhere in claim 1 does it recite “delegated execution” or reproducing a current thread’s local state. The examiner cited Calciu to teach “ensures only one thread on the core of the multi-core processor can access the critical section at a time” [Calciu, paragraph 53, “Each processor core may be a multi-threaded core, in some embodiments. For example, in one embodiment each processor core may be capable of concurrently executing eight hardware threads”; paragraphs 48-49, in this example, the method may include a thread acquiring a cluster-specific lock that is associated with a critical section of code or a shared resource (e.g., a lower-level lock for use in managing access to the critical section of code or shared resource by threads executing on the same cluster as the given thread). After acquiring the cluster-specific lock, the thread may acquire a global shared lock (i.e. a top-level lock) that protects the critical section of code or shared resource (e.g., that manages access to the critical section of code or shared resource by any and all of the threads executing on the clusters in the system, as in 120. The method may include the given thread executing the critical section of code or accessing the shared resource while it holds both the global shared lock and the cluster-specific lock, as in 130”; Once the given thread exits the critical section of code or no longer requires access to the shared resource, rather than merely releasing one or more of the locks it holds, the given thread may determine whether there is another thread executing on the same cluster as the given thread that desires the global shared lock (e.g., a thread that wishes to execute the critical section of code or access the shared resource that is protected by the global shared lock), as in 140. If so, shown as the positive exit from 140, the method may include the thread that holds the cluster-specific lock passing ownership of the cluster-specific lock to a next thread of the same cluster without releasing the global shared lock, as in 160. The next thread may then execute the critical section of code or access the shared resource while it holds the cluster-specific lock, as in 170. If there is no other thread executing on the same cluster as the given thread that wished to acquire the global shared lock, shown as the negative exit from 140, the method may include the thread holding the cluster-specific lock (in this case, the given thread) releasing the global shared lock and then the cluster-specific lock, as in 150”; hence only one thread can access the critical section at a time].
Claim 1 does not make any mention of thread state, context switches, or reproducing a current thread’s register-based local state. In addition, applicant provides no reasoning as to why Calciu’s cited portions do not teach the claimed invention or how Calciu combined with Ma, yields a modification that is incompatible. The examiner request clarification on exactly how Calciu, combined with Ma, yield a modification that is incompatible. In addition, the examiner request clarification on why the cited portions of Calciu are improper teachings of the limitation “ensures only one thread on the core of the multi-core processor can access the critical section at a time.
The examiner disagrees with applicant’s argument that the combination of references lacks any support and violates MPEP 2143.01. In fact, there is nothing in applicant’s response that addresses the motivation for combining the references (reproduced below for reference):
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Calciu in the method of Ma to implement, a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time, in order to reduce coherence traffic and improve aggregate performance [Calciu, paragraph 12].
Regarding the eighth argument, the examiner disagrees with applicant’s argument that reference 1 teaches away. Reference 1 does not constitute a teaching away because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). The examiner does not find any portion of Ma that criticizes, discredits, or otherwise discourages the claimed solution, hence Ma does not teach away. In addition, the examiner notes that the features upon which applicant relies (i.e., claimed invention expressly forbids delegation and mandates core-local execution) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the ninth argument, it has been held that "the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). Hence, reference 2 does no teach away since reference 2 does not criticize, discredit, or otherwise discourage the solution claimed.
Regarding the tenth argument, applicant asserts that for reference 2 to behave like the invention, one would need to remove the cluster lock, remove the global lock, rmove cohorting, rewrite the scheduling mechanism, and discard numa-local preference [remarks, pp. 4-5]. Applicant gives no reasoning as why these particular features would need to be removed in order to behave like the invention, only that they need to be removed. The examiner is not persuaded by such a general allegation, especially without supporting reasons as to why these features need to be removed and once removed, how Calciu will behave like the claimed invention. In addition, applicant argues “the claimed invention optimizes for per-core routing” [remarks, p. 5]. The examiner disagrees, as there is no mention in the claimed invention (claim 1) of “per-core routing.”
Regarding the eleventh argument, the examiner disagrees. Reference 3 does not have to provide any or all of per-core routing, successor designation, cache-migration minimization, core-level serialization, any mechanism to determine the ‘next core’, any awareness of system topology, because claim 1 is devoid of such features. It appears that applicant intends to import language from the specification into the claims, without actually claiming any of the features listed. "Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment." Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004). See also Liebel-Flarsheim Co. v. Medrad Inc., 358 F.3d 898, 906, 69 USPQ2d 1801, 1807 (Fed. Cir. 2004) (discussing recent cases wherein the court expressly rejected the contention that if a patent describes only a single embodiment, the claims of the patent must be construed as being limited to that embodiment); E-Pass Techs., Inc. v. 3Com Corp., 343 F.3d 1364, 1369, 67 USPQ2d 1947, 1950 (Fed. Cir. 2003) ("Interpretation of descriptive statements in a patent’s written description is a difficult task, as an inherent tension exists as to whether a statement is a clear lexicographic definition or a description of a preferred embodiment. The problem is to interpret claims ‘in view of the specification’ without unnecessarily importing limitations from the specification into the claims.").
Applicant argues that reference 3 offers no teaching relevant to the claimed successor-determination mechanism [remarks, p. 6]. The examiner notes that the claimed invention (claim 1), makes no mention of a “successor-determination mechanism.” The features upon which applicant relies (i.e., successor-determination mechanism) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the twelfth argument, the examiner disagrees with applicant. Applicant argues the examiner’s theory is that reference 1 provide “execution control” and reference 2 provides “priority or grouping.” This is factually incorrect. Firstly, provided in the Office Action is a prior art rejection under 35 USC 103. This is not a “theory.” The examiner requests, in detail, the portions of the Non-Final Rejection which leads applicant to believe, reference 1 provides “execution control.” The examiner also requests, in detail, the portions of the Non-Final Rejection which leads applicant to believe, reference 2 provides “priority or grouping.” Applicant argues references 1 and 2 provide paradigms that contradict each other and therefore, incompatible [remarks, p. 6]. Applicant provide no reasoning regarding this allegation. The examiner is not persuaded and maintains the prior art rejection. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant argues that reference 1 and 2 are incompatible and none suggest current core designates next core [remarks, p 6]. The examiner has addressed these arguments in the rebuttal above.
Regarding the thirteenth argument, applicant argues none of the references teach or suggest the features recited in claim 2. The examiner disagrees and refers applicant to the prior art rejection for claim 2.
Applicant argues that the references do not disclose core-level variable allocation, non-hierarchical per-core scheduling, and core-based execution or any mechanism preventing inter-core data flow.
The examiner notes that the features upon which applicant relies (i.e., core-level variable allocation, non-hierarchical per-core scheduling, and core-based execution or any mechanism preventing inter-core data flow) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the fourteenth argument, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, combining Ma with Calciu would lead to reduced coherence traffic and improved aggregate performance [Calciu, paragraph 12]. Applicant argues that reference 1 teaches toward centralizing execution, not distributing it. Reference 2 teaches toward NUMA-cluster hierarchy, not flat core-level routing. Reference 3 teaches toward spinning reduction, not cache-migration control. The examiner argues that “not distributing it,” “not flat core-level routing,” and “not cache-migration control” is irrelevant. Claim 1 is devoid of any language that recites distributing it, flat core-level routing, and cache-migration control. As mentioned above, obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (hereinafter Ma), US 20200134182 A1, in view of Calciu et al (hereinafter Calciu), US 20130290967 A1.
Referring to claim 1, Ma discloses a method for managing mutual exclusion access to a critical section in a multi-core processor, the multi-core processor processing managing steps comprising:
using a multicore-lock-unlock module that permits only one core of the multi-core processor to access a critical section at any given time [fig. 1, see multi-core processor comprising cores CPU0-CPUn; paragraphs 35, 47, 51-52, “When a thread runs on a first CPU, the first CPU may request for a lock to execute a critical section function associated with the thread on the shared data; the lock provides permission to update the shared data, and the critical section function updates the shared data. If the lock is successfully obtained, the thread may perform an update operation on the shared data. For example, if CPU1 obtains the lock, then the corresponding Thread 1 may update the shared data (Shared_Data). If the lock is occupied by a second CPU, the first CPU may set a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index”; CPU1 requests for a lock…In Step 406, when CPU1 determines that the lock has been occupied by another CPU, CPU1 sets the bit of the memory of the lock corresponding to the memory index associated with CPU1… After the corresponding bit of the memory of the lock is set, CPU1 just needs to wait. The critical section function that was to be executed by Thread1 running on CPU1 will be called and executed by CPU2; hence CPU1 requests a lock for access to a critical section. If a lock has been occupied by CPU2, the critical section is not executed by CPU1 and instead is executed by CPU2, thereby permitting only one core to access a critical section at any given time].
Ma discloses a thread on a core [fig. 2] but does not explicitly multiple thread on the core such that using a multithread-lock-unlock module ensures only one thread on the core of the multi-core processor can access the critical section at a time.
However, Calciu discloses a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time [paragraph 53, “Each processor core may be a multi-threaded core, in some embodiments. For example, in one embodiment each processor core may be capable of concurrently executing eight hardware threads”; paragraphs 48-49, in this example, the method may include a thread acquiring a cluster-specific lock that is associated with a critical section of code or a shared resource (e.g., a lower-level lock for use in managing access to the critical section of code or shared resource by threads executing on the same cluster as the given thread). After acquiring the cluster-specific lock, the thread may acquire a global shared lock (i.e. a top-level lock) that protects the critical section of code or shared resource (e.g., that manages access to the critical section of code or shared resource by any and all of the threads executing on the clusters in the system, as in 120. The method may include the given thread executing the critical section of code or accessing the shared resource while it holds both the global shared lock and the cluster-specific lock, as in 130”; Once the given thread exits the critical section of code or no longer requires access to the shared resource, rather than merely releasing one or more of the locks it holds, the given thread may determine whether there is another thread executing on the same cluster as the given thread that desires the global shared lock (e.g., a thread that wishes to execute the critical section of code or access the shared resource that is protected by the global shared lock), as in 140. If so, shown as the positive exit from 140, the method may include the thread that holds the cluster-specific lock passing ownership of the cluster-specific lock to a next thread of the same cluster without releasing the global shared lock, as in 160. The next thread may then execute the critical section of code or access the shared resource while it holds the cluster-specific lock, as in 170. If there is no other thread executing on the same cluster as the given thread that wished to acquire the global shared lock, shown as the negative exit from 140, the method may include the thread holding the cluster-specific lock (in this case, the given thread) releasing the global shared lock and then the cluster-specific lock, as in 150”; hence only one thread can access the critical section at a time].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Calciu in the method of Ma to implement, a multithread-lock-unlock module that ensures only one thread on the core of the multi-core processor can access the critical section at a time, in order to reduce coherence traffic and improve aggregate performance [Calciu, paragraph 12].
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma, in view of Calciu, as applied to claim 1 above, and further in view of Bliss, US 20070300226 A1.
Referring to claim 2, the modified Ma does not explicitly disclose the method for managing mutual exclusion access to the critical section in the multi-core processor according to claim 1, wherein when the thread currently running on the core that is allowed to access the critical section attempts to access the critical section but the currently running thread is not the designated next thread to access the critical section, the currently running thread relinquishes its right to access the critical section on the core that is allowed to access the critical section.
However, Bliss discloses wherein when the thread currently running on the core that is allowed to access the critical section attempts to access the critical section but the currently running thread is not the designated next thread to access the critical section [fig. 2, paragraphs 19-20, “If the difference exceeds a threshold value (250)” indicating the thread is not the designated next thread to access the critical section], the currently running thread relinquishes its right to access the critical section on the core that is allowed to access the critical section [paragraphs 19-20, 16, “If the difference exceeds a threshold value (250), the ticket lock implementation yields the remainder of its timeslice (260)”; “a waiting thread yields the remainder of its timeslice if it determines that the NowServing variable does not match its ticket value (Listing 1, line 80). Yielding the processor here frees processing cycles for use by other threads of execution, but may result in a context switch to another thread or process”; hence yielding the timeslice relinquishes its right to access the critical section].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bliss in the method of the modified Ma to implement, wherein when the thread currently running on the core that is allowed to access the critical section attempts to access the critical section but the currently running thread is not the designated next thread to access the critical section, the currently running thread relinquishes its right to access the critical section on the core that is allowed to access the critical section, in order to allow efficient implementation of synchronization that may permit a multithreaded program to operate faster [Bliss, paragraph 4].
Allowable Subject Matter
Claims 3-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest the algorithm includes following operations: pre-operation: setting up data structures, synchronized lock states, and number of waiting threads associated with the cores and using atomic operations to update the data structure, the number of waiting threads, and the synchronized lock state on each of the cores, wherein the synchronized lock state on each of the cores represents either a locked state allowed to access the critical section or an unlocked state waiting to access the critical section, the number of waiting threads on each of the cores represents number of threads waiting to access the critical section, and each of the data structures represents an order of all threads of the number of waiting threads allowed to enter the critical section; access operation: when receiving a thread’s request to access the critical section, atomic operations are used to increment the number of waiting threads on the core where the thread is located and to update the synchronized lock state to either the locked state or the unlocked state, and at the same time, only one of the synchronized lock states on the cores is the locked state, and when anyone of the cores in the locked state uses the data structure and the number of waiting threads to designate one of all the threads as the next thread to access the critical section; and leave operation: when the thread leaves the critical section, atomic operations are used to decrement the number of waiting threads on the core where the thread is located and to update the data structure and the synchronized lock state on the core where the thread is located, and according to the updated of the data structure, the synchronization lock status and the number of waiting threads to determine to maintain the locked state of the core where the thread is located or set another of the cores to be allowed to access the critical section; after completing the pre-operation, the access operation is performed each time the thread requests access to the critical section, and the leave operation is performed each time the thread leaves the critical section, in combination with other recited limitations in claim 3.
Claims 4-21 are objected to by virtue of their dependency.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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/Farley Abad/ Primary Examiner, Art Unit 2181