DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 103, filed May 6, 2026, with respect to the rejections of claims 1 – 4, 6 – 12, and 14 – 20 under 35 U.S.C. § 103 have been fully considered and are persuasive. The claims have been amended to include limitations not suggested by the relied upon prior art. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of art found in a search of the prior art prompted by amendments.
Claim Rejections - 35 USC § 103
Claims 1 – 4, 6 – 12, and 14 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Toupal in view of Ladkani (Cited in previous action) and Hori (US Patent Application Publication 2015/0121129).
Regarding claim 1, Toupal teaches an operation method of a storage system,
wherein the storage system comprises a host device and a storage device (Fig. 1, the MCP 100 and other devices and packages 110) including a plurality of non-volatile memories (Paragraphs 0016 and 0017, both the MCPs may include an SoC including multiple components including memories; Paragraphs 0049 – 0052, memory devices may benefit from the invention disclosed in Toupal), wherein the host device and the storage device are connected (Fig. 2, and paragraphs 0021 – 0023, the components of the interconnect bus, specifically the IBs, SiPhs, and the interconnects 210, 230 and 260) through a peripheral component interconnect express (PCIe) channel (The components described in Paragraphs 0021 – 0023 are the physical layer of the link. According to paragraph 0030, the status of the link may be exposed to a PCIe interface, that is, the physical link may be used as a PCIe channel), or a non-volatile memory express (NVMe) channel, and wherein the method comprises:
based on a response time of the storage device being greater than a threshold time (Paragraphs 0034 – 0038, detecting that there is a link error based on a timeout), terminating a previous mode of the storage device and setting the storage system to a recovery mode (Paragraph 0034, the system enters a link failure error detection workflow);
determining, in the recovery mode, whether the PCIe channel or the NVMe channel is in a link down state based on a connection status of the channel (Paragraph 0039, each error is subjected to analysis to determine if the error is a network error, such as a link error, based on the error cause types logged into the status register),
based on a state of the PCIe channel or NVMe channel being the link down state, resetting, by the storage system, the PCIe channel or the NVMe channel between the host device and the storage device (Paragraph 0045, in the case of a link error, certain routines may be used to initiate a reset in the link endpoints).
Toupal does not explicitly teach:
transmitting, by the host device, a recovery signal to the storage device (Toupal is concerned with the link itself rather than the relationship between devices. While Toupal teaches recovery signals in the form of an interrupt in paragraph 0040 and a failure signal in paragraph 0042, they are not recited as being transmitted from a particular side of the link to another);
performing, by the storage device, storage recovery based on receiving the recovery signal (As with the previous limitation, Toupal does not teach the recovery signal as recited in its entirety).
Ladkani teaches an operation method of a storage system wherein the method comprises:
transmitting, by a host device (Fig. 3, the management entity 10), a recovery signal to a storage device (Fig. 3, the BMC is the storage device. Paragraph 0031 indicates that the BMC may have errors with its firmware, including its memory. Furthermore one knowledgeable in the art would; Paragraph 0033, the BMC that cannot be reached via the primary path receives a recovery signal from the management entity) and
performing, by the storage device, storage recovery based on receiving the recovery signal (Paragraph 0034, restoring the BMC firmware to a last known good state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to, in response to detecting the PCIe link failing with the method taught in Toupal, send a recovery command to the storage device by the host device and prompt the storage device to recover. It would be obvious because it provides the advantage of allowing for recovery regardless of the storage device’s status (Ladkani paragraphs 0025, 0033).
It would have further been obvious that the method of Toupal would be applicable to a system with a hierarchy similar to that taught by Ladkani. It would be obvious because such systems are known in the art and commonly used in the industry (Ladkani paragraph 0001). It would be clear to one of ordinary skill in the art that the method of Toupal, which describes the arrangement of devices generally and focuses on the link, would be applicable to a wide range of systems, including commonly used arrangements such as the one described by Ladkani.
Toupal and Ladkani do not teach that the transmitting is performed regardless of whether the PCIe channel or the NVMe channel is in the link down state (Paragraph 0042 of Toupal describes the case where the error is not a link down error, where instead a failure signal is sent to a different controller to indicate a logical switch off mode, instead of the recovery signal).
Hori teaches an operation of a storage system (Paragraph 0003), wherein the method comprises transmitting, by the host device, a recovery signal to the storage device (Paragraph 0053, a first control unit detects an abnormality of a second control unit. It transmits a retraction signal to the abnormal unit), wherein the transmitting is performed regardless of whether the PCIe channel (Paragraph 0005) or the NVMe channel is in the link down state (Paragraphs 0121, 0131, 0133 and 0138, there can be cases where the link has an abnormality but is not down. As seen in Figs. 9 and 13, transmitting the retraction signal is based on the presence of an abnormality, not whether the abnormality is a link abnormality.).
It would have been obvious to one of ordinary skill in the art that the recovery signal of Toupal in view of Ladkani should be transmitted regardless of whether the channel is in the link down state, similarly to the recovery signal taught by Hori. It would be obvious because it beneficially allows useful information to be communicated between devices via the link when it is not down (Hori paragraph 0131). Furthermore, even if an abnormality would not cause a complete link down, it would still be beneficial to correct the abnormality, as an abnormality left uncorrected can affect the performance of the devices. It is noted that Hori is clearly in the same field of endeavor as Toupal, as it relates to repairing a PCIe abnormality that is detected via timeout (Hori paragraphs 0075 – 0079).
Regarding claim 2, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein the response time of the storage device is a heartbeat update time of the storage device (Toupal paragraphs 0035 – 0037, the timeouts for the status of the device).
Regarding claim 3, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein the response time of the storage device is a response time of the storage device to a command signal from the host device (Toupal paragraph 0038, failing to receive an acknowledgement in response to packets).
Regarding claim 4, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein the host device comprises a host memory (Toupal paragraphs 0016, 0030, and 0049, the devices in Toupal each contain memories),
wherein the storage device comprises a storage controller including a buffer memory (Toupal paragraphs 0016, 0030, and 0049, the devices in Toupal each contain memories; Ladkani teaches that the storage devices comprise controllers, and the controllers contain memory as in paragraph 0031), and
a channel for data storage and transmission between the host memory and the buffer memory, wherein the channel for data storage and transmission between the host memory and the buffer memory comprises the PCIe channel (The PCIe channels of Toupal itself. Fig. 2 of Toupal shows the channels contain status registers for storing data; Toupal paragraph 0030, the endpoints have memories).
Toupal in view of Ladkani and Hori does not explicitly teach that the recovery signal is transmitted through this channel for data storage and transmission between the host memory and the buffer memory (The signal of Ladkani that is mapped to the recovery signal is only sent when the primary channel is completely unavailable, and is sent through a side channel rather than the primary channel which would comprise the PCIe channel. Hori likewise transmits its signal via a side channel directly connecting the CPUs rather than via the PCIe channel).
However, Toupal teaches that the channel for data storage and transmission between the host memory and the buffer memory comprises more than one PCIe channel (Toupal paragraph 0031, there are multiple virtual channels; Toupal Fig. 3, there are multiple physical links; Only an all VCs timeout error described in Toupal paragraph 0038 will bring down every PCIe link.). Therefore, it is possible for a single PCIe channel to be in a link down state while still allowing for communication over the channel for data storage and transmission comprising that PCIe channel. Ladkani teaches that recovery signals may be sent via the primary communication path (Ladkani paragraph 0029, corrective action commands can be sent via the primary path), and that the use of the sideband path is conditioned on the primary path being unavailable (Ladkani paragraph 0053). Similarly Hori teaches that information may be transmitted via the primary communication path as long as it is not down (Hori paragraph 0113).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that, if only a single PCIe channel of the plurality taught by Toupal were to enter a link down state, the primary communication path would still be available, and the recovery signal could be sent via a different PCIe channel of the plurality in a manner similar to that taught by Ladkani paragraph 0029. It would be obvious because Ladkani paragraph 0014 teaches communicating with a faulty storage device to repair it remotely as a known technique in the art. Although Toupal, Ladkani and Hori do not explicitly recite details of the existing methods as claimed, as they are focused on improvements to those methods, one of ordinary skill in the art would be able to reason them given the related disclosures.
Regarding claim 6, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein setting the storage system to the recovery mode comprises:
determining whether a heartbeat update time of the storage device is greater than a first threshold time (Toupal paragraphs 0035 – 0037, the timeouts for the status of the device);
determining whether a response time of the storage device with respect to a command signal of the host device is greater than a second threshold time, wherein the first threshold time is different from the second threshold time (Toupal paragraph 0038, failing to receive an acknowledgement in response to packets); and
setting the storage system to the recovery mode based on the heartbeat update time being greater than the first threshold time or the response time being greater than the second threshold time (Toupal paragraph 0034, different error conditions are detected by these separate timers).
Regarding claim 7, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein the recovery signal is configured to cause the storage device to perform internal fault recovery (Ladkani paragraph 0024, the recovery is local to the faulty device).
Regarding claim 8, Toupal in view of Ladkani and Hori teaches the method of claim 1, wherein the recovery signal is transmitted from the host device to the storage device through a side band channel between the storage device and the host device, wherein the side band channel is distinct from the PCIe channel (Ladkani Abstract; Hori paragraph 0053, transmission of the retraction signal is performed through an I2C line).
Claim 9 recites similar language to claim 1, and is similarly rejected.
Claim 10 recites similar language to claim 2, and is similarly rejected.
Claim 11 recites similar language to claim 3, and is similarly rejected.
Claim 12 recites similar language to claim 4, and is similarly rejected.
Claim 14 recites similar language to claim 6, and is similarly rejected.
Claim 15 recites similar language to claim 7, and is similarly rejected.
Claim 16 recites similar language to claim 8, and is similarly rejected.
Claim 17 recites similar language to claim 1, and is similarly rejected.
Claim 18 recites similar language to claim 2, and is similarly rejected.
Claim 19 recites similar language to claim 3, and is similarly rejected.
Claim 20 recites similar language to claim 4, and is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishiyama et al. (US Patent Application Publication 2015/0370683) and Chaiken et al. (US Patent Application Publication 2021/0255939) teach methods for determining the cause of a timeout for a PCIe device, including whether or not the timeout was caused by a link down. They are not relied upon as a secondary reference as they do not explicitly teach recovery steps.
Guo et al. (US Patent Application Publication 2020/0050505) teaches a method for recovering from errors in hosts connected via PCIe, for multiple different types of errors including link error. It is not relied upon due to differences in the high-level arrangement of hosts.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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