Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 10.
b. Claims 1-15 are pending on the application.
Drawings
2. The drawings were received on 07/30/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 07/30/2024. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-3 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ishikawa (Pub. No.: US 2007/0176658 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1. Ishikawa in Figures 1-9 are directly discloses a semiconductor device (a memory device 100, Figures. 1, 4 and 6) comprising:
a first data holding circuit (input amplifier 101, Figs 1, 4 and 6) for latching an input data signal in synchronization with a first data strobe signal (a data strobe signal DQS, Figs. 1, 4 and 6)(the data strobe signal DQS generate the input to the input amplifier 101, Figs. 1 and 6);
a second data holding circuit (input amplifier 102, Figs. 1 and 6) for latching the input data signal in synchronization with a second data strobe signal (a data signal DQS, Figs. 1 and 6)(the data signal DQ generate the input to the input amplifier 102, Figs. 1 and 6);
a variable delay circuit (a variable delay circuit 103, Fig. 1 and 103, 103b, Fig. 6) for generating the first (the data strobe signal DQS) and second data strobe signals (the data signal DQ) by delaying an input data strobe signal by a first delay amount (the variable delay circuit 103, Fig. 6) and a second delay amount (the variable delay circuit 103b, Fig. 6)(the variable delay circuit 103 connected to the latch circuit 104-106 and output A, B, C to the judging circuit 107, while the variable delay circuit 103b connected to the latch circuit 104b-106b and output A, B, C to the judging circuit 107b, respectively, Fig. 6) respectively; and
a timing adjustment circuit (a Judging circuit 107, Fig. 1 and 107, 107b, Fig. 6) for setting the first (the variable delay circuit 103, Fig. 6) and second delay amounts in the variable delay circuit (the variable delay circuit 103b, Fig. 6), wherein the timing adjustment circuit (the Judging circuit 107, 107b, Fig. 6) adjusts the first delay amount based on a determination of a match/mismatch between a first data signal (the data strobe signal DQS) from the first data holding circuit (the input amplifier 101, Fig. 6) and a second data signal (the data signal DQ) from the second data holding circuit (the input amplifier 102, Fig. 6) while changing the second delay amount (the judging circuit 107, 107b receives the outputs of the latch 104-106 each time a data signal is input thereto and compares the outputs (signal A, B, C) of the flip-flops again each other, then, the judging circuit 107, 107b delivers a delay control signal to the delay adjustment circuit 103, 103b; respectively, see at least in Figures 1, 4 and 6, column 2, paragraph 0029 to column 4, paragraph 0046 and the related disclosures).
Regarding dependent claim 2. Ishikawa in Figures 1-9 are directly disclosed a semiconductor device (a memory device 100, Figures. 1, 4 and 6), wherein the input data signal (the data strobe signal DQS) and the input data strobe signal (the data signal DQ) are signals output from a memory chip (memory chip 100)(the data strobe signal DQS and the data signal DQ generate the input in the memory device 100, Fig. 1).
Regarding dependent claim 3. Ishikawa in Figures 1-9 are directly disclosed a semiconductor device (a memory device 100, Figures. 1, 4 and 6), wherein the memory chip (memory device 100, Fig. 1) is a DDR-SDRAM chip (the memory device 100 is the type of DDR-SDRAM chip, column 1, paragraph 0004).
Allowable Subject Matter
6. Claims 4-9, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 4-5, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor device, wherein the timing adjustment circuit operates during a normal operation period in which the memory chip performs a normal read operation, and wherein the first data signal is transmitted to a subsequent stage as a read data signal from the memory chip, wherein an initial sequence period including a training period for the memory chip is provided before the normal operation period, wherein the initial value of the first delay amount is determined during the initial sequence period, and wherein the timing adjustment circuit starts operating from the initial value of the first delay amount during the normal operation period.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor device, wherein the timing adjustment circuit detects the eye width of the input data signal by determining the match/mismatch while changing the second delay amount and adjusts the first delay amount so that the edge of the first data strobe signal is positioned in the center of the eye width.
With respected to dependent claim 7, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor device, further comprising a Decision Feedback Equalizer (DFE) inserted in the transmission path of the input data signal for performing waveform equivalence of the input data signal, semiconductor device.
With respected to dependent claim 8, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor device further comprising: a third data holding circuit for latching the input data signal in synchronization with a third data strobe signal, wherein the variable delay circuit generates the second data strobe signal by delaying the input data strobe signal by a second delay amount smaller than the first delay amount, wherein the variable delay circuit generates the third data strobe signal by delaying the input data strobe signal by a third delay amount larger than the first delay amount, and wherein the timing adjustment circuit adjusts the first delay amount based on the determination of the match/mismatch between the first data signal and the second data signal and the match/mismatch between the first data signal and the third data signal from the third data holding circuit, while varying the second and third delay amounts.
With respected to dependent claim 9, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor device is a semiconductor chip that serves the function of a data buffer in a memory module.
7. Claims 10-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 10: there is no teaching, suggestion, or motivation for combination in the prior art to “a module wiring board having control external terminals and data external terminals; multiple DDR-SDRAM chips mounted on the module wiring board; a registered clock driver mounted on the module wiring board for re-driving a memory control signal input through the control external terminals and outputting to the multiple DDR-SDRAM chips; and a data buffer mounted on the module wiring board for re-driving data signals and data strobe signals input through the data external terminals and outputting to the multiple DDR-SDRAM chips, and for re-driving input data signals and input data strobe signals from the multiple DDR-SDRAM chips and outputting to the data external terminals, wherein the data buffer has a first data holding circuit for latching the input data signal in synchronization with a first data strobe signal, a second data holding circuit for latching the input data signal in synchronization with a second data strobe signal, a variable delay circuit for generating the first and second data strobe signals by delaying the input data strobe signal by the first and second delay amounts, respectively, and a timing adjustment circuit for setting the first and second delay amounts in the variable delay circuit, and wherein the timing adjustment circuit adjusts the first delay amount based on the determination of whether the first data signal from the first data holding circuit matches or does not match the second data signal from the second data holding circuit, while varying the second delay amount” in a memory module as claimed in the independent claim 10. Claims 11-15 are also allowed because of their dependency on claim 10.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Okinoi (US. 11,626,867 B2) discloses variable delay circuit and semiconductor integrated circuit.
Nishio (US. 9,368,174 B2) discloses a control device that comprises a first data strobe input terminal to be connected in common to data strobe terminal that are includes respectively in first memory device.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov