DETAILED ACTION
Claims 1-20 were restricted. Claims 1, 8-20 were elected. Claims 2-7 are withdrawn.
Claims 1,8-12,14,16-17,19-20 are amended. Claims 1,8-20 are pending.
Priority: 7/30/2024
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claim 1 is rejected for reciting limitations that are unclear, vague, ambiguous and indefinite.
Claim 1 recites ‘An apparatus, comprising: register, a DRAM array….’. The phrase ‘register’ lacks antecedent basis because it is introduced without an article (e.g., ‘a’ or ‘an’). It is unclear whether the limitation intends to claim a single register, a specific register, or a plurality of registers.
The identity of the claimed ‘register’ is further unclear with reference to the spec. In Para-0025, the spec states that the control circuitry includes a ‘number of registers 122 (e.g., mode registers)’ designed to ‘store default settings for the memory array’.
Claim 1, however, requires the controller to maintain a ‘tag match table in the register indicating correspondence between a respective tag identifier….and a respective list of a plurality of DRAM addresses’.
It is completely unclear whether the ‘register’ of Claim 1 is one of the ‘number of registers 122 (e.g., mode registers)’ or an entirely separate hardware component. If it is intended to be one of the mode registers 122, the spec fails to clarify how a standard mode register storing default settings can be configured to maintain a tag match table (suggests lack of possession). If it is intended to be a separate register, the spec provides no corresponding disclosure or specific number for such a structure (suggests lack of possession).
Since the spec assigns a specific purpose to the only registers it explicitly discloses (storing default settings), claiming a generic ‘register’ to perform an entirely different, complex data-mapping function creates a contradiction. Consequently, the identity of the claimed ‘register’ renders the claim indefinite. Hence claim 1 is rejected. Claims 8, 19 have the same issue and are also rejected.
2.Amended Claims 1, 8, 19 are rejected as being unclear, inconsistent and indefinite.
Claim 19 introduces a special ‘tag register’ to store a tag identifier name, but requires the controller to maintain a tag match table in ‘the register’ (lacking a direct antecedent basis).
Claim 1 drops the word ‘tag’, introducing a generic ‘register’ (omitting an introductory article) to store the exact same tag match table.
Since the claims alternate between a ‘tag register’ and a generic ‘register’, it cannot be determined with reasonable certainty whether the two independent claims are referencing the same physical hardware structure or two entirely separate structural components. This confusion is compounded by the fact that the term ‘tag register’ appears nowhere in the written description.
This structural uncertainty becomes more confusing by the spec's self-contradictory disclosures regarding where this ‘tag match table’ actually resides. Specifically, the spec describes the tag match table as being located in five different locations - within the control circuitry, within a tag controller inside the control circuitry, inside a tag match engine of a DRAM memory device, inside a register and outside of the register.
‘Inside a register’ and ‘outside of the register’ are mutually exclusive physical locations. By reciting a ‘tag register’ in Claim 19, a generic ‘register’ in Claim 1, and the spec that simultaneously places the tag match table inside and outside of these structures, it is unclear what physical hardware actually constitutes the claimed ‘controller’ and ‘register’. Since the claims utilize inconsistent nomenclature to define the underlying hardware structures, the scope of the claims and the disclosure are uncertain.
Hence claim 1 and 19 are rejected. Amended Claim 8 is similar to claim 1 and is also rejected.
3.Amended Claims 1,8,19 is rejected for reciting limitations that are unclear, ambiguous, inconsistent and indefinite.
Amended Claim 1 recites that the controller is configured to ‘receive a memory access request, which includes the respective tag identifier’. The phrase ‘the respective tag identifier’ in this limitation lacks proper antecedent basis.
While the previous limitation refers to a table indicating correspondence between ‘a respective tag identifier of a plurality of tag identifiers’ and address lists, the next recitation of receiving a request with ‘the respective tag identifier’ is ambiguous.
By stating that an incoming memory access request includes ‘the’ respective tag identifier, the claim implies that a single memory access request simultaneously contains or refers to the entire plurality of tag identifiers defined within the table. This contradicts the spec.
Para-0009 of the spec states that the controller receives a request including ‘a particular tag identifier’. Since the claim substitutes this clear designation with the broad, linked term ‘the respective tag identifier’, the exact scope or sequential logic of the data entering the controller during a memory access event cannot be determined. Therefore, the limitation is indefinite.
The last limitation recites, ‘thereby accessing a relatively larger amount of data than would be accessed using a single DRAM address’.
The phrase ‘a relatively larger amount of data’ is a term of degree that lacks a standard baseline measurement within the claim or the spec. The claim fails to define what standard baseline is being compared against ‘relatively larger’ (e.g., a standard burst length, a single cache line, or a specific page size). Under MPEP 2173.05(b), terms of degree must be bounded by a standard. Since this ‘thereby….’ limitation relies on a comparative and unbounded result, the scope of the claim is unclear. Therefore claim 1 is rejected as being indefinite. Claims 8, 19 have the same issue and are also rejected.
4.Amended Claims 9-12, 14, 16-17, 20 are rejected for reciting limitations that are unclear, ambiguous and indefinite.
Claims 9–12, 14, 16-17 depend on independent Claim 8. Because independent Claim 8 is indefinite for the reasons shown above regarding the phrase ‘the respective tag identifier’, the dependent claims are similarly indefinite because they incorporate the ambiguous limitations of the independent claim by reference.
Furthermore, each of the dependent claims recites ‘the respective tag identifier’ to add further structural or operational limitations. Since the Claim 8 phrase lacks proper antecedent basis and fails to clearly distinguish between a single incoming tag identifier from a memory request and the plurality of tag identifiers stored in the table, the scope of the limitations in the dependent claims is unclear. Claim 20, a dependent claim of independent claim 19 has the same issue. Hence limitations 9-12, 14, 16-17, 20 are rejected as being indefinite.
5.Amended Claims 1,8,19 is rejected for reciting limitations that are unclear, ambiguous and indefinite.
Amended Claim 1 recites maintaining a tag match table indicating a correspondence between ‘a respective tag identifier of a plurality of tag identifiers’ and ‘a respective list of a plurality of DRAM addresses for each of the plurality of tag identifiers’.
The spec does not recite this limitation. In addition, the limitation creates an ambiguity regarding the scope of the phrase ‘the plurality of tag identifiers’ at the end of the clause. The ambiguity is whether the ‘plurality of tag identifiers’ refers to the same set or two different sets.
It is unclear whether ‘for each of the plurality of tag identifiers’ refers back to the entire ‘plurality of tag identifiers’ introduced just a few words prior, or if it is attempting to define the scope of the ‘respective tag identifier’ within that plurality.
As recited, the limitation presents a logical contradiction. If a correspondence is established for a respective tag identifier (singular) chosen out of a plurality, it is logically inconsistent to immediately require that this same single correspondence is also maintained ‘for each of’ the entire plurality.
On the other hand, the spec provides a clear, concise phrase, ‘maintain a tag match table indicating correspondence between a respective tag identifier and a respective plurality of DRAM addresses for each of a plurality of tag identifiers’.
Therefore by introducing the extra words ‘of a plurality of tag identifiers’ and changing the subsequent phrase to ‘a respective list of….’, the claim has introduced unnecessary nesting that obscures whether the ‘tag match table’ maps one-to-many across the entire set, or if the claim is trying to limit the table's function to a specific subset of tag identifiers. Accordingly, the scope of the claim is unclear. Hence claim 1 is indefinite and rejected. Claims 8,19 have the same issue and are also rejected.
6.Amended Claim 9 is rejected for reciting a limitation that are unclear, ambiguous and indefinite.
Claim 9 recites, ‘classifying, using the respective tag identifier, data stored in a first DRAM address and data stored in a second DRAM address as public or private’.
The claim continues to use the incorrect phrase ‘the respective tag identifier’. As shown previously, this phrase is ambiguous because it fails to distinguish between a single incoming tag from a memory request and the entire matrix of tags stored in the table.
Furthermore, the claim introduces a new functional operation (‘classifying…. as public or private’) but fails to state what is performing the classification. Is the controller configured to classify the data? Is the register doing it? By leaving the functional verb ‘classifying’ unanchored to a specific structural component, the claim scope is indefinite.
Though Para-0043 of the spec recites ‘a tag identifier can classify data….’, a tag identifier is not a structural component and cannot classify data. Is the classification host controlled? Since neither the spec nor the claim recite what component performs the classification and how it is done, claim 9 is indefinite and rejected.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 8-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Amended Claims 1, 8, 19 are rejected for reciting a limitation that lacks written description support in the spec.
Claim 1 recites that the controller is configured to ‘maintain a tag match table in the register’.
However the spec and drawings fail to demonstrate that the inventor was in possession of a paragraph where the tag match table is structurally or logically configured inside the register at the time of filing.
First, Fig. 1 shows a DRAM with control circuitry, a tag controller, and a register, but completely omits the ‘tag match table’. The drawings provide no structural representation or memory mapping showing how a table structure is maintained within the illustrated register component.
Second, the spec does not provide any written description of this configuration. While the spec lists ‘inside a register’ as one option, it immediately weakens this recitation by stating ‘in other embodiments, the tag match table can be stored outside of the register’, or within a control circuitry, a tag controller, or a separate tag match engine.
Since the spec provides an open-ended list of mutually exclusive hardware hosts (inside vs. outside a register) and the drawings fail to show the tag match table within any of them, the mere mention of the phrase ‘inside a register’ is a functional wish list rather than a description of a completed, possessed structure.
The spec fails to show in detail how the controller acts upon the register to maintain the specific claimed tabular data structure or tag match table and retrieve information from the table. Therefore, the inventor has not demonstrated possession of the limitation ‘maintain a tag match table in the register indicating correspondence between a respective tag identifier of a plurality of tag identifiers and a respective list of a plurality of DRAM addresses for each of the ….tag identifiers’. Hence claim 1 recites a scope unsupported by the spec and is rejected. is rejected. Claims 8 and 19 have the same issue and are also rejected.
2.Claims 1, 8, 19 are rejected for reciting a limitation that is unsupported by the spec.
Amended Claim 1 recites that the controller which maintains a tag match table in the register is configured to ‘retrieve the respective plurality of DRAM addresses corresponding to the respective tag identifier from the tag match table’ and ‘access memory locations corresponding to the respective plurality of DRAM addresses’. This broad language includes any and all methods, hardware configurations, or algorithms capable of searching a register-resident tag match table and mapping a tag identifier to a list of separate physical memory addresses.
To satisfy the written description requirement, the spec must describe the invention in sufficient detail to show that the inventor possessed the specific hardware or algorithm to execute the claimed function.
But the spec fails to provide this detail. In Para-0029, the spec merely recites that the tag controller ‘can search the tag match table to determine whether the tag identifier corresponding to the request for data has a value’, and if it does, the data is retrieved. This disclosure outlines a broad, generic research concept (determining if a tag has a value) rather than a concrete technical implementation.
The spec provides no details regarding how this search is actually performed within the physical and functional constraints of the claimed invention. For example, the spec fails to disclose whether the search is a sequential linear search, a binary search, or a parallelized content-addressable memory/CAM lookup. The spec fails to describe how a standard, generic ‘register’ is structurally or logically partitioned to support a dynamic search-and-retrieval operation linking a variable ‘string of numbers and/or letters’ to a ‘plurality of DRAM addresses’.
The spec relies on 1-line circular, non-structural outcomes, stating that if a tag ‘has a value’, data is retrieved, and if it ‘does not have a value’, it is not retrieved. See spec, Para-0029. The spec fails to define what constitutes a ‘value’ (e.g., a valid bit, a specific pointer, or an address mapping).
Though the claim recites a ‘tag match table’ to represent a multi-bank DRAM architecture, how the tag match table is populated/built is undisclosed.
DRAM row and column addresses require significant bit-widths. A single line (‘maintaining….a tag match table in a register’) claiming that an entire matrix (multiple tags, each mapped to a list of a plurality of DRAM addresses) is stored directly inside an on-chip register creates a physical sizing conflict. How the controller ‘maintains’ this entire matrix is undisclosed.
A disclosure that merely recites the desired functional capability of a device (searching a tag match table in a register) does not satisfy the requirement to describe the actual structure or step-by-step logic used to achieve that capability. Because the spec fails to disclose any technical details, algorithm, flowchart etc. showing how the claimed apparatus/hardware executes the search of the register-resident tag match table, the disclosure does not demonstrate that the inventor possessed the claimed invention at the time of filing. Hence claim 1 recites a scope unsupported by the spec and is rejected. Claims 8, 19 have the same issue and are also rejected.
Restriction
In the Restriction Requirement mailed on Oct 16, 2025, applicant elected claims 1, 8-20 and Fig. 4 for prosecution.
Independent Claims 1, 8, 19, submitted as part of the original disclosure, stated, ‘….correspondence between a respective tag identifier and a respective plurality of dynamic random access memory (DRAM) addresses….’. The same configuration is recited in Para-0037 and Fig. 4 of the spec.
The current amendment to Claims 1, 8, 19 modifies the phrase ‘a respective plurality of DRAM addresses’ to ‘a respective list of a plurality of DRAM addresses’.
The introduction of a ‘list’ of DRAM addresses corresponds to the disclosure of Fig. 2, Para-0028 (‘The table which is in a DRAM engine can include a DRAM address list 228 and a tag value list 230’) and Fig. 3, Para-0030 (‘a linked list of DRAM addresses’), which are directed to a non-elected invention. Under MPEP 821.01, an amendment to an elected claim that introduces limitations drawn solely to a non-elected invention is improper.
Applicant is advised that the inclusion of this limitation is viewed as an attempt to constructively traverse the restriction or shift the scope to a non-elected embodiment. Applicant must either: amend the claim to remove the non-elected ‘list’ limitation, returning the claim scope to the elected embodiment, or cancel the claim and pursue this subject matter in a divisional application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 16-19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hansson et al (20190384718) in view of Le et al (20170212840) and Crawford (20180074754).
As per Claim 8, Hansson discloses a method (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2]; [0051 - Fig. 2 shows a DRAM-based storage circuit 30]; [0057 - Fig. 6 shows DRAM 64 of Fig. 5. As in Fig. 2, the DRAM 64 comprises an array 32 of storage locations 34]; [0014 - A method for accessing information from storage circuitry comprising an array of storage locations arranged in rows and columns]), comprising:
maintaining, by a controller (Hansson, [0009 - a cache controller to control accesses to cached data stored in the storage circuitry]), a tag match table (Hannson, [Fig. 3: SRAM tag storage 50]; [0051 - The row decoder 40 activates the corresponding row 46, to bring the information stored in each of the storage locations/addresses 34 of the corresponding row into row buffer 36]) in a register (Hansson, [0051 - storage circuit 30 comprises an array 32 of storage locations 34 arranged in rows and columns, a row buffer 36 with tags and data, a column multiplexer 38 and a row decoder 40; Since a register inside a DRAM controller is fast because it is built from high-speed flip-flops or latches, the citation is a valid interpretation]; [See 112(a), 112(b)]) indicating correspondence between a respective tag identifier of a plurality of tag identifiers and a respective list of a plurality of DRAM addresses for each of the plurality of tag identifiers (Hansson, [0003-0006 - storage circuitry comprising: an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of entries of the row buffer, and to identify which of said subset of entries/list is a matching entry storing information matching the tag value, said subset comprising two or more entries of the row buffer, thereby implying storage circuitry which includes comparison circuitry maintains the table which stores tags and their corresponding list of DRAM addresses]);
receiving, by the controller, a memory access request which includes the respective tag identifier (Hansson, [0047 – in response to a cache access request specifying a target address, implying that address is in hexadecimal format; Since the spec, Para-0029 recites that tag identifier value can be a string of numbers and/or letters it implies that identifier is in hex format]; [0059 - when a tag-matching command is received, the control circuitry 74 controls the comparators 70 to compare the received tag value 72 with the tags stored in a subset of entries 68 of the row buffer]; [0068 - Fig. 11 shows processing of a tag-matching command. At step 110, DRAM 64 receives a tag-matching command specifying a row address 42 and a tag value 72 and read/write, from the cache controller 62; Since the claim does not define the format of ‘the respective tag identifier’, the citation is a valid interpretation]);
retrieving, by the controller the plurality of DRAM addresses corresponding to the respective tag identifier from the tag match table (Hansson, [0002 - Once a row is activated, a number of reads to different locations/addresses in the row can be performed by reading the contents of the row buffer]; [0015 - transferring information from storage locations/addresses in an active row of the array to a row buffer comprising a plurality of entries, each entry storing information from a storage location at a corresponding column of the active row]);
access by the controller, memory locations corresponding to the respective plurality of DRAM addresses (Hansson, [Fig. 11: tag gather command]; [0016 - in response to a tag-matching command specifying a tag value, comparing the tag value with information stored in each of a subset of entries of the row buffer, and identifying which of said subset of entries is a matching entry storing information matching the tag value, said subset comprising two or more entries of the row buffer; Here ‘subset of entries’ is a list]), thereby accessing a relatively larger amount of data than would be accessed using a single DRAM address (Hansson, [0032 - The comparison circuitry performs a plurality of comparisons in parallel thereby implying fast lookups]; [0031 - The storage circuitry is used more effectively as a set-associative cache, since a set of locations can have their tags looked up in response to a single tag-matching command, rather than requiring a number of separate read operations, thereby implying accessing a relatively larger amount of data]).
Le discloses maintaining a tag match table in a register where the tag match table indicates a correspondence between each tag identifier and its associated list of addresses as follows,
maintaining, by a controller (Le, [Fig. 6: memory controller 610]; [0055 - The memory system 612 can include one or more memory units 624(0)-624(N); Here 624(0)-624(N) are DDR, an advanced DRAM]; [0058 – In Fig. 1, the processor may be a controller]), a tag match table in a register (Le, [0021 – In Fig. 1, a DRAM cache 104 and an associated tag directory 106 for the DRAM cache 104, both of which are part of a high-bandwidth memory 108; Here components 104+106 represent the tag match table]) indicating correspondence between a respective tag identifier of a plurality of tag identifiers and a respective list of a plurality of DRAM addresses for each of the plurality of tag identifiers (Le, [0007 - DRAM cache management utilize a cache for storing tags corresponding to cached memory addresses]; [0024 – In Fig. 1, DRAM cache 104 provides DRAM cache lines 118(0)-118(B),118′(0)-118′(B) organized into ways 120(0)-120(C) to store the previously read memory addresses and data. For each of the DRAM cache lines 118(0)-118(B),118′(0)-118’(B) within DRAM cache 104, tag directory 106 for the DRAM cache 104 stores a tag 122(0)-122(I) generated from a memory address of the corresponding DRAM cache line 118(0)-118(B),118′(0)-118′(B)]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag match table of Le into the DRAM memory device of Hansson, for the benefit of improving memory bandwidth, wherein the DRAM cache within the high-bandwidth memory of the processor-based system is used to cache memory addresses and data that were previously read from memory lines within the system memory DRAM (Le, Para-0023).
Crawford discloses maintaining the table in a register as follows,
maintaining, by a controller (Crawford, [Fig. 1A: controller 140]), a tag match table (Crawford, [Fig. 2 shows a first row of a table]) in a register (Crawford, [0040 – In Fig. 2, register 236 can include a row index (R) 235, a column index (C) 237, and subarray index (S) 239. Register 236 can include a reference/address to data in memory arrays that includes a row index 235, a column index 237, and a subarray index 239]) indicating correspondence between a respective tag identifier of a plurality of tag identifiers and a respective list of a plurality of DRAM addresses for each of the plurality of tag identifiers (Crawford, [0041 – In Fig. 2, row index 235 can be used to access data based on the row in the memory array in which the data is stored. The row index 235 in register 236 can be updated by iterating through row indexes to access data stored in horizontal bit vectors in the array of memory cells. Column index 237 can be used to access data based on the column in the memory array in which the data is stored. The column index 237 in register 236 index 237 in register 236 can be updated by iterating through columns indexes to access data stored in vertical bit vectors in the array of memory cells. Subarray index 239 can be used to access data based on the subarray in the memory array in which the data is stored. The subarray index 239 in register 236 can be updated by iterating through subarray indexes to access data stored in particular locations/addresses of subarrays in the array of memory cells]);
access by the controller, memory locations corresponding to the respective plurality of DRAM addresses (Crawford, [0016 - The resolve instruction can include fewer bits than a corresponding instruction executed on the host to access the same memory locations in the memory array. Subsequently, adjacent memory locations may be accessed by performing arithmetic operations on the bank register contents without intervention by systems or processors other than a controller on the memory device]), thereby accessing a relatively larger amount of data than would be accessed using a single DRAM address (Crawford, [0036 - The reference in register 136 can be used as an operand in logical operations performed on a memory device. The reference can be updated so that logical operations can access data that is located in a number of locations in the memory array, thereby implying that a larger amount of data is accessed by the controller]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the register of Crawford into the DRAM memory device of Hansson, for the benefit of including an array of memory cells and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated to access the data stored in the array of memory cells (Crawford, 0015).
As per Claim 16, the rejection of claim 8 is incorporated, and Hansson discloses,
identifying, by the respective tag identifier, data stored in a first DRAM address and the data stored in a second DRAM address (Hansson, [0033 - The tag value identifies part of the address of the data value in the other location of the pair]) in response to the controller associating (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2. The cache 2 has a number of cache entries 4 each comprising a tag-data pair]) the data stored in the first DRAM address with the data stored in the second DRAM address (Hansson, [T0,D0]; [T1,D1]; [0033 - When the storage circuitry is used as a cache, the storage locations may be allocated in pairs with each pair comprising one location for storing a cached data value and another storage location for storing a corresponding tag value]; [0047 - When a hit is identified in response to the tag-matching command, the storage circuitry outputs to the cache controller at least one of: a data value corresponding to a target storage location other than the storage location associated with the matching entry, and information for identifying which storage location of the storage circuitry is the target storage location, thereby showing the association between the data stored in the first and second DRAM addresses; Since the claim does not recite how the ‘association’ is made, the citation is a valid interpretation]).
As per Claim 17, the rejection of claim 16 is incorporated, and Hansson discloses,
identifying, by the respective tag identifier, data stored in a third DRAM address and data stored in a fourth DRAM address (Hansson, [0033 - The tag value identifies part of the address of the data value in the other location of the pair]) in response to the controller associating (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2. The cache 2 has a number of cache entries 4 each comprising a tag-data pair]) the data stored in the third DRAM address to the data stored in the fourth DRAM address (Hansson, [T2,D2]; [T3,D3]; [0033 - When the storage circuitry is used as a cache, the storage locations may be allocated in pairs with each pair comprising one location for storing a cached data value and another storage location for storing a corresponding tag value]; [0047 - When a hit is identified in response to the tag-matching command, the storage circuitry may output to the cache controller at least one of: a data value corresponding to a target storage location other than the storage location associated with the matching entry, and information for identifying which storage location of the storage circuitry is the target storage location]).
As per Claim 18, the rejection of claim 17 is incorporated, and Hansson discloses,
wherein the first DRAM address and the third DRAM address are stored in a first memory bank (Hansson, [Fig. 9: Bank0 – T0,T2]; [0064 - Fig. 8 shows an example with two banks of DRAM]), and the second DRAM address and the fourth DRAM address are stored in a second memory bank (Hansson, [Fig. 9: Bank1 – T1,T3]; [0065 - In a multi-bank DRAM implementation, it is useful to interleave the data values and tag values of a number of tag-data pairs among corresponding rows of separate banks as shown in Fig. 9]).
As per Claim 19, Hansson discloses a system (Hansson, [0047 - An apparatus, e.g. a data processing system, comprises of a storage circuitry and a cache controller to control accesses to cached data stored in the storage circuitry]; [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2]; [0051 - Fig. 2 shows a DRAM-based storage circuit 30]), comprising:
a host (Hansson, [0067 - In Fig. 10, step 100, the DRAM 64 receives an activate command specifying a row address 42 from the cache controller 62, thereby implying that the host wants to read or write data]);
a memory device coupled to the host (Hansson, [0056 - Fig. 5 shows a data processing apparatus 60 comprising a cache controller 62 and DRAM storage circuitry 64/DRAM memory device and as shown above DRAM 64 receives the activate command implying coupling with the host]),
wherein the memory device includes:
a register (Hansson, [0051 - storage circuit 30 comprises an array 32 of storage locations 34 arranged in rows and columns, a row buffer 36, a column multiplexer 38 and a row decoder 40]);
a dynamic random access memory (DRAM) array (Hansson, [0057 - As in Figs. 2,6, DRAM 64 comprises an array 32 of storage locations 34, row buffer 36, column multiplexer 38 and row decoder 40. The row buffer 36 includes a number of entries 68, each entry 68 corresponding to one column of storage array 32]);
a memory device controller (Hansson, [Fig. 5: cache controller 62]) coupled to the register and to the DRAM array (Hansson, [Figs. 5,6]) and configured to receive, from the host, a request for data stored in the DRAM array (Hansson, [0056 – In Fig. 5, for a read operation, cache controller 62 issues a tag-matching read command, and provides DRAM 64 with a row address identifying the required row of DRAM locations and a tag value to be compared with the tags stored in that row of DRAM locations]),
wherein the memory device controller (Hansson, [Fig. 6]) includes:
a tag register configured to store a tag identifier name (Hansson, [0061 – Fig. 6: configuration storage element 76]; [0061 – In Fig. 6, configuration data 76 identifies the entries storing the tags and control the comparators 70 to compare those entries with the tag value 72, thereby implying that the identification uses a tag identifier name/ID]; [See 112(b)]);
and a tag controller (Hansson, [Fig. 6: control circuitry 74]) configured to:
Le clarifies,
a memory device controller (Le, [Fig. 1: processor-based system 102 is a controller]) coupled to the register (Le, [Fig. 1: HBM 108]) and to the DRAM array (Le, [Fig. 1: DRAM 110]), wherein the controller is configured to receive, from the host (Le, [Fig. 6: CPU 602]), a request for data stored in the DRAM array (Le, [Fig. 1: memory read request 128]),
wherein the memory device controller includes:
a tag register configured to store a tag identifier name (Le, [Fig. 1: HBM 108]; [See 112(b)]);
and a tag controller (Le, [Fig. 1: DRAM cache management circuit 102]) configured to:
Crawford clarifies,
a host (Crawford, [Fig. 1A: host 110]);
a memory device coupled to the host (Crawford, [0021 – In Fig. 1A, system 100 includes host 110 coupled to memory device 120, which includes memory array 130]),
wherein the memory device includes:
a register (Crawford, [Figs. 1A-1B, Register 136]; [See 112(b)]);
a dynamic random access memory (DRAM) array (Crawford, [Fig. 1A: memory array 130]: [0023 – In Fig. 1A, memory array 130 is a DRAM array]);
a memory device controller (Crawford, [Fig. 1A: controller 140]) coupled to the register and to the DRAM array (Crawford, [0025 – In Fig. 1A, controller 140 is responsible for executing instructions from host 110 and sequencing access to array 130. Controller 140 includes register 136. Register 136 can include a reference to data stored in memory array 130]), wherein the controller is configured to receive, from the host, a request for data stored in the DRAM array (Crawford, [0025 – In Fig. 1A, controller 140 decodes signals provided by control bus 154 from host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including memory operations, e.g., data read, data write, and/or data erase operations, among other operations, for example) and/or logical operations]),
wherein the memory device controller includes:
a tag register configured to store a tag identifier name (Crawford, [Fig. 1B: register 136]; [See 112(b)]);
and a tag controller (Crawford, [Fig. 1B: control logic 131]) configured to:
The remaining limitations are similar to claims 1,8 and therefore the same mappings are incorporated.
As per Claim 1, Hansson discloses an apparatus (Hansson, [0047 - An apparatus, e.g. a data processing system comprises the storage circuitry and a cache controller to control accesses to cached data stored in the storage circuitry]), comprising:
register (Hannson, [0054 - SRAM-based storage structure 50]; [0051 - storage circuit 30 comprises an array 32 of storage locations 34 arranged in rows and columns, a row buffer 36, a column multiplexer 38 and a row decoder 40]; [See 112(b)]);
a dynamic random access memory (DRAM) array (Hansson, [Fig. 2: DRAM array 32]);
a controller (Hansson, [Figs. 3-4: cache controller 52]; [Fig. 5: cache controller 62]) coupled to the register and to the DRAM array (Hansson, [0056 - Fig. 5 shows a data processing apparatus 60 comprising a cache controller 62 and DRAM storage circuitry 64]),
Le clarifies,
register (Le, [Fig. 1: HBM 108]; [See 112(b)]);
a dynamic random access memory (DRAM) array (Le, [Fig. 1: DRAM 110]);
a controller (Le, [Fig. 1: processor-based system 102 is a controller]) coupled to the register and to the DRAM array (Le, [Fig. 1]),
Crawford clarifies,
register (Crawford, [Figs. 1A-1B, Register 136]; [See 112(b)]);
a dynamic random access memory (DRAM) array (Crawford, [Fig. 1A: memory array 130]: [0023 – In Fig. 1A, memory array 130 is a DRAM array]);
a controller (Crawford, [Fig. 1A: controller 140]) coupled to the register and to the DRAM array (Crawford, [0025 – In Fig. 1A, controller 140 is responsible for executing instructions from host 110 and sequencing access to array 130. Controller 140 includes register 136. Register 136 can include a reference to data stored in memory array 130]),
The remaining limitations are similar to claim 8 and therefore the same mappings are incorporated.
Claims 9-10, 13, 20 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Hansson et al (20190384718) in view of Le et al (20170212840), Crawford (20180074754) and Ayrapetyan et al (20210294755).
As per Claim 9, the rejection of claim 8 is incorporated, and Hansson, Le, Crawford disclose a tag match table.
Ayrapetyan further discloses,
classifying, using the respective tag identifier, data stored in a first DRAM address and data stored in a second DRAM address as public or private (Ayrapetyan, [0085 – In Fig. 3, with each data block 115, there is a tag field 120, which is a single bit field referred to as the tag bit, which is set to identify that the associated data block represents a capability, and is cleared to indicate that the associated data block represents normal data; Here clear bit/normal is interpreted as public]).
As mentioned in the 112(b), it is unclear what component classifies the data.
As a general hardware rule, a standard DRAM controller cannot classify the data stored inside the DRAM. It is well known that the host CPU can classify data by generating and embedding metadata tags and capability pointers directly into the references for that data. By attaching hardware-enforced tag bits and setting explicit boundary and permission fields, the host defines whether DRAM-stored information functions as public or private data.
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson, Le, Crawford for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 10, the rejection of claim 9 is incorporated, and Hansson, Le,
Crawford disclose a tag match table.
Ayrapetyan further discloses,
assigning, using the particular tag identifier, an access level to the data stored in the first DRAM address and the data stored in the second DRAM address (Ayrapetyan, [0105 – Figs. 7A to 7C show the use of headers for each allocated memory region of data]; [0109 - the permissions field 330 can be provided to store at least a portion of the permission bits of the bounded pointer]; [0110 – In Fig. 7C, the revocable bounded pointer includes a pointer field 345 for storing a pointer value, a base field 350 for identifying the base address of the memory region, a limit field 355 for identifying the limit address, a permissions field 360/access level for storing various permissions bits, a small token field 365 for storing a small token value, etc.; Since the claim does not define ‘access level’ and its representation, the citation is a valid interpretation]) in response to the particular tag identifier classifying the data stored in the first DRAM address and the data stored in the second DRAM address as private (Ayrapetyan, [0085 – In Fig. 3, in association with each data block 115, there is a tag field 120, which is a single bit field referred to as the tag bit, which is set to identify that the associated data block represents a capability/private]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson, Le, Crawford for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 13, the rejection of claim 10 is incorporated, and Hansson, Le, Crawford disclose a tag match table.
Ayrapetyan further discloses,
wherein the data stored in the first DRAM address has a first access level and the data stored in the second DRAM address has a second access level that is a different access level than the first access level (Ayrapetyan, [0105 - Figs. 7A-7C show the use of headers for each allocated memory region of data]; [0110 - FIG. 7C shows a revocable bounded pointer 340, and its various fields. The revocable bounded pointer includes a pointer field 345 for storing a pointer value, a base field 350 for identifying the base address of the memory region, a limit field 355 for identifying the limit address, a permissions field 360 for storing various permissions bits. An E bit field 375 can be provided which can be used to identify whether the content of the bounded pointer is encoded or not, thereby implying that being encoded or not determines the access level; Since the claim does not define ‘access level’, how it is represented or determined, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson, Le, Crawford for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 20, the rejection of claim 19 is incorporated and Hansson, Le, Crawford disclose a tag match table.
Ayrapetyan further discloses,
the respective tag identifier indicates whether data stored in a first DRAM address and data stored in a second DRAM address are in a first mode or a second mode (Ayrapetyan, [0080 – In Fig. 1, restriction 66 field of each bounded pointer register 60 could be used to restrict the types of instructions which may use pointer 62/tag ID, or the modes of the pipeline 4 in which the pointer can be used]);
the first mode allows for a greater level of interactivity with the data stored in the first DRAM address and the data stored in the second DRAM address than the second mode (Ayrapetyan, [0080 - The range information 64 and restriction information 66 define capabilities within which the pointer 62 is allowed to be used. When an attempt is made to use a pointer 62 outside the defined capabilities, an error can be triggered. The range information 64 can be useful for ensuring that pointers remain within certain known bounds and do not stray to other areas of the memory address space which might contain sensitive or secure information, thereby establishing ‘level of interactivity’. Since the claim does not recite how ‘level of interactivity’ is determined, the citation is a valid interpretation]).
Neither the claim nor the spec disclose the format of the ‘respective tag identifier’.
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson, Le, Crawford for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
Claims 11-12, 14-15 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Hansson et al (20190384718) in view of Le et al (20170212840), Crawford (11288188), Ayrapetyan et al (20210294755), and Barnes (20200225872).
As per Claim 11, the rejection of claim 10 is incorporated, and Hansson, Le, Crawford, Ayrapetyan disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device retrieves the data stored in the first DRAM address and the second DRAM address (Barnes, [0032 - The memory access circuitry generates an indication of whether a match is detected between the guard tag and the address tag. This indication is used to control whether the memory access is allowed to succeed]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator program 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the respective tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device (Barnes, [0032 - Memory access circuitry compares an address tag that is associated with the target address with a guard tag that is stored in the memory system is associated with a block of one or more memory locations/first and second, which includes the addressed location identified by the target address]), that the personal device has a respective access level that is greater than or equal to the access level (Barnes, [0049 - Access permissions specifying which privilege levels can access the page]; [0034 - In response to a memory access request specifying a target address, the memory access circuitry selects some target addresses/access requests for which the guard tag checking is not carried out and only the memory access itself is carried out, thereby implying a higher access level for the personal device]) of the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0049 - A page table entry can specify tag-guard control information which is used to control whether guard tag checking happens when access is made to an address within that page of addresses]; [Fig. 6: steps 100,102,104,110]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson, Le, Crawford, Ayrapetyan for the benefit of having the memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address (Barnes, 0030).
As per Claim 12, the rejection of claim 10 is incorporated, and Hansson, Le, Crawford, Ayrapetyan disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device fails to retrieve the data stored in the first DRAM address and the second DRAM address (Barnes, [0033 - Error reporting mechanism in case of failure]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the respective tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device (Barnes, [0032 - Memory access circuitry compares an address tag that is associated with the target address with a guard tag that is stored in the memory system is associated with a block of one or more memory locations/first and second which includes the addressed location identified by the target address]), that the personal device has a respective access level that is less than the access level (Barnes, [0049 - Access permissions specifying which privilege levels can access the page]; [0034 - In response to a memory access request specifying a target address, the memory access circuitry and selects target addresses/access requests for which the guard tag checking is carried out as well as the memory access itself, thereby implying a lower access level for the personal device]) of the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0053 – In Fig. 3, step 56 the memory access circuitry 15 compares the address tag 40 with the guard tag 32 obtained at step 54. At step 58 an indication of whether a match is detected between the guard tag and the address tag is generated by the memory access circuitry 15, e.g. mismatch reporting indication]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson, Le, Crawford, Ayrapetyan for the benefit of having the memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address (Barnes, 0030).
As per Claim 14, the rejection of claim 13 is incorporated, and Hansson, Le, Crawford, Ayrapetyan disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device retrieves the data stored in the first DRAM address (Barnes, [0032 - The memory access circuitry generates an indication of whether a match is detected between the guard tag and the address tag. This indication is used to control whether the memory access is allowed to succeed]) and fails to retrieve the data stored in the second DRAM address (Barnes, [0033 - Error reporting mechanism in case of failure]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator program 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the respective tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device, that the personal device has a respective access level that is greater than (Barnes, [Fig. 2: guard tag B/personal device]) or equal to the first access level (Barnes, [Fig. 2:guard tag C is lower than guard tag B]) and the personal device has the respective access level that is less than the second (Barnes, [Fig. 2:guard tag A is above]) access level (Barnes, [0053 – In Fig. 3, at step 56 the memory access circuitry 15 compares the address tag 40 with the guard tag 32 obtained at step 54. At step 58 an indication of whether a match is detected between the guard tag and the address tag is generated by the memory access circuitry]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson, Le, Crawford, Ayrapetyan for the benefit of having personal device interact with the simulator program which includes memory access logic for accessing addressed locations and carrying out guard tag checking. The simulator program can also control whether to perform the comparison of a guard tag and an address tag and report whether any mismatch between the guard tag and the address tag has been detected (Barnes, 0061).
As per Claim 15, the rejection of claim 14 is incorporated, and Hansson, Le, Crawford, Ayrapetyan disclose a DRAM memory device.
Barnes further discloses,
retrieving, by the controller (Barnes, [Fig. 1: at least components 4,6,14,15,19]; [Fig. 1: at least components memory access circuitry 15, tag 19 represent the tag controller]; [Fig. 8]), the data stored in the first DRAM address and the data stored in the second DRAM address through first input/output (I/O) lines (Barnes, [Figs. 1, 8]; [0061 – In Fig. 8, the simulator program 210 includes memory access logic 216 for accessing addressed locations and for carrying out guard tag checking]; [0052 – In Figs. 1-2, when a tag-guarded memory access is performed, a comparison is made between address tag 40 and guard tag 32 and a determination as to whether they match. The comparison is performed between the memory access circuitry 15 and physical memory 18, thereby using first I/O lines; In Fig. 2, the blocks denote the data and their respective DRAM addresses]) and retrieving, by the personal device, the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0061 – In Fig. 8, simulator program 210 includes memory access logic 216 for accessing addressed locations and for carrying out guard tag checking]; [0062 - The tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations/first and second comprising an addressed location identified by the target address, thereby providing the data in first and second addresses to the personal device]) through second I/O lines that are different than the first I/O lines (Barnes, [0061 – In Fig. 8, simulator program 210 provides a program interface/API virtual to target code 200 which includes applications/user etc., thereby implying communicating by the personal device via the API using second I/O lines]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson, Le, Crawford, Ayrapetyan for the benefit of having personal device interact with the simulator program which includes memory access logic for accessing addressed locations and carrying out guard tag checking. The simulator program can also control whether to perform the comparison of a guard tag and an address tag and report whether any mismatch between the guard tag and the address tag has been detected (Barnes, 0061).
Response to Arguments
The Applicant's arguments filed on August 19, 2026 have been fully considered, but they are not persuasive.
Applicant argues,‘Applicant has amended the claims to strike those amendments and replace them with new amendments’. (Rem, Pg. 8)
Response: The new amendments have a number of issues. Please see the new 112(a)’s and 112(b)’s.
One of the new amendments recites, ‘receive a memory access request, which includes the respective tag identifier….’. But when a memory access request comes into a controller, it doesn't include the entire table or every single identifier at once. It includes one specific, single tag identifier (the one associated with that request).
By using the definite article ‘the’ combined with ‘respective’, the claim implies that the incoming request includes a previously defined, singular tag identifier, or it confuses a single incoming tag with the entire ‘plurality of tag identifiers’ mentioned in the prior table-maintaining limitation. This creates an indefinite loop. Please see the 112(b).
Since all dependent claims carry forward the phrase ‘the respective tag identifier’, this creates a systemic 35 U.S.C. 112(b) issue that flows down through the entire claim set.
The spec is self-contradictory. The spec assigns the same component or function to multiple different hardware elements without describing in detail their structural hierarchy. This creates technical issues resulting in 112(a)’s and 112(b)’s.
Applicant further argues,‘As such, Hansson, Ayrapetyan, and Tummala, alone or in combination, do not teach, suggest, or render obvious each and every element of claims 1, 8, and 19, as amended’. (Rem, Pg. 10)
Response: The amendments are improper, especially claim 19.
As mentioned above, the spec reads like a casual wish list to cover all outcomes rather than a clear description of specific hardware boundaries.
The spec merely provides a series of disparate and conflicting examples. Specifically, that the tag match table can be maintained by a main controller, a tag controller, a tag match engine, or stored ‘inside a register’ and ‘outside of the register’.
By asserting that the table can reside essentially anywhere (both inside and outside a register, and within multiple unlinked structures), the spec fails to describe any structural commonality governing the implementation. The disclosure outlines a broad research plan (covering all possible ways to use a tag match table in a DRAM) rather than a completed invention that has been fully conceptualized, implemented and possessed.
That being said, relying on improper amendments to mischaracterize prior art, invalidates the argument. Please see the O/A.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
