DETAILED ACTION
Claims 1-20 were restricted. Claims 8-20 were elected. Claims 2-7 are withdrawn.
Claims 1,8-12,14,16-20 are amended. Claims 1,8-20 are pending.
Priority: 7/30/2024
Assignee: Micron
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 1 there is insufficient antecedent basis for this limitation in the claim.
1.Amended Claim 1 is rejected for reciting a limitation with antecedent basis issues.
Amended Claim 1 recites, ‘….a memory access request which includes a particular tag identifier…. wherein a particular tag identifier …’.
Claim(s) 1, 8-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
1.Amended Claims 1,8,19 is rejected for reciting limitations that are unclear, inconsistent and indefinite.
Amended Claim 8 recites, ‘…..wherein the particular tag identifier links the first DRAM address with a second DRAM address of the respective plurality of DRAM addresses’.
The spec does not recite this limitation.
Para-0028 of the spec recites, ‘The table (e.g., tag match table) 226 can include a DRAM address list 228. And Para-0029 recites, ‘The DRAM address list 228 can be a list that includes the addresses of the locations at which data is stored that has been linked by a tag identifier’.
As per spec, Paras-0028,0029, the ‘tag identifier’ being privileged is associated with the tag match table and the addresses are linked by the ‘tag identifier’. Claim 8 also recites the same association (see first limitation).
But the ‘particular tag identifier’, being less-privileged, is associated with the request. Therefore the amended limitation, ‘….wherein the particular tag identifier links the first DRAM address with a second DRAM address….’, conflicts with the spec and hence is indefinite.
Since the limitation fails to align with the spec and does not clearly define the metes and bounds of the disclosure with respect to the spec, it is indefinite and rejected accordingly. Claims 1,19 have the same issue.
A ‘link’ is a structural/logical relationship. The ‘(particular) tag identifier’ is a passive variable. It does not have the logic circuitry to determine the ‘link’. Accordingly it is unclear which active component determines the ‘link’ between the two addresses.
2.Amended Claims 1,8,19 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Amended Claim 8 recites, ‘receiving, by the controller, a memory access request which includes a particular tag identifier, for a first DRAM address….’. The limitation does not align with the spec.
Fig. 4, Para-0039 recites, ‘At step 444, the method 440 can include receiving, by a controller, a memory access request including a particular tag identifier’.
Whether it is the ‘tag identifier’ or ‘particular tag identifier’, the spec does not explicitly recite the contents/format of the identifiers.
Para-0029 of the spec recites, ‘The tag identifier value can be a string of numbers and/or letters’. There is no disclosure of parsing identifier strings to extract and determine the parameters in it.
The spec does not explicitly disclose parsing the ‘particular tag identifier’ string. So how any information about the ‘first DRAM address’ is determined is unclear. How the ‘particular tag identifier’ serves as an ‘ID’ for the data at the first DRAM address lacks written description support.
Therefore the limitation, ‘a request ….includes a particular tag identifier, for a first DRAM address….’, is an unverified extrapolation.
Since amended Claim 8 recites a limitation that is inconsistent with the spec by reciting a statement that extrapolates the spec, the scope of the disclosure becomes uncertain. Hence claim 8 is rejected. Claims 1,19 have the same issue.
3.Amended Claims 1,8,19 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Amended Claim 8 recites, ‘retrieving, by the controller, the first DRAM address corresponding to the particular tag identifier from the tag match table’. Nowhere does the spec does not recite this limitation.
Fig. 4, Para-0040 recites, ‘At step 446, the method 440 can include retrieving, by the controller, the respective plurality of DRAM addresses corresponding to the particular tag identifier from the tag match table’.
Since the limitation, ‘retrieving, by the controller, the first DRAM address….’, fails to align with the spec and does not clearly define the metes and bounds of the disclosure with respect to the spec, it is indefinite and rejected accordingly. Claims 1,19 have the same issue.
4.Claims 1,8,19 are rejected for reciting a limitation that unclear, incorrect and indefinite.
Amended Claim 8 recites ‘access memory…. corresponding to the first DRAM address and the second DRAM address….’. This limitation is incorrect.
Amended Claim 8 previously recites, ‘retrieving, by the controller, the first DRAM address ….from the tag match table’. As recited, the ‘second DRAM address’ was not retrieved from the tag match table. (Also see related 112(b) above)
So, if only the ‘first DRAM address’ was retrieved, and the ‘second DRAM address’ was not retrieved, then it is unclear how memory corresponding to the ‘second DRAM address’ is accessed.
Since the limitation fails to align with the spec, it is indefinite and rejected accordingly. Claims 1,19 have the same issue.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 8-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Claims 1,8,19 are rejected for reciting a limitation that is unsupported by the spec.
Amended Claim 8 recites, ‘retrieving, by the controller, the first DRAM address corresponding to the particular tag identifier from the tag match table’. Nowhere does the spec does not recite this limitation.
Spec, Fig. 4, Para-0040 recites, ‘At step 446, the method 440 can include retrieving, by the controller, the respective plurality of DRAM addresses corresponding to the particular tag identifier from the tag match table’.
More importantly, the spec does not disclose the specific contents/format of the ‘particular tag identifier’ and the ‘tag identifier’. Spec, Para-0029 recites, ‘The tag identifier value can be a string of numbers and/or letters’. How the string is constructed, what the specific contents of the string are and how this ‘string’ is parsed to extract the address(es) and other relevant information, is undisclosed. The spec does not provide any working examples to show possession of determining the ‘first DRAM address’ in the ‘particular tag identifier’. In short, the spec does not disclose how the ‘particular tag identifier’ is used.
Neither the spec nor the claim recite the detailed steps of how the ‘retrieving….’ is performed. For example, to retrieve any address(es), corresponding to the ‘particular tag identifier’ from the table, the spec does not disclose analyzing the ‘particular tag identifier’ by the controller. Based on the analysis, a search and match algorithm would locate the correct ‘tag identifier’ from the table to determine the associated ‘plurality of addresses’. But the spec is silent about the search and retrieval by the controller. Para-0029 of the spec recites a 1-line, passing mention of a search, but no details of the search steps and/or algorithm are provided. This lack of information shows lack of possession of the ‘search and locate’ function by the controller to locate the ‘plurality of addresses’ from the tag match table. See MPEP § 2163.
The spec also does not disclose how the controller determines which address or addresses are linked/associated with the ‘first DRAM address’ received via the ‘particular tag identifier’. This demonstrates lack of possession of the ‘link’ determination between first DRAM address and other DRAM addresses.
Though the claim recites a ‘tag match table’ to represent a multi-bank DRAM architecture, how the tag match table is populated/built is undisclosed. The contents of a single row of the table, as it relates to the ‘particular tag identifier’ and matched ‘tag identifier recited in claim 8, are undisclosed. How the table is used to store and retrieve values is undisclosed. Since the spec does not recite how to build and use the table, the spec fails to tie the claimed functionality of ‘retrieving, by the controller, the first DRAM address from the tag match table’. Furthermore, since the table cannot be searched successfully, the controller cannot ‘access memory corresponding to the first DRAM address and the second DRAM address’, with certainty.
In short, the claim and spec recite a functional result (‘retrieving… from the tag match table’) without disclosing the specific steps to show how the result is achieved. This lack of disclosure demonstrates that the applicant's possession of the ‘tag match table’ to retrieve address(es) based on the received ‘particular tag identifier’, at the time of filing was incomplete.
By reciting, ‘retrieving, by the controller,….’, the claim recites broad functional language that covers a wide field of search-and-locate technology. But the spec does not provide sufficient written description to support the broad scope recited in ‘retrieving…’. Hence Claim 8 is rejected for reciting a limitation that is unsupported by the spec. Claims 1,19 have the same issue.
2.Amended Claims 9-12, 14, 16-17,20 are rejected for reciting limitations that are unsupported by the spec.
Claims 9-12, 14, 16-17,20 have been improperly amended by substituting ‘tag identifier’ with ‘particular tag identifier’.
Though the claims substitute ‘tag identifier’ with ‘particular tag identifier’, the spec only recites ‘tag identifier’ in all the embodiments. The spec does not demonstrate that the inventor was in possession of the limitations substituted with ‘particular tag identifier’ at the time of filing.
Claims 9-12,14,16-17,20, submitted as part of the original disclosure recited the limitations using ‘tag identifier’ to elaborate the storage capabilities of the ‘tag identifier’. According to the spec, the ‘tag identifier’ which is associated with the tag match table has a privileged status compared to the less-privileged ‘particular tag identifier’ which is associated with the request. Therefore replacing the same limitations with the less-privileged ‘particular tag identifier’ is not a true narrowing of the original disclosure, but rather a new idea not originally described. Hence claims 9-12,14,16-17,20 recite new matter and are rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-10, 13, 16-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hansson et al (20190384718) in view of Ayrapetyan et al (20210294755) and Tummala et al (11288188).
As per Claim 1, it is similar to claim 8 and therefore the same mappings are incorporated.
As per Claim 8, Hansson discloses a method (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2]; [0051 - Fig. 2 shows a DRAM-based storage circuit 30]; [0057 - Fig. 6 shows DRAM 64 of Fig. 5. As in Fig. 2, the DRAM 64 comprises an array 32 of storage locations 34]; [0014 - A method for accessing information from storage circuitry comprising an array of storage locations arranged in rows and columns]), comprising:
maintaining, by a controller (Hansson, [0058 - In Fig. 6, control circuitry 74 receives commands provided by cache controller 62 and activate the appropriate control paths in the hardware of the DRAM unit 64 to control the row decoder 40, column multiplexer 38 and comparators 70 to perform the required operations]; [Fig. 6: at least control circuitry 74+comparison circuitry 70+row decoder 40+col multiplexer 38+configuration storage element 76]; [0022 - Fig. 6 shows storage circuitry comprising comparison circuitry 70/tag controller to compare a tag value against a subset of entries of a row buffer; So control circuitry 74+comparison circuitry 70 is the tag controller]), a tag match table (Hansson, [0054 - In Fig. 3, store the data value from each tag-data pair in the DRAM 30 or store the tag values in SRAM-based storage structure 50, thereby implying a tag-match table]) indicating correspondence between a respective tag identifier and a respective plurality of dynamic random access memory (DRAM) addresses (Hansson, [0030,0031 - Fig. 14 shows a method of processing a tag-gather command. The storage circuitry is provided with comparison circuitry which is responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of entries of the row buffer, therefore implying the correspondence between a tag identifier and addresses]) for each of a plurality of tag identifiers (Hansson, [0023 – Fig. 7 shows tags and data within a row of storage cells]; [0033 - When the storage circuitry is used as a cache, the storage locations are allocated in pairs with each pair comprising one location/address for storing a cached data value and another storage location/address for storing a corresponding tag value. So the tag value identifies part of the address of the data value in the other location of the pair]);
receiving, by the controller (Hansson, [Fig. 6: at least control circuitry 74+comparison circuitry 70+row decoder 40+col multiplexer 38+configuration storage element 76]), a memory access request which includes a particular tag identifier for a ([See 112(b)]) first DRAM address (Hansson, [0047 - In response to a cache access request specifying a target address, the storage circuitry issues the tag-matching command specifying a tag value determined as a function of said target address/first DRAM address]; [0068 - Fig. 11 shows processing of a tag-matching command. At step 110, DRAM 64 receives a tag-matching command specifying a row address 42 and a tag value 72 and read/write, from the cache controller 62; Since the claim does not define the format of ‘a particular tag identifier’, the citation is a valid interpretation]]) of the respective plurality of DRAM addresses (Hansson, [0037 - A single bank of storage locations/addresses, or two or more banks of storage locations]),
wherein the particular tag identifier ([See 112(b)]) links (Hansson, [0056 – For a read operation, the cache controller 62 issues a tag-matching read command, and provides the DRAM 64 with a row address identifying the required row of DRAM locations/addresses and a tag value to be compared with the tags stored in that row of DRAM locations, thereby implying the linkage between the first and second DRAM address of the plurality of addresses]) the first DRAM address (Hansson, [0035 - The target storage location/first address is the paired storage location that stores the data value associated/link with the tag value stored in the storage location for which the hit was detected]) with a second DRAM address of the respective plurality of DRAM addresses (Hansson, [0048 - Fig. 1 shows a 4-way set associative cache 2. The group of locations at corresponding locations within each set is referred to as a ‘way’ 12, e.g. way 0,way 1,way 2 etc.; It is well-known that a set-associative cache in a DRAM maps/associates/links memory addresses by dividing the cache into N-way sets, using index bits to select a specific set, and tag bits to identify the block within that set. Since the spec does not disclose how the ‘association/link’ is achieved, the citation is a valid interpretation]);
retrieving, by the controller (Hansson, [Fig. 6: at least control circuitry 74+comparison circuitry 70+row decoder 40+col multiplexer 38+configuration storage element 76]), the first DRAM address ([See 112(b)]) corresponding to the particular tag identifier from the tag match table (Hansson, [0068 – In Fig. 11, step 112, control circuitry 74 controls the comparison circuitry 70 to compare the tag value 72 with each of a subset of entries 68 of the row buffer 36 with the subset of entries being identified by the configuration storage element 76]);
access (Hansson, [0068 – In Fig. 11, step 114, the control circuitry determines whether the comparison circuitry 70 has identified a hit or miss. In the case of a hit, at step 116 the control circuitry 74 triggers a read or write operation targeting the storage cell associated with the matching tag entry]), by the controller, memory corresponding to the first DRAM address and the second DRAM address (Hannson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2; In a set-associative cache, because multiple memory locations map/link to the same set, the cache compares the tag bits of the incoming address/first address against all tags within that specific set simultaneously, thereby accessing the memory corresponding to the first and second addresses]; [0049 – In Fig. 1, a hit signal is asserted for the way 12 containing the matching tag, and the corresponding data value 6 is read out from cache entry 4 in the matching way 12 of the indexed set 10. An offset portion 20 of the target address identifies the location of the required data within the returned data value 6]) without the controller receiving a memory access request for the second DRAM address (Hansson, [0031 - The storage circuitry is used more effectively as a set-associative cache, since a set of locations can have their tags looked up in response to a single tag-matching command, rather than requiring a number of separate read operations/request]).
It is well-known that the controller is a hardware component featuring multiple components. Ayrapetyan further clarifies the controller and tag-match table as follows,
maintaining, by a controller (Ayrapetyan, [Fig. 1: at least processing pipeline 4, bounded pointer control circuitry 90+ memory allocator/deallocator circuitry 92, execute]; [Fig. 1: at least bounded pointer control circuitry 90+ memory allocator/deallocator circuitry 92, is the tag controller]), a tag match table (Ayrapetyan, [Fig. 1: capability registers 60]) indicating correspondence between a respective tag identifier and a respective plurality of dynamic random access memory (DRAM) addresses (Ayrapetyan, [0076 – In Fig. 1, main memory 50 is physically addressed, thereby implying the controller is coupled to DRAM arrays; It is well known that due to its capacity and cost, DRAM is used in a cache hierarchy]) for each of a plurality of tag identifiers (Ayrapetyan, [0080 – In Fig. 1, each bounded pointer register 60 includes a pointer value 62/tag ID that is used to determine an address of a data value to be accessed, and range information 64 specifying an allowable range of addresses when using the corresponding pointer 62. The bounded pointer register 60 also includes restrictions information 66 define one or more restrictions/permissions on the use of the pointer, thereby implying a tag-match table]);
wherein the particular tag identifier links ([See 112(b)]) the first DRAM address with a second DRAM address of the respective plurality of DRAM addresses (Ayrapetyan, [0007 - The revocable bounded pointer/particular tag identifier providing a pointer value/first DRAM address and range information identifying an address range of the memory region/second DRAM address; Here the revocable bounded pointer is equivalent to any kind of tag identifier, including ‘tag identifier’ and ‘particular tag identifier’, and it provides the claimed link between the addresses. Since neither the claim nor the spec recite how the ‘link’ between the addresses is created, the citation is a valid interpretation]);
access, by the controller, memory corresponding to the first DRAM address and the second DRAM address without the controller receiving a memory access request for the second DRAM address (Ayrapetyan, [0027 - The range information associated with a bounded pointer/first address will identify the range of memory addresses forming the memory region. Whenever it is desired to access an address within the memory region, that memory address/second address can be generated with reference to such a bounded pointer, thereby implying that the first DRAM address and the second DRAM address can be accessed due to the region linkage between them and with a single memory request]).
Some functions of the controller include transaction scheduling, address translation, command scheduling, electrical signaling and DRAM access.
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson, for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers, wherein the bounded pointer generation circuitry generates at least a revocable bounded pointer for use in accessing the memory region, the revocable bounded pointer providing a pointer value and range information identifying an address range in the memory region (Ayrapetyan, 0029).
Neither the claim nor the spec recite how the link/association between the two addresses is achieved. Tummala clarifies the association as follows,
wherein the particular tag identifier (Tummala, [Fig. 6: step 602, receive a request to access data at a 1st data location in a 1st page and associated metadata in a 2nd page, thereby implying that the request includes metadata/particular tag identifier]) links the first DRAM address (Tummala, [Fig. 6: 1st data location, 1st page]) with a second DRAM address (Tummala, [Fig. 6: 2nd data location, 2nd page]) of the respective plurality of DRAM addresses (Tummala, [Fig. 6: Step 604-1st data location configured to store metadata? Yes; Step 608-Determine 2nd data location in 2nd page; Step 610-Access data in 2nd data location in 2nd page; Since data in the 2nd data location is accessed based on the request, it implies that the first DRAM address/1st data location is linked/associated with the second DRAM address/2nd data location]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address linking of Tummala into the DRAM memory device of Hansson,Ayrapetyan for the benefit of dynamic metadata relocation wherein if the target of a data access request is a location in a first page that is configured to store metadata rather than data, then a second location in a second page is determined, and the requested data is accessed at the second location. The associated metadata is accessed at the location in the first page, which is configured in the virtual domain to store data but is configured in the physical domain to store the metadata associated with the data in the first page (Tummala, Abstract).
As per Claim 9, the rejection of claim 8 is incorporated, and Hansson, Ayrapetyan,Tummala disclose,
classifying, using the particular tag identifier, data stored in a first DRAM address and data stored in a second DRAM address as public or private (Ayrapetyan, [0085 – In Fig. 3, with each data block 115, there is a tag field 120, which is a single bit field referred to as the tag bit, which is set to identify that the associated data block represents a capability, and is cleared to indicate that the associated data block represents normal data; Here clear bit/normal is interpreted as public]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson,Tummala for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 10, the rejection of claim 9 is incorporated, and Hansson, Ayrapetyan,Tummala disclose,
assigning, using the particular tag identifier, an access level to the data stored in the first DRAM address and the data stored in the second DRAM address (Ayrapetyan, [0105 – Figs. 7A to 7C show the use of headers for each allocated memory region of data]; [0109 - the permissions field 330 can be provided to store at least a portion of the permission bits of the bounded pointer]; [0110 – In Fig. 7C, the revocable bounded pointer includes a pointer field 345 for storing a pointer value, a base field 350 for identifying the base address of the memory region, a limit field 355 for identifying the limit address, a permissions field 360/access level for storing various permissions bits, a small token field 365 for storing a small token value, etc.; Since the claim does not define ‘access level’ and its representation, the citation is a valid interpretation]) in response to the particular tag identifier classifying the data stored in the first DRAM address and the data stored in the second DRAM address as private (Ayrapetyan, [0085 – In Fig. 3, in association with each data block 115, there is a tag field 120, which is a single bit field referred to as the tag bit, which is set to identify that the associated data block represents a capability/private]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson,Tummala for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 13, the rejection of claim 10 is incorporated, and Hansson, Ayrapetyan,Tummala disclose,
wherein the data stored in the first DRAM address has a first access level and the data stored in the second DRAM address has a second access level that is a different access level than the first access level (Ayrapetyan, [0105 - Figs. 7A-7C show the use of headers for each allocated memory region of data]; [0110 - FIG. 7C shows a revocable bounded pointer 340, and its various fields. The revocable bounded pointer includes a pointer field 345 for storing a pointer value, a base field 350 for identifying the base address of the memory region, a limit field 355 for identifying the limit address, a permissions field 360 for storing various permissions bits. An E bit field 375 can be provided which can be used to identify whether the content of the bounded pointer is encoded or not, thereby implying that being encoded or not determines the access level; Since the claim does not define ‘access level’, how it is represented or determined, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson,Tummala for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
As per Claim 16, the rejection of claim 8 is incorporated, and Hansson discloses,
identifying, by the particular tag identifier, data stored in a first DRAM address and the data stored in a second DRAM address (Hansson, [0033 - The tag value identifies part of the address of the data value in the other location of the pair]) in response to the controller associating (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2. The cache 2 has a number of cache entries 4 each comprising a tag-data pair]) the data stored in the first DRAM address with the data stored in the second DRAM address (Hansson, [T0,D0]; [T1,D1]; [0033 - When the storage circuitry is used as a cache, the storage locations may be allocated in pairs with each pair comprising one location for storing a cached data value and another storage location for storing a corresponding tag value]; [0047 - When a hit is identified in response to the tag-matching command, the storage circuitry outputs to the cache controller at least one of: a data value corresponding to a target storage location other than the storage location associated with the matching entry, and information for identifying which storage location of the storage circuitry is the target storage location, thereby showing the association between the data stored in the first and second DRAM addresses; Since the claim does not recite how the ‘association’ is made, the citation is a valid interpretation]).
As per Claim 17, the rejection of claim 16 is incorporated, and Hansson discloses,
identifying, by the particular tag identifier, data stored in a third DRAM address and data stored in a fourth DRAM address (Hansson, [0033 - The tag value identifies part of the address of the data value in the other location of the pair]) in response to the controller associating (Hansson, [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2. The cache 2 has a number of cache entries 4 each comprising a tag-data pair]) the data stored in the third DRAM address to the data stored in the fourth DRAM address (Hansson, [T2,D2]; [T3,D3]; [0033 - When the storage circuitry is used as a cache, the storage locations may be allocated in pairs with each pair comprising one location for storing a cached data value and another storage location for storing a corresponding tag value]; [0047 - When a hit is identified in response to the tag-matching command, the storage circuitry may output to the cache controller at least one of: a data value corresponding to a target storage location other than the storage location associated with the matching entry, and information for identifying which storage location of the storage circuitry is the target storage location]).
As per Claim 18, the rejection of claim 17 is incorporated, and Hansson discloses,
wherein the first DRAM address and the third DRAM address are stored in a first memory bank (Hansson, [Fig. 9: Bank0 – T0,T2]; [0064 - Fig. 8 shows an example with two banks of DRAM]), and the second DRAM address and the fourth DRAM address are stored in a second memory bank (Hansson, [Fig. 9: Bank1 – T1,T3]; [0065 - In a multi-bank DRAM implementation, it is useful to interleave the data values and tag values of a number of tag-data pairs among corresponding rows of separate banks as shown in Fig. 9]).
As per Claim 19, Hansson discloses a system (Hansson, [0047 - An apparatus, e.g. a data processing system, comprises of a storage circuitry and a cache controller to control accesses to cached data stored in the storage circuitry]; [0048 - Fig. 1 shows the logical functionality of a tag lookup operation for a set-associative cache 2]; [0051 - Fig. 2 shows a DRAM-based storage circuit 30]), comprising:
a host (Hansson, [Fig. 5: controller 62]);
a memory device coupled to the host (Hansson, [0056 - Fig. 5 shows a data processing apparatus 60 comprising a cache controller 62/host and DRAM storage circuitry 64/DRAM memory device]),
wherein the memory device includes: a dynamic random access memory (DRAM) array (Hansson, [0057 - As in Figs. 2,6, DRAM 64 comprises an array 32 of storage locations 34, row buffer 36, column multiplexer 38 and row decoder 40. The row buffer 36 includes a number of entries 68, each entry 68 corresponding to one column of storage array 32]);
a memory device controller (Hansson, [Fig. 6: at least control circuitry 74+comparison circuitry 70+row decoder 40+col multiplexer 38+configuration storage element 76]; [0058 – In Fig. 6, control circuitry 74 is provided to receive commands provided by the cache controller 62 and activate the appropriate control paths in the hardware of the DRAM unit 64 to control the row decoder 40, column multiplexer 38 and comparators 70 to perform the required operations]) coupled to the DRAM array and configured to receive, from the host, a request for data stored in the DRAM array (Hansson, [0056 – In Fig. 5, for a read operation, cache controller 62/host issues a tag-matching read command, and provides DRAM 64 with a row address identifying the required row of DRAM locations and a tag value to be compared with the tags stored in that row of DRAM locations]),
wherein the memory device controller (Hansson, [Fig. 6]) includes:
a tag register configured to store a tag identifier name (Hansson, [0061 – Fig. 6:configuration storage element 76]; [0061 – In Fig. 6, configuration data 76 identifies the entries storing the tags and control the comparators 70 to compare those entries with the tag value 72, thereby implying that the identification uses a tag identifier name/ID]);
and a tag controller (Hansson, [Fig. 6: control circuitry 74+comparison circuitry 70]) configured to:
Ayrapetyan discloses,
wherein the memory device controller (Ayrapetyan, [Fig. 1: at least processing pipeline 4, bounded pointer control circuitry 90+ memory allocator/deallocator circuitry 92, execute]) includes:
a tag register configured to store a tag identifier name (Ayrapetyan, [0110 – As per Fig. 7C, bounded pointer register 385 shows a small token field 365 for storing a small token value]);
and a tag controller (Ayrapetyan, [Fig. 1: at least bounded pointer control circuitry 90+ memory allocator/deallocator circuitry 92]) configured to:
The remaining limitations are similar to claims 1,8 and therefore the same mappings are incorporated.
As per Claim 20, the rejection of claim 19 is incorporated and Hansson, Ayrapetyan,Tummala disclose,
the particular tag identifier indicates whether data stored in a first DRAM address and data stored in a second DRAM address are in a first mode or a second mode (Ayrapetyan, [0080 – In Fig. 1, restriction 66 field of each bounded pointer register 60 could be used to restrict the types of instructions which may use pointer 62/tag ID, or the modes of the pipeline 4 in which the pointer can be used]);
the first mode allows for a greater level of interactivity with the data stored in the first DRAM address and the data stored in the second DRAM address than the second mode (Ayrapetyan, [0080 - The range information 64 and restriction information 66 define capabilities within which the pointer 62 is allowed to be used. When an attempt is made to use a pointer 62 outside the defined capabilities, an error can be triggered. The range information 64 can be useful for ensuring that pointers remain within certain known bounds and do not stray to other areas of the memory address space which might contain sensitive or secure information, thereby establishing ‘level of interactivity’. Since the claim does not recite how ‘level of interactivity’ is determined, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tag-match table of Ayrapetyan into the DRAM memory device of Hansson,Tummala for the benefit of using an apparatus that comprises memory allocation circuitry to allocate a memory region in memory, and bounded pointed generation circuitry to generate bounded pointers (Ayrapetyan, 0029).
Claims 11-12, 14-15 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Hansson et al (20190384718) in view of Ayrapetyan et al (20210294755), Tummala et al (11288188) and Barnes (20200225872).
As per Claim 11, the rejection of claim 10 is incorporated, and Hansson, Ayrapetyan disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device retrieves the data stored in the first DRAM address and the second DRAM address (Barnes, [0032 - The memory access circuitry generates an indication of whether a match is detected between the guard tag and the address tag. This indication is used to control whether the memory access is allowed to succeed]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator program 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the particular tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device (Barnes, [0032 - Memory access circuitry compares an address tag that is associated with the target address with a guard tag that is stored in the memory system is associated with a block of one or more memory locations/first and second, which includes the addressed location identified by the target address]), that the personal device has a respective access level that is greater than or equal to the access level (Barnes, [0049 - Access permissions specifying which privilege levels can access the page]; [0034 - In response to a memory access request specifying a target address, the memory access circuitry selects some target addresses/access requests for which the guard tag checking is not carried out and only the memory access itself is carried out, thereby implying a higher access level for the personal device]) of the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0049 - A page table entry can specify tag-guard control information which is used to control whether guard tag checking happens when access is made to an address within that page of addresses]; [Fig. 6: steps 100,102,104,110]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson,Ayrapetyan,Tummala for the benefit of having the memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address (Barnes, 0030).
As per Claim 12, the rejection of claim 10 is incorporated, and Hansson, Ayrapetyan,Tummala disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device fails to retrieve the data stored in the first DRAM address and the second DRAM address (Barnes, [0033 - Error reporting mechanism in case of failure]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the particular tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device (Barnes, [0032 - Memory access circuitry compares an address tag that is associated with the target address with a guard tag that is stored in the memory system is associated with a block of one or more memory locations/first and second which includes the addressed location identified by the target address]), that the personal device has a respective access level that is less than the access level (Barnes, [0049 - Access permissions specifying which privilege levels can access the page]; [0034 - In response to a memory access request specifying a target address, the memory access circuitry and selects target addresses/access requests for which the guard tag checking is carried out as well as the memory access itself, thereby implying a lower access level for the personal device]) of the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0053 – In Fig. 3, step 56 the memory access circuitry 15 compares the address tag 40 with the guard tag 32 obtained at step 54. At step 58 an indication of whether a match is detected between the guard tag and the address tag is generated by the memory access circuitry 15, e.g. mismatch reporting indication]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson,Ayrapetyan,Tummala for the benefit of having the memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address (Barnes, 0030).
As per Claim 14, the rejection of claim 13 is incorporated, and Hansson, Ayrapetyan,Tummala disclose a DRAM memory device.
Barnes further discloses,
wherein a personal device retrieves the data stored in the first DRAM address (Barnes, [0032 - The memory access circuitry generates an indication of whether a match is detected between the guard tag and the address tag. This indication is used to control whether the memory access is allowed to succeed]) and fails to retrieve the data stored in the second DRAM address (Barnes, [0033 - Error reporting mechanism in case of failure]) in response to:
a DRAM memory device (Barnes, [Fig. 8: simulator 210 with memory access logic 216]; [0061 – In Fig. 8, simulator program 210 is stored on computer-readable storage medium 212; Since simulator 210 interacts with the personal device, it implies that the storage medium is volatile memory/DRAM as it facilitates rapid communication with the personal device by serving as the high-speed, main temporary storage/staging area for data. DRAM bridges the speed gap compared to slower hard drives or SSDs/NVM]) receiving a request from the personal device for the particular tag identifier (Barnes, [0034 - A memory access request specifying a target address]; [Fig. 8: Request from target code 200/personal device via API-virtual]);
determining, by the DRAM memory device, that the personal device has a respective access level that is greater than (Barnes, [Fig. 2: guard tag B/personal device]) or equal to the first access level (Barnes, [Fig. 2:guard tag C is lower than guard tag B]) and the personal device has the respective access level that is less than the second (Barnes, [Fig. 2:guard tag A is above]) access level (Barnes, [0053 – In Fig. 3, at step 56 the memory access circuitry 15 compares the address tag 40 with the guard tag 32 obtained at step 54. At step 58 an indication of whether a match is detected between the guard tag and the address tag is generated by the memory access circuitry]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson,Ayrapetyan,Tummala for the benefit of having personal device interact with the simulator program which includes memory access logic for accessing addressed locations and carrying out guard tag checking. The simulator program can also control whether to perform the comparison of a guard tag and an address tag and report whether any mismatch between the guard tag and the address tag has been detected (Barnes, 0061).
As per Claim 15, the rejection of claim 14 is incorporated, and Hansson, Ayrapetyan,Tummala disclose a DRAM memory device.
Barnes further discloses,
retrieving, by the controller (Barnes, [Fig. 1: at least components 4,6,14,15,19]; [Fig. 1: at least components memory access circuitry 15, tag 19 represent the tag controller]; [Fig. 8]), the data stored in the first DRAM address and the data stored in the second DRAM address through first input/output (I/O) lines (Barnes, [Figs. 1, 8]; [0061 – In Fig. 8, the simulator program 210 includes memory access logic 216 for accessing addressed locations and for carrying out guard tag checking]; [0052 – In Figs. 1-2, when a tag-guarded memory access is performed, a comparison is made between address tag 40 and guard tag 32 and a determination as to whether they match. The comparison is performed between the memory access circuitry 15 and physical memory 18, thereby using first I/O lines; In Fig. 2, the blocks denote the data and their respective DRAM addresses]) and retrieving, by the personal device, the data stored in the first DRAM address and the data stored in the second DRAM address (Barnes, [0061 – In Fig. 8, simulator program 210 includes memory access logic 216 for accessing addressed locations and for carrying out guard tag checking]; [0062 - The tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations/first and second comprising an addressed location identified by the target address, thereby providing the data in first and second addresses to the personal device]) through second I/O lines that are different than the first I/O lines (Barnes, [0061 – In Fig. 8, simulator program 210 provides a program interface/API virtual to target code 200 which includes applications/user etc., thereby implying communicating by the personal device via the API using second I/O lines]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the personal device of Barnes into the DRAM memory device of Hansson,Ayrapetyan,Tummla for the benefit of having personal device interact with the simulator program which includes memory access logic for accessing addressed locations and carrying out guard tag checking. The simulator program can also control whether to perform the comparison of a guard tag and an address tag and report whether any mismatch between the guard tag and the address tag has been detected (Barnes, 0061).
Response to Arguments
The Applicant's arguments filed on January 21, 2026 have been fully considered, but they are not persuasive.
In an attempt to overcome the prior art, the amendments recite improper, inconsistent and unsupported subject matter. The applicant must ensure that amendments are supported by the original disclosure to satisfy the written description requirement.
Applicant argues: However, Hansson does not teach or suggest a controller receives a request, which includes a particular tag identifier, for a first DRAM address, wherein the particular tag identifier links the first DRAM address to a second DRAM address, as recited in claims 1, 8, and 19, as amended. (Rem, Pg. 10)
Response: This argument is incorrect. The limitations are improper.
The spec does not disclose the limitation, ‘a controller receives a request, which includes a particular tag identifier, for a first DRAM address’. Please see the 112(b).
Fig. 4, Para-0039 recites, ‘At step 444, the method 440 can include receiving, by a controller, a memory access request including a particular tag identifier’. That’s all. No further information is provided.
Para-0029 of the spec recites, ‘The tag identifier value can be a string of numbers and/or letters’. There is no disclosure of parsing the ‘tag identifier’ and/or the ‘particular tag identifier’ string, by the controller, to extract and determine the parameters in it.
The spec does not explicitly disclose analyzing the ‘particular tag identifier’ to determine its contents, by the controller (or any other component). Specifically, the spec does not recite any steps that verify if the ‘first DRAM address’ is included in the ‘particular tag identifier’. What the ‘particular tag identifier’ provides and how the ‘particular tag identifier’ serves as an ‘ID’ for the data at the first DRAM address lacks written description support. Therefore the limitation is an unverified extrapolation and a potential 112(a).
Regarding the next limitation, ‘wherein the particular tag identifier links the first DRAM address to a second DRAM address’, please see the 112(b). The limitation does not align with the spec. As per Paras-0028,0029 of the spec, the addresses are linked by the ‘tag identifier’ (not the ‘particular tag identifier’).
Relying on improper limitations to mischaracterize the prior art, invalidates the argument.
Applicant further argues: ‘Further, Hansson does not teach or suggest that a controller accesses the first DRAM address and the second DRAM address without the controller receiving a memory access request for the second DRAM address, as recited in claims 1, 8, and 19, as amended’. (Rem, Pg. 10)
Response: This argument is incorrect. Please see the 112(b).
Para-0026 of the spec recites, ‘A “tag identifier” indicates an association between data stored in a first memory location and data stored in a second memory location’. Here association means ‘link’ but the spec does not disclose how the association is determined and implemented or how the ‘tag identifier’ indicates the ‘association’. Reciting a one-line statement without detailed written description suggests lack of possession about the ‘link’. A one-line statement does not demonstrate that the inventor possessed the full scope of linking addresses.
That said, the combination of Hansson,Ayrapetyan disclose the above requirement, wherein Hansson, Para-0048 recites, ‘FIG. 1 shows the logical functionality of a tag lookup operation for a set-associative cache’.
It is well-known in the prior art that a set-associative cache in a DRAM maps/associates/links memory addresses by dividing the cache into N-way sets, using index bits to select a specific set, and tag bits to identify the block within that set. As shown in Hansson, Fig. 1, the first DRAM address is split into Tag, Index, and Offset, allowing a block to reside in any of the N slots (ways) within the selected set. Because multiple memory locations map/link to the same set, the cache compares the tag bits of the first DRAM address against all tags within that specific set simultaneously. This suggests that the controller can access the first DRAM address and the linked second DRAM address.
Hansson, Para-0031 further recites, ‘The storage circuitry is used more effectively as a set-associative cache, since a set of locations can have their tags looked up in response to a single tag-matching command, rather than requiring a number of separate read operations/request’, thereby disclosing the claimed requirement. Please see O/A.
Ayrapetyan, Para-0027 discloses, ‘The range information associated with a bounded pointer/first address will identify the range of memory addresses forming the memory region. Whenever it is desired to access/single request an address within the memory region, that memory address/second address can be generated with reference to such a bounded pointer’. This implies that the first DRAM address and the second DRAM address can be accessed due to the linkage between them and with a single memory request. Please see O/A.
Examiner Notes:
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
1.‘Apparatuses and methods for compute enabled cache’, Micron, US20210224192A1 - As shown in FIG. 1A, a cache controller 115 may use firmware (e.g., microcode instructions) and/or hardware, e.g., an application specific integrated circuit (ASIC), to create a block select as metadata to a cache line and to create a subrow select as metadata to the cache line, shown in more detail in FIG. 1B. The cache controller 115 can provide cache lines having the block select and the subrow select metadata to the number of allocated locations in array 130 of memory device 120 to provide a compute enabled cache on memory device 120. (Paras:0026-0027)
2.‘Techniques for storing data and tags in different memory arrays’, Rambus, US20210089464A1 - FIG. 1A illustrates a memory integrated circuit 201 and a processor integrated circuit 202. FIG. 1B illustrates 3 memory integrated circuits 205-207. Each of the memory integrated circuits 201 and 205-207 includes memory cells such as, volatile memory cells, non-volatile memory cells, or any combination of volatile and non-volatile memory cells. The memory cells may include any memory cell technology such as, for example, DRAM, SRAM, flash, etc. Memory integrated circuit 201 functions as main memory for processor integrated circuit 202. Memory integrated circuits 205-207 function as cache memory for processor integrated circuit 202. Processor integrated circuit 202 stores data in and accesses data from memory integrated circuits 201 and 205-207. (Paras:0028-0030)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights