Prosecution Insights
Last updated: August 16, 2026
Application No. 18/789,087

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jul 30, 2024
Priority
Feb 08, 2022 — JP 2022-017651 +1 more
Examiner
YECHURI, SITARAMARAO S
Art Unit
Tech Center
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
766 granted / 894 resolved
+25.7% vs TC avg
Minimal -9% lift
Without
With
+-8.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
40 currently pending
Career history
921
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
61.8%
+21.8% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 894 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim 9-11, 13-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Swan et al. (US 8053872 B1) hereafter referred to as Swan in view of Danno et al. (US 20180182692 A1) hereafter referred to as Danno In regard to claim 1 Swan teaches a semiconductor device [see Fig. 5, Fig. 15] comprising: a first semiconductor [“die 20 resides on top of the die attach pad 12”] element; a first terminal [see Fig. 5 reproduced below, it can be the corner 14 on sides A, B, C] electrically connected to the first semiconductor element; a second terminal [see Fig. 5 reproduced below, it is the mirror image of the first terminal and it too can be the corner 14 on sides A, B, C] electrically connected to the first semiconductor element and spaced apart from the first terminal in a first [see Fig. 5 reproduced below, it is along the side A] direction; and a overmold [“An overmold body 26 is formed over the semiconductor device package 10, covering the die 20, die attach pad 12, wire bonds 22, inside row of contact pads 14 and a portion of the outside row of contact pads 16. As illustrated, a portion of the outside row of contact pads 16 remains exposed. The die attach pad 12, the inside row of contact pads 14, and the outside row of contact pads 16 are held together by the overmold body 26”] covering the first semiconductor element and a part of each of the first terminal and the second terminal, PNG media_image1.png 568 1087 media_image1.png Greyscale wherein the overmold includes a first side surface [see Fig. 5 reproduced above, it is the side face of the resin on side A see Fig. 15] facing in a second direction [i.e perpendicular to side A] orthogonal to the first direction and located closest [see side A is closest to both the corner 14 on sides A, B, C] to the first terminal and the second terminal in the second direction, and the first terminal and the second terminal are spaced apart [see Fig. 5 reproduced above, see that the corner 14 on sides A, B, C are spaced apart from the side face of the resin on side A] from the first side surface but does not state that the overmold is a sealing resin. See Danno Fig. 1, Fig. 2 see “In the semiconductor device, the two semiconductor chips are sealed with a sealing resin” “sealing body (sealing resin layer, sealing resin, sealing resin portion, or sealing body) 7 is made of, e.g., a resin material such as a thermosetting resin and may also contain a filler or the like”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Swan to include that the overmold is a sealing resin. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that resin is known to give excellent results as molding for semiconductor packages. In regard to claim 2 Swan and Danno as combined teaches further comprising a die pad [“die 20 resides on top of the die attach pad 12”] on which the first semiconductor element is mounted, wherein, as viewed in a third direction [vertical] orthogonal to the first direction and the second direction, the die pad includes a first edge [i.e. facing side A] extending in the first direction and located closest [i.e. it is facing side A] to the first side surface in the second direction, and the first terminal and the second terminal are located on opposite sides [see Fig. 5 reproduced above] of the first edge in the first direction. In regard to claim 3 Swan and Danno as combined teaches wherein the first terminal and the second terminal are located opposite to the first side surface with respect to [see Fig. 5 reproduced above this is true, see the corner 14 on sides B, C] the first edge in the second direction. In regard to claim 4 Swan and Danno as combined does not teach wherein, as viewed in the third direction, the first terminal overlaps with a first extension line extending from one end of the first edge in the first direction. However see Danno Fig. 1, Fig. 5, Fig. 6 see that when there are a plurality of different size die, the output terminals in Fig. 1 on left and right overlap the top edge of the die pad “die pad 3”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Swan to include wherein, as viewed in the third direction, the first terminal overlaps with a first extension line extending from one end of the first edge in the first direction. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is to include a plurality of dies in the package to increase the functionality in the package and thus to maximize the output pads by allowing output pads to overlap the extension line of the die pad edge. In regard to claim 5 Swan and Danno as combined teaches wherein, as viewed in the third direction, the second terminal overlaps [see combination claim 4 see that in both Swan and Danno there is symmetrical output pads on left side and right side] with a second extension line extending from another end of the first edge in the first direction. In regard to claim 6 Swan and Danno as combined does not teach wherein a dimension of the die pad in the first direction increases as the die pad extends away from a side on which the first side surface is located with respect to the first semiconductor element in the second direction. However see Danno Fig. 1, Fig. 5, Fig. 6 see that when there are a plurality of different size die, the die pad “die pad 3” is not rectangular, see that bottom part of the die pad is wider. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Swan to include wherein a dimension of the die pad in the first direction increases as the die pad extends away from a side on which the first side surface is located with respect to the first semiconductor element in the second direction. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is to include a plurality of dies in the package to increase the functionality in the package and to shape the die pad to accomododate the different dies in an optimal manner for connectivity. In regard to claim 7 Swan and Danno as combined teaches [see combination claim 6, see Danno Fig. 1, Fig. 5, Fig. 6 see that when there are a plurality of different size die, the die pad “die pad 3” is not rectangular, see that bottom part of the die pad is wider and protrudes to left and righ sides] wherein a portion of the die pad that is located opposite to the first edge with respect to the first semiconductor element in the second direction protrudes toward opposite sides in the first direction with respect to the first edge. In regard to claim 8 Swan and Danno as combined teaches wherein at least a part of the die pad is covered with [see Swan Fig. 5, Fig. 15, see combination “An overmold body 26 is formed over the semiconductor device package 10, covering the die 20, die attach pad 12, wire bonds 22, inside row of contact pads 14 and a portion of the outside row of contact pads 16. As illustrated, a portion of the outside row of contact pads 16 remains exposed. The die attach pad 12, the inside row of contact pads 14, and the outside row of contact pads 16 are held together by the overmold body 26”] the sealing resin, the sealing resin includes a bottom surface [see Swan Fig. 5, Fig. 15] facing away from a side on which the first semiconductor element is located with respect to the die pad, and the first terminal and the second terminal are exposed [see Swan Fig. 5, Fig. 15 see the body 26 extends between 14, 16 and see that 14, 16 are exposed at the bottom] externally from the bottom surface. In regard to claim 12 Swan and Danno as combined does not teach wherein the sealing resin includes a second side surface and a third side surface facing away from each other in the first direction, the first terminal is exposed externally from the second side surface, and the second terminal is exposed externally from the third side surface. However this is because in claim 1 the corner 14 on sides A, B, C were identified as first terminal and second terminal. However see Swan Fig. 5, Fig. 15 see “Wire bonds 22 couple bond pads (not shown) from various devices on the die 20 to contact pads 24 within the inside row of contact pads 14 and the outside row of contact pads 16” however Swan also says “electromagnetic shield 34 reduces electromagnetic interference (EMI), especially when all or certain of the contact pads 24 of the outside row of contact pads 16 are grounded” “All or most of the contact pads 24 of the outside row of contact pads 16 are reserved for connecting to the shield 34 and should not be used for any other purpose” i.e. Swan seems to indicate that some contact pads 16 can be used for other purposes, and see the left and right edges of Fig. 5, Fig. 15 where the 16 are exposed from the sealing resin thus see Fig. 5 reproduced in claim 1, in Fig. 5 on all sides, the sides of contact pads 16 are exposed from the body 26, see that on the sides B, C can be the “a second side surface and a third side surface”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Swan to include wherein the sealing resin includes a second side surface and a third side surface facing away from each other in the first direction, the first terminal is exposed externally from the second side surface, and the second terminal is exposed externally from the third side surface. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that Swan seems to indicate that some contact pads 16 can be used for other purposes (such as ground connection). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Jul 30, 2024
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
77%
With Interview (-8.7%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 894 resolved cases by this examiner. Grant probability derived from career allowance rate.

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