DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 07/30/2024 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-9 and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al. (U.S. 2024/0313705).
Regarding claim 1, LEE et al. (hereinafter, Ref~705) discloses (please see Figs. 1-8 and related text for details) an apparatus (1000 of Fig. 1) comprising:
a first transistor (P-L2 of Fig. 4) having a first terminal and a control terminal (gate);
a second transistor (P-L4 of Fig. 4) having a first terminal and a control terminal (gate), the first terminal (source) of the second transistor coupled to the first terminal (drain) of the first transistor;
a third transistor (N-L2 of Fig. 4) having a first terminal and a control terminal (gate);
a fourth transistor (N-L4 of Fig. 4) having a first terminal and a control terminal (gate), the first terminal of the fourth transistor (source) coupled to the first terminal (drain) of the third transistor;
feedback circuitry (C1/C2 of Fig. 4) coupled to the first transistor, the second transistor, the third transistor and the fourth transistor;
current source circuitry (230/240 of Fig. 4) having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to the feedback circuitry;
slew assist circuitry (400 of Fig. 1) coupled (via ND2/ND4 of Fig. 4) to the first transistor, the second transistor, the third transistor and the fourth transistor, the feedback circuitry and the current source circuitry (please note: direct coupling not required); and
current mirror circuitry (P_L1/P_L3 and N_L1/N_L3 of Fig. 4) coupled to the slew assist circuitry, meeting claim 1.
Regarding claim 8, Ref~705 discloses (please see Figs. 1-8 and related text for details) an apparatus (1000 of Fig. 1) comprising:
a first transistor (P-L3 of Fig. 4) having a first input;
a second transistor (N_L3 of Fig. 4) having a second input;
input transistor circuitry (P_L4/N_L4 of Fig. 4) coupled to the first transistor (P_L3 of Fig. 4) and the second transistor (N_L3 of Fig. 4), the input transistor circuitry having a first output (ND1) and a second output (ND3 of Fig. 4);
slew assist circuitry (400 of Fig. 1) coupled to the first transistor, the second transistor, and the input transistor circuitry, the slew assist circuitry having a first output (ND2 or ND4 of Fig. 4) and a second output (ND4 or ND2 of Fig. 4); and
output stage circuitry (300 of Fig. 1) coupled to the input transistor circuitry and (via current mirrors 210/220 of Fig. 4) slew assist circuitry (400 of Fig. 1), the output stage circuitry having an output (VOUT) wherein a slew rate of a voltage on the output is based on a voltage on the first output (ND2 or ND4 of Fig. 4) of the slew assist circuitry and a voltage on the second output (ND4 or ND2 of Fig. 4) of the slew assist circuitry, meeting claim 8.
Regarding claim 9, Ref~705 discloses the apparatus of claim 8, further comprising current mirror circuitry (210/220 of Fig. 4) coupled to the slew assist circuitry and the output stage circuitry, the current mirror circuitry configured to:
mirror a first current (current at ND2 of Fig. 4) of the first output of the slew assist circuitry;
mirror a second current (current at ND4 of Fig. 4) of the second output of the slew assist circuitry; and
cause (via I_SOURCE and/or I_SINK of Fig. 1) the output stage circuitry to increase the slew rate by supplying the first current and the second current, meeting claim 9.
Regarding claim 12, Ref~705 discloses the apparatus of claim 8, further comprising: current source circuitry (230/240 of Fig. 4) coupled to the slew assist circuitry; and
feedback circuitry (C1/C2 of Fig. 4) coupled to the first transistor, the second transistor, the input transistor circuitry, the slew assist circuitry, and the current source circuitry (please note: direct coupling not required), meeting claim 12.
Regarding 13, Ref~705 discloses the apparatus of claim 12, further comprising current mirror circuitry (210/220 of Fig. 4) coupled to the slew assist circuitry, the output stage circuitry, and the feedback circuitry, meeting claim 13.
Allowable Subject Matter
Claims 2-7, 10-11 and 14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 15-20 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor coupled to the third transistor and the fourth transistor, the control terminal of the fifth transistor coupled to the feedback circuitry, the first transistor, and the second transistor; a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor coupled to the first transistor and the second transistor, the control terminal of the sixth transistor coupled to the feedback circuitry, the third transistor, and the fourth transistor; and current mirror circuitry coupled to the second transistor and the fourth transistor” structurally and functionally interconnected with other limitations in the manner as cited in the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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