DETAILED ACITON
This office action is in response to an Amendment/Request for Reconsideration filed 4/6/2026 for application 18/789,107 filed 7/30/2024.
Claims 1-20 have been amended. No claims have been cancelled. No claims are new. Thus claims 1-20 have been examined.
The IDS sent 1/27/2026 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to a signal per se which is not a process, machine, manufacture, or composition of matter.
Claim 1 recites “a computer-readable storage medium having encoded thereon computer-executable instructions to cause one or more processing units of the system” made in open ended language and thus it is reasonable to interpret to include all possible mediums, including non-statutory mediums such as “transitory computer readable storage medium”. Transitory computer readable storage medium instructions are drawn to a signal. As such, the claim(s) are drawn to a form of energy. Energy is not one of the four categories of invention and therefore the claims are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter. Therefore, the claimed invention is directed to non-statutory subject matter.
The examiner suggests amending the claims to read “a non-transitory computer readable storage medium”.
Claims 2-14 are rejected under 35 U.S.C. 101 because the claims depend from claim 1 that has been rejected to and fail to cure the deficiencies of claim 1.
Allowable Subject Matter
Claims 5-6, 11-12, and 18-19 are object to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims and resolving the 101 rejection.
Regarding claims 5 and 18, the prior art does not teach ‘in response to determining that not all of the set of high-latency memory entries are available, store the second write data in the set of high-latency memory entries.
This limitation requires that a second write request is placed on the memory write input (that is an input to the high-latency memory) the system determines all of the plurality of high-latency memory entries are used, and knowing this, the system forwards the memory write request to the L3 cache (high-latency memory) that does not have space for the entry. This is different than forwarding the data to the larger memory input, discovering after it arrives at the larger memory input that space is not available and processing the request by moving existing cache entries to temporary buffers or evicting cache data to make space from the buffer once it arrives. This is placing the data on an input to the high-latency memory system, and in response to determining all the .. entries in the high-latency memory system are not available... forward the write request to the larger memory system.
Regarding claims 6 and 19, the prior art does not teach ‘in response to determining that all of the set of high-latency memory entries are available, store the second write data in the set of low-latency memory entries’.
This limitation requires sending write entries to the larger memory system in response to determining the second memory system is empty of entries (all of plurality of second memory entries.. are available).
An updated search of the available art filed to identify a teaching, alone or in combination that teaches the claimed limitation.
Regarding claim 11, the prior art does not teach ‘in response to determining that none of the set of low-latency memory entries are available for storing the write data, assert a control signal on the multiplexor control input to cause the multiplexor circuit to forward the previously stored data from the set of high-latency memory entries to the set of low- latency memory entries’.
This limitation requires that data that is to be read into the low-latency memory from the high-latency memory, and the system first determines that the low-latency memory is full and in response to this determination, continue to forward the high-latency memory control signal (i.e. read request, thus trigger sending reading data into the low-latency memory) even though it was determined that the low-latency memory does not have an entry for this request,
An updated search of the available art failed to identify a teaching alone or in combination that teaches the claimed limitation.
Regarding claim 12 the prior art does not teach claim 12 when including the limitations of claim 11 from which claim 12 depends and thus would be allowable for the reasons stated in claim 11 above
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 13-14, 16-17 and 20 are rejected under U.S.C. 103 as being unpatentable over Arimilli (Arimilli et al., US 6,356,980 B1) and further in view of Chang (Chang et al., US 2015/0254014 A1).
Regarding claim 1, Arimilli teaches A system, (Arimilli [Abstract] teaches the inventive concepts are directed to a method and system.) comprising: a set of low-latency memory entries configured to store data; and a set of high-latency memory entries configured to store data, wherein a latency of the set of low-latency memory entries is lower than a latency of the set of high-latency memory entries; (Arimilli column 1 line 67 through column 2 line 2 discloses that in multi-level cache memories typically each higher level is smaller and has a shorter access time. Thus the L1 Cache of Fig. 6 that is the highest level cache of Arimilli is the lowest-latency memory, and the System Memory 46 of Fig. 6 is the highest level memory. See Arimilli column 6 line 44 through column 7; line 55 for a description of the layers. Each cache level is composed of entries, thus a set of entries. The low-latency memory entries may be from any layer that is closer to or the L1 layer, and the high-latency memory may be from any layer further away from the L1 layer than the low-latency layer. Thus the low-latency memory entries may be the L2 cache entries and the high-latency memory entries may be the L3 cache entries.)
a computer-readable storage medium having encoded thereon computer executable instructions to cause one or more processing units of the system to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
receive a memory write request for storing write data; (Arimilli claim 16 and claim 11 from which claim 16 depends discloses a write-through request which is a write request in a cache that may skip a cache level and write between layers that are not adjacent. See also Arimilli col 4 lines 60-61. See also Arimilli col 4 lines 35-40 discloses when a system needs memory in a cache level, which would include the L1 level, the system will generate a castout write and look for a place to put the castout write data such as the L2 layer which is an example of a write-through request that may skip a layer.)
determine whether any of the set of low-latency memory entries are available for data storage of the write data; (Arimilli claim 16 and claim 11 from which claim 16 depends discloses that the system may use a full output signal to determine if an intervening cache is full, where the L2 and L3 cache are examples of intervening caches. See also Arimilli Fig. and col 6 line 37 through col 7 line 32.) in response to determining that none of the set of low-latency memory entries are available for storage of the write data: store the write data in the set of high-latency memory entries; (Arimilli claim 16 and claim 11 from which claim 16 depends discloses an intervening memory may be skipped if the intervening cache is full. Thus the low-latency memory may be the L2 cache and the higher latency cache may be the L3 cache and the system may write the data directly to the L2 cache (the high-latency memory) when the L2 cache is full. See also Arimilli Fig. and col 6 line 37 through col 7 line 32.)
However, Arimilli does not explicitly disclose after storing the write data in the set of high-latency memory entries, forward previously stored data from the set of high-latency memory entries to the set of low-latency memory entries, wherein said forwarding occurs independently of receipt of a memory read request, store the previously stored data in the set of low-latency memory entries; receive the memory read request for accessing the previously stored data from the set of low-latency memory entries; and in response to the memory read request, output the previously stored data stored from the set of low-latency memory entries.
Chang, of a similar field of endeavor, further discloses after storing the write data in the set of high-latency memory entries, forward previously stored data from the set of high-latency memory entries to the set of low-latency memory entries, wherein said forwarding occurs independently of receipt of a memory read request, (Chang [0021] discloses to speed up processing time hot data blocks may be promoted from slower memory levels to higher levels based on their temperature wherein data block temperature may be based on the number of writes only. Chang [0019] teaches that the memory location may be memory levels or tiers. Arimilli column 7 lines 43-50 teaches that the concepts are adaptable to be used in other memory structures including DASD which would include the non-volatile devices of Chang. Thus the solution of Arimilli in view of Chang would promote data to specific cache levels (such as L1, L2, or L3) from slower memory based on the promotion levels of Chang.)
and store the previously stored data in the set of low-latency memory entries; (Chang [0021] discloses to speed up processing time Hot data blocks may be promoted from slower memory levels to higher levels based on their temperature. Thus Arimilli in view of Chang would promote hot data blocks currently in the L3 cache into the L3 cache as their temperature heats up.)
Arimilli and Chang are in a similar field of endeavor as both relate to managing cache for memory devices. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention with the solution of Arimilli and Chang before them to incorporate the promotion of hot data that is based on the number of writes of the data from a lower level/slower memory to an upper level/faster cache as taught by Chang into the solution of Arimilli that maintains a multi-layer cache. Thus combining prior art elements according to known methods to yield predictable results (to make accessing data written faster for data that is written more frequently and identified as hot data.).
Arimilli in view of Chang would further teach receive the memory read request for accessing the previously stored data from the set of low-latency memory entries; and in response to the memory read request, output the previously stored data stored from the set of low-latency memory entries. (Chang teaches promoting data from lower level cache such as the L3 cache of Arimilli into higher level cache such as the L2 cache of Arimilli. Arimilli Fig. 2 and column 3 line 62 through column 5 line 24 teaches the system will being reading from the L1 cache and will read the data from the L2 cache if the L1 cache does not contain the data. Thus the solution of Arimilli in view of Chang would access the previously stored data from the L3 cache that has been promoted to the L2 cache when a read request is received after the promotion, and return that data store in a L2 cache entry to the requesting program.)
The motivation to combine Chang into the existing combination is the same as set forth in claim 16 above.
Regarding claim 2, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above.
further configured to, in response to determining that none of the set of low-latency memory entries are available for storage of the write data: determine whether any of the set of high-latency memory entries are available for storing the write data; (Arimilli claim 16 and claim 11 from which claim 16 depends teaches a full output signal indicating if an intervening cache has available storage. See also Arimilli Fig. 2 and col 3 line 63 through column 5 line 24 [most notable col 4 lines 1-15] that teaches the L2 Cache is an intervening cache between the L1 cache and the L3 cache and the L3 Cache is an intermediate cache between the L2 cache and the System Memory, thus both the L2 and L3 caches would have a full output signal indicating if the respective cache (L2 and L3) has available space. If the L2 cache (low-latency cache) did not have space the system would look to the L3 cache (the high-latency cache) and inspect the L3 cache full output signal to determine if the L3 cache (the high-latency cache has room available for data storage).)
and in response to determining that at least one of the set of high-latency memory entries is available, store the write data in the set of high-latency memory entries. Arimilli suggests the target to write evicted data is the next lower cache level that is not full and the system would simply put the entry in the target cache level (given it is not full and not to be skipped. Thus if evicting data from the L1 Cache identifies the L2 cache is full, the system will send the write request to the L3 cache (the high-latency cache) if the L3 cache is identified as not full.)
Regarding claim 3, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above.
wherein the computer-executable instructions further cause the one or more processing units to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
in response to receiving the memory write request, determine whether at least one of the set of low-latency memory entries is available for storing the write data; (Arimilli col 4 lines 35-40 discloses when a system needs memory in a cache level, which would include the L1 level, the system will generate a castout write and look for a place to put the castout write data such as the L2 layer. Arimilli claim 16 and claim 11 from which claim 16 depends teaches a full output signal indicating if an intervening cache has available storage. See also Arimilli Fig. 2 and col 3 line 63 through column 5 line 24 [most notable col 4 lines 1-15] that teaches the L2 Cache is an intervening cache between the L1 cache and the L3 cache, thus L2 (low-latency memory entries) would have a full output signal indicating if the L2 cache has available space.)
and in response to determining that at least one of the set of low-latency memory entries is available, store the write data in one of the available low-latency memory entries. (Arimilli suggests if evicting data from the L1 cache to a lower cache and the full signal for the L2 cache indicates the system has space, the system would simply place the data evicting from the L1 cache into the L2 cache.)
Regarding claim 4, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above. Arimilli further teaches
wherein the computer-executable instructions further cause the one or more processing units to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
in response to determining that none of the set of low-latency memory entries are available for storage of the write data, determine-whether a high-latency memory entry of the set of high-latency memory entries is available for storing the write data; and in response to determining that the high-latency memory entry is not available, delay storing the write data. (Arimilli claim 16 and claim 11 from which claim 16 depends discloses an intervening memory may be skipped if the intervening cache is full. Thus the low-latency memory may be the L2 cache and the higher latency cache may be the L3 cache and both may be full thus the system may write the data to the next lowest level such as the system memory of Arimilli which is lower and slower, thus will day storing the write data as the write data takes longer to complete, thus delays the storing of the write data.)
Regarding claim 7, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above. Arimilli further teaches wherein the computer-executable instructions further cause the one or more processing units to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
Determine whether at least one of the set of low-latency memory entries is available for storing data; (Chang [0021] discloses that the system determines how full the cache is in order to determine the promotion thresholds. Thus Chang [0021] suggests the system would determines if at least one of the entries in the target cache is available. )
and in response to determining that at least one of the set of low-latency memory entries is available, forward the previously stored data from the set of high-latency memory entries to the set of low-latency memory entries. (Chang [0021] discloses that the system may have a plurality of worthwhile blocks to promote to a higher level cache and thus will select from the plurality of worthwhile blocks the blocks that are the most worthwhile to promote based on a cost benefit analysis. Thus is filling the available cache entries in a low-latency cache with the most worthwhile entries. Thus Chang suggests if one block is available in a higher level target cache it will pick the most worthwhile block to promote and would promote the most worthwhile entry from the L3 cache to the L2 cache of Arimilli.)
Regarding claim 8, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above.
wherein the previously stored data is forwarded from the set of high-latency memory entries to the set of low-latency memory entries in response to the memory read request. (Arimilli Fig. 2 and para column 4 lines 1-15 discloses that a processor ISU 61 may perform a plurality of read requests for data. Arimilli Fig. 4 and paras col 2 lines 1-11 and col4 lines 1-15 and column 5 line 46 through line 64 discloses to satisfy a read request from a ISU (core for data not present in the L1 cache ) a victim is selected at step 22 for the L2 cache entry, the victim data is stored in a temporary location in step 23 which frees up an entry in the L2 cache, and as a result at step 24 the system reads data from lower level cache (L3) into higher level target location (L2), thus the high-latency memory entry will forward the read data stored in response to a lower-latency memory entry being available because the existing data was moved to a temporary buffer.)
Regarding claim 13, the combination of Arimilli and Chang teaches all of the limitations of claim 3 above. Arimilli further teaches further comprising: a first memory tracker configured to track availability of the set of low-latency memory entries and generate an indicator representing availability of at least one low-latency memory entry; (Arimilli claim 16 and claim 11 from which claim 16 depends discloses an intervening memory may be skipped if the intervening cache is full based on a full output where the L2 cache is an intervening cache between the L1 cache and L3 cache and would have a full signal, which would indicate at least one L2 cache entry (low-latency entry) is available if this signal is not set to true.)
and a second memory tracker configured to track availability of the set of high-latency memory entries and generate an indicator representing availability of the set of high-latency memory entries ; (Arimilli claim 16 and claim 11 from which claim 16 depends discloses an intervening memory may be skipped if the intervening cache is full based on a full output where the L3 cache is an intervening cache between the L2 cache and system memory and would have a full signal, which would indicate at least one L3 cache entry (high latency entry) is available if this signal is not set to true.)
wherein the computer-executable instructions further cause the one or more processing units to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.) determine availability of the set of low-latency memory entries and the set of high-latency memory entries based on the respective indicators. (Arimilli claim 16 and claim 11 from which claim 16 depends discloses an intervening memory may be skipped if the intervening cache is full based on a full output where the L2 and L3 cache are intervening caches and each have a respective full signal indicator, which would indicate at least one cache entry is available if this signal is not set to true.)
Regarding claim 14, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above. Arimilli further teaches wherein: the set of low-latency memory entries comprises a random access memory (RAM) including a plurality of RAM storage entries; and the set of high-latency memory entries comprises a larger RAM including a plurality of RAM storage entries. (Arimilli column 1 lines 35-59 teaches that the temporary memory of the solution may be implemented in random access memory (RAM), where the L2, L2, and L3 cache are examples of temporary memory as the final destination for the data is the System Memory 46.)
Regarding claim 16, Arimilli teaches A method of performing data accesses to a memory system (Arimilli [Abstract] discloses the solution may be a method for bypassing caches.) comprising: a(Arimilli, Col 1 line 66 though col 2 line 5 discloses multi-level cache memories typically have levels where each higher level is smaller and has shorter access time, where the cache closest to the processor is the smallest cache. See Arimilli Fig. 2 that shows a L2 Cache 66 that is an example of low-latency memory given it has lower latency than the L3 cache or system memory.) and a set of high-latency memory entries configured to store data, wherein a latency of the set of low-latency memory entries is lower than a latency of the set of high-latency memory entries, (Arimilli, Col 1 line 66 though col 2 line 5 discloses multi-level cache memories typically have levels where each higher level is smaller and has shorter access time and discloses L3 Cache or System 72 that are examples of high-latency memories where the L2 entries latencies are lower than the L3 high-latency memories.)
the method comprising: receiving a memory write request for storing write data; determining whether any of the set of low-latency memory entries are available for storing the write data in response to receiving the memory write request; in response to determining that none of the set of low-latency memory entries are available for storing the write data, storing the write data in the set of high-latency memory entries; (Arimilli col 4 lines 35-40 discloses when a system needs memory in a cache level, which would include the L1 level, the system will generate a castout write and look for a place to put the castout write data such as the L2 layer. Arimilli claim 16 and claim 11 from which claim 16 depends discloses a higher level memory, a lower level memory and an intervening memory that processes a write-through request that causes a cache line to be transferred from the higher level memory to lower level memory, skipping the intervening memory when a full output signal indicates the intervening cache is full. The L2 cache (the low-latency memory entries) is an intervening and if the L2 is full the system sends the data to the L3 cache (the high-latency memory).)
However Arimilli does not explicitly disclose after storing the write data in the set of high-latency memory entries, forwarding previously stored data from the set of high-latency memory entries to the set of low-latency memory entries independently of receipt of a memory read request; storing the previously stored data in one of the set of low-latency memory entries; receiving a memory read request for accessing the previously stored data; and in response to the memory read request, outputting the previously stored data stored in the set of low-latency memory entries.
Chang, of a similar field of endeavor, further discloses after storing the write data in the set of high-latency memory entries, forwarding previously stored data from the set of high-latency memory entries to the set of low-latency memory entries independently of receipt of a memory read request; (Arimilli column 7 lines 43-50 teaches that the concepts are adaptable to be used in other memory structures including DASD which would include the non-volatile devices of Chang. Chang [0021] discloses to speed up processing time hot data blocks may be promoted from slower memory levels to higher levels based on their temperature wherein data block temperature may be based on the number of writes only. Chang [0019] teaches that the memory location may be memory levels or tiers. Thus the solution of Arimilli in view of Chang would promote data to specific cache levels (L1, L2, or L3 based on the promotion levels of Chang.)
storing the previously stored data in one of the set of low-latency memory entries; (Chang [0021] discloses to speed up processing time Hot data blocks may be promoted from slower memory levels to higher levels based on their temperature. Thus Arimilli in view of Chang would promote hot data blocks currently in the L3 cache into the L3 cache as their temperature heats up.)
Arimilli and Chang are in a similar field of endeavor as both relate to managing cache for memory devices. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention with the solution of Arimilli and Chang before them to incorporate the promotion of hot data that is based on the number of writes of the data from a lower level/slower memory to an upper level/faster cache as taught by Chang into the solution of Arimilli that maintains a multi-layer cache. Thus combining prior art elements according to known methods to yield predictable results (to make accessing data written faster for data that is written more frequently and identified as hot data.).
Arimilli in view of Chang would further teach receiving a memory read request for accessing the previously stored data; and in response to the memory read request, outputting the previously stored data stored in the set of low-latency memory entries.
(Chang teaches promoting data from lower level cache such as the L3 cache of Arimilli into higher level cache such as the L2 cache of Arimilli. Arimilli Fig. 2 and column 3 line 62 through column 5 line 24 teaches the system will being reading from the L1 cache and will read the data from the L2 cache if the L1 cache does not contain the data. Thus the solution of Arimilli in view of Chang would access the previously stored data from the L3 cache that has been promoted to the L2 cache when a read request is received after the promotion, and return that data store in a L2 cache entry to the requesting program.)
The motivation to combine Chang into the existing combination is the same as set forth in claim 16 above.
Regarding claim 17, the combination of Arimilli and Chang teaches all of the limitations of claim 16 above.
further comprising, in response to receiving the memory write request comprising the write data: determining whether at least one of the set of low-latency memory entries is available for storing the write data; (Arimilli claim 16 and claim 11 from which claim 16 depends teaches a full output signal indicating if an intervening cache has available storage. See also Arimilli Fig. 2 and col 3 line 63 through column 5 line 24 [most notable col 4 lines 1-15] that teaches the L2 Cache is an intervening cache between the L1 cache and the L3 cache, thus L2 (low-latency memory entries) would have a full output signal indicating if the L2 cache has available space.)
and in response to determining that at least one of the set of low-latency memory entries is available, storing the write data in one of the available low-latency memory entries. (Arimilli claim 16 and claim 11 from which claim 16 depends teaches a full output signal indicating if an intervening cache has available storage. See also Arimilli Fig. 2 and col 3 line 63 through column 5 line 24 [most notable col 4 lines 1-15] that teaches the L2 Cache is an intervening cache between the L1 cache and the L3 cache, thus L2 (low-latency memory entries) would have a full output signal indicating if the L2 cache has available space. Arimilli suggests placing the data being evicted from the L1 cache into the L2 cache if the full signal for the L2 cache indicates the system has space.)
Regarding claim 20, Arimilli teaches A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a one or more processors, cause the one or more processors to access a memory system (Arimilli column 1, lines 36 through 45 teaches one or more processing units …, a permanent memory device (such as a hard disk, or a floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device (such as random access memory or RAM) that is used by the processor(s) in carrying out program instructions.)
The remainder of claim 20 recites limitations described in claim 16 and thus is rejected based on the teaching and rationale of claim 16 above.
Claims 9-10 are rejected under U.S.C. 103 as being unpatentable over Arimilli (Arimilli et al., US 6,356,980 B1) in view of Chang (Chang et al., US 2015/0254014 A1) as detailed in claim 1 above and further in view and further in view of Chlipala (Chlipala et al., US 2010/0191913 A1)
Regarding claim 9, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above. Arimilli further teaches wherein the computer-executable instructions further cause the one or more processing units to; (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
However, the combination does not explicitly teach further comprising a de-multiplexor circuit; comprising: a de-multiplexor input configured to receive the memory write request; a first de-multiplexor output coupled to the set of low-latency memory entries; a second de-multiplexor output coupled to the set of high- latency memory entries; and a de-multiplexor control input; in response to determining that none of the set of low-latency memory entries are available for storing the write data, assert a control signal on the de-multiplexor control input to cause the de-multiplexor circuit to direct the memory write request to the set of high- latency memory entries.
Chlipala, of a similar field of endeavor, further discloses further comprising a de-multiplexor circuit; (Chlipala Fig. 5 and para [0039] discloses de-multiplexor circuity 436B (1-to-many routing))
comprising: a de-multiplexor input configured to receive the memory write request; ; (Chlipala Fig. 5 and para [0039] discloses de-multiplexor 436B coupled to the data arriving from L1B cache in the solution of Armilla in view of Chlipala that writes evicted data from the processor to the L1 cache and then to lower level caches on the output line from the 430B Cache.)
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a first de-multiplexor output coupled to the set of low-latency memory entries; (Chlipala Fig. 5 and para [0039] that discloses Multiplexor 436B connected to L2B-cache (low-latency memory entries).) …
a second de-multiplexor output coupled to the set of high- latency memory entries; (Chlipala Fig. 5 and para [0039] that discloses Multiplexor 446B connected to L2B-cache (low-latency memory entries).) …
and a de-multiplexor control input; (Chlipala Fig. 5 and para [0039] discloses the connections between the L1B cache to the L2 cache or the memory beyond 446B is controlled by the de-multiplexor that controls the input and directs it to the proper output) .
in response to determining that none of the set of low-latency memory entries are available for storing the write data, assert a control signal on the de-multiplexor control input to cause the de-multiplexor circuit to direct the memory write request to the set of high- latency memory entries. (Arimilli teaches (Arimilli claim 16 and claim 11 from which claim 16 depends discloses a higher level memory, a lower level memory and an intervening memory that processes a write-through request that causes a cache line to be transferred from the higher level memory, where the intervening memory includes a full output signal indicating whether said intervening cache has available storage, and the system bypasses the intervening memory when the intervening memory is full and transfers the data to the lower level memory without storing the data in the intervening memory. Chlipala teaches that to bypass the L2 cache (because it is full per Arimilli) a system may use a series of de-multiplexors that route input such as write data that is being evicted from a higher level cache such as a L1 cache through a de-multiplexor and control the output to a L2 cache or to additional external memory such as a L3 cache of Arimilli. Thus the solution of Arimilli in view of Chang and Chlipala that bypasses the L2 cache when the L2 cache is full would assert a control signal for the larger memory on the de-multiplexor control input to cause the de-multiplexor circuit to assert the write request (first memory write request) on the second de-multiplexor output to be forwarded to the higher-latency memory entries (i.e. on the output line from De-multiplexor 436B that bypasses the cache to multiplexor 446B. Examiner notes that per [0044] of Chlipala the system may be embodied in the form of program code embodied in program code loaded and executed by a machine such as the instructions of Arimilli. )
Arimilli, Chang, and Chlipala are in a similar field of endeavor as all relate to managing a cache that may elect to bypass an intermediate cache. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the multiplexor / di-multiplexor hardware components of Chlipala into the solution of Arimilli and Chang, thus combining prior art elements according to known methods to yield predictable results (provide a physical means of providing routing when directing a single input to a multiple output components such as a L2 cache and aL3 cache which is required by Arimilli and which de-multiplexors are designed to do. See Chlipala [0020].)
Regarding claim 10, the combination of Arimilli, Chang, and Chlipala teaches all of the limitations of claim 9 above. Arimilli further teaches wherein the computer-executable instructions further cause the one or more processing units to: (Arimilli column 1 lines 34-42 discloses that the instructions of column 3 line 12 are typically executed on one or more processing units connected to a permanent memory device such as a hard disk for storing the computer’s operating system and user program that would be executed on the processing unit.)
in response to receiving the memory write request, determine whether at least one of the set of low-latency memory entries is available for storing the write data; and in response to determining that at least one of the set of low-latency memory entries is available (Arimilli claim 16 and claim 11 from which claim 16 depends teaches a full output signal indicating if an intervening cache has available storage. See also Arimilli Fig. 2 and col 3 line 63 through column 5 line 24 [most notable col 4 lines 1-15] that teaches the L2 Cache is an intervening cache between the L1 cache and the L3 cache, thus L2 would have a full output signal indicating if the L2 cache has available space and would determine that at least one of the L2 Cache entries (low-latency entries) is available.)
Chlipala further teaches assert a control signal on the de-multiplexor control input to cause the de-multiplexor circuit to direct the memory write request to the set of low-latency memory entries. (Chlipala Fig. 5 and para [0039] discloses de-multiplexor 436B coupled to the data arriving from L1B cache in the solution of Armilla in view of Chlipala that writes evicted data from the processor to the L1 cache and then to lower level caches on the output line from the 430B Cache thus the system of Arimilli., in view of Chang and Chlipala would identify data destined for the L1 cache and then to the L2 cache (the low-latency cache) would assert a control input to cause the de-multiplexor to direct the memory write request to the low-latency L2 entries.)
The motivation to combine Chlipala is the same as those presented in claim 9 above.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Arimilli (Arimilli et al., US 6,356,980 B1) in view of Chang (Chang et al., US 2015/0254014 A1) as detailed in claim 1 above and further in view of Lilly (Lilly et al., US 2015/0026404 A1) and Toshiba (an screen shot of an article that details the architecture of a shift register attached to this office action and available online at https://web.archive.org/web/20230327015627/https://toshiba.semicon-storage.com/us/semiconductor/knowledge/e-learning/cmos-logic-basics/chap3/chap3-3-4.html)
Regarding claim 15, the combination of Arimilli and Chang teaches all of the limitations of claim 1 above. However, the combination does not explicitly teach wherein: the set of low-latency memory entries comprises a plurality of flip-flops serially coupled to each other; and the set of high-latency memory entries comprises a plurality of flip-flops serially coupled to each other.
Lilly in view of Toshiba, both of a similar field of endeavor, further discloses wherein: the set of low-latency memory entries comprises a plurality of flip-flops serially coupled to each other; and the set of high-latency memory entries comprises a plurality of flip-flops serially coupled to each other. (Lilly Fig. 3 and paras [0031]-[0034], most notably [0034] discloses that one means of detecting least recently used cache entry is to use a linear feedback shift register in a cache controller that manages a cache. Thus the Solution of Arimilli that evicts data from the caches such as the L2 cache and L3 cache using the least recently used algorithm may implement the algorithm using a shift register. Toshiba page 1 lines 10 – 19 further discloses that shift registers are made up of multiple cascading flipflops where the output of one flip flop is the input to another flip flop, thus a shift register is made up of flip flops serially coupled to each other.)
Arimilli, Chang, and Lilly are in a similar field of endeavor as all relate to managing cache that evicts data. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the use of a shift register to compute the LRU cache element as taught by Lilly into the solution of Arimilli and Chang that evicts data according to the LRU algorithm. Thus combining prior art elements according to known methods to yield predictable results (to implement the LRU using simple to synthesize, using few resources, that can be run at very high clock rates.)
Arimilli, Chang, Lilli, and Toshiba are in a similar field of endeavor as all relate to components associated with the cache memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the description of a sequential logic as detailed by Toshiba into the solution of Arimilli, Chang, and Lilli that implements LRU using a shift register, thus combining prior art elements according to known methods to yield predictable results (implanting a shift register according to commonly used techniques used by companies such as Toshiba Electronics Devices & storage Corporation).
Response to Remarks
Examiner thanks Applicant for their claim amendments and remarks of 4/6/2026. They have been fully considered. Applicants argument that Arimilli does not teach the claim as amended 4/6/2026 is persuasive. Therefore the rejection has been withdrawn. However, upon further consideration and in response to the claims as amended, a new ground(s) of rejection is made in view of Chang (Chang et al., US 2015/0254014 A1) as detailed above.
Applicant further argues on pages 21-22 of their remark ‘By contrast, the quoted limitation of Claim 2 requires that the system "determine whether any of the set of high-latency memory entries are available for storing the write data" after determining that none of the low-latency memory entries are available. Thus, Claim 2 requires an explicit determination regarding the availability of entries within the high-latency memory tier before performing the write operation. The portions of Arimilli cited by the Office Action do not disclose such functionality. Arimilli describes a cache hierarchy in which write data or evicted cache lines are propagated to lower cache levels according to predetermined cache hierarchy rules. In such systems, the destination of the data is determined by the hierarchy itself rather than by the explicit determination required by Claim 2 regarding whether entries in a high-latency memory tier are available for storing newly received write data. The portions of Arimilli cited by the Office Action do not disclose such functionality. Arimilli describes a cache hierarchy in which write data or evicted cache lines are propagated to lower cache levels according to predetermined cache hierarchy rules. In such systems, the destination of the data is determined by the hierarchy itself rather than by the explicit determination required by Claim 2 regarding whether entries in a high-latency memory tier are available for storing newly received write data.’
Examiner respectfully disagrees. The Examiner citation includes claims 1 and 16 of Arimilli as well as additional citations with Arimilli such as Arimilli Col 1 line 66 through col 2 line 5. Arimilli [Abstract] puts these claims in context and notes the inventive concepts are directed to “A method and system for bypassing cache levels when storing data castout from an upper level cache provides a memory hierarchy that can selectively skip one more intermediate levels when writing castout entries from a higher level cache based on a number of detected conditions” Claim 16 states “wherein said intervening memory includes a full output indicating whether said intervening cache has available storage, .. said writeback of said cache line from said higher level memory to said lower level memory bypassing said intervening memory is performed when said intervening memory is full. Thus Arimilli teaches examining a full output signal at an intervening memory level (such as L2 or L3 caches), and if the signal indicates it is evicting (casting out) a cache line from an upper level cache such as the L1 cache to a lower level (such as the L2, L3, or System memory) it will first review the full signal to determine if the intermediate cache is full (i.e. when it is full it does not have any entries available for storing the write data) and after determining if it is full, and concluding it is full, it will write the data to a lower level of cache, skipping an intermediate cache layer. For example when evicting data from a L1 cache, and upon determining the L2 cache is full, it will evict the data into the L3 cache if the L3 cache is not full.
Applicant further argues on pages 22-23 of their remarks ‘Arimilli describes a cache hierarchy in which write data or evicted cache lines are propagated to lower cache levels according to predetermined cache hierarchy rules. In such systems, the destination of the data is determined by the hierarchy itself rather than by the explicit determination required by Claim 2 regarding whether entries in a high-latency memory tier are available for storing newly received write data’.
Examiner respectfully disagrees. As detailed above, Arimilli discloses an explicit determination of whether entries in a high-latency memory tier (such as the L2 cache are available for storing newly received data from a write-through request, and the availability of storage space is a key hierarchy rule that determines where to write castout data.
Applicant further argues on page 23 of their remarks ‘The Office Action's reliance on signals indicating whether an intervening cache is full therefore does not disclose the claimed determination regarding the availability of high-latency memory entries. Those signals merely indicate whether a cache level should be bypassed during propagation of data through the cache hierarchy and do not correspond to the claimed determination.
Examiner respectfully disagrees. First, examiner notes that the signal indicating a cache is full is also a signal that indicates the cache level has no available space. Furthermore, the instant application does not contain an explicit definition of high-latency memory entries. The claims recite high-latency memory entries and low-latency memory entries wherein a latency of the set of low-latency memory entries is lower that a latency of the set of high-latency memory entries. Arimilli column 1 line 66 though column 2 line 1 discloses multi-level cache memories typically support a tier structure such that higher each higher level is smaller (in size) and has shorter access time (i.e. shorter latency) than an cache at a lower level. Thus in Fig. 6 of Arimilli detailed in column 6 line 44 through column 7, the L1 cache has the shortest latency (is the highest-latency cache), the L2 cache is slower than the L1 cache, the L3 cache is slower than the L2 cache and the System Memory 46 is slower than the L3 cache. Thus the L1 cache, L2 cache and L3 cache are examples of high-latency memory entries when compared against the L2, L3, and system memory entries respectively. The signal of Arimilli is directed to intermediate caches, thus to the L2 and L3 cache levels and teaches the claimed determination. Therefore Examiner disagrees with applicants conclusion that the portions of the reference cited fails to teach or suggest “determine whether any of the set of high-latency memory entries are available for storing the write data; and in response to determining that at least one of the set of high-latency memory entries is available, store the write data in the set of high-latency memory entries." Thus Arimilli will use the full signal to determine if data that is a write castout that is not placed in the L2 cache should be place in the L3 cache or not (the high-latency memory), based on the fullness signal for the L3 cache.
Applicant further argues on page 24 of their remarks ‘The quoted limitation recites a specific write-handling policy that occurs in response to receiving a memory write request. In particular, the system first determines whether at least one entry in the low-latency memory tier is available for storing the write data and then stores the write data in that low-latency memory tier when such availability exists. Thus, the quoted limitation requires a decision process that explicitly evaluates the availability of low-latency memory entries for storing newly received write data. The portions of Arimilli cited by the Office Action do not disclose such functionality. The portions of Arimilli cited by the Office Action do not disclose such functionality. Instead, Arimilli describes a conventional hierarchical cache architecture in which cache lines are propagated through the cache hierarchy according to cache hierarchy rules and eviction policies. In those systems, the destination of the write operation is determined by the structure of the cache hierarchy itself, such as writing evicted data from an L1 cache to an L2 cache or propagating write- through data to a lower cache level.
Examiner respectfully disagrees. As detailed above, Arimilli teaches a decision process that evaluations the availability of an entry in an intervening memory such as the L2 cache that is a low-latency memory as compared to the L3 memory, and will write the data into the lower latency memory such as the L2 memory if the full signal indicates there is room for the entry.
Applicant further argues on pages 24-25 of their remarks ‘The Office Action's reliance on the eviction of data from an L1 cache to an L2 cache does not correspond to the quoted limitation. Eviction mechanisms in Arimilli involve the movement of previously stored cache lines when a cache line must be replaced, rather than determining whether a low-latency memory entry should receive newly written data in response to a memory write request. In other words, Arimilli's eviction policies manage existing cache lines within the cache hierarchy, whereas the quoted limitation requires a determination regarding whether newly received write data should be placed into a low-latency memory entry.
Examiner respectfully disagrees. Applicant is arguing a limitation not cited in the claim. The claim does not recite the limitation that the data may not be previously written. Arimilli teaches propagating a castout write request from a L1 cache to potentially a L2 level cache, a L3 level cache, or system Memory. See Arimilli column 4 lines 36-40 that discloses the eviction process generates a write request prior to filling the castout’s prior location with the read value. Thus the castout write from the L1 cache may be the claimed “write request for storing write data” which was generated by the caching system in response to detecting a need to create space in the L1 cache.
Applicant further argues on page 24 of their remarks ‘Similarly, the Examiner's reliance on signals indicating whether a cache level is full does not disclose the quoted limitation. Those signals merely indicate whether a cache level should be bypassed when propagating data through the cache hierarchy. They do not teach or suggest the claimed determination that evaluates whether a low-latency memory entries are available for storing write data in response to a memory write request.
Examiner respectfully disagrees. First, examiner notes that the signal indicating a cache is full is also a signal that indicates the cache level has no available space. Furthermore, the instant application does not contain an explicit definition of low-latency memory entries. The claims recite high-latency memory entries and low-latency memory entries wherein a latency of the set of low-latency memory entries is lower that a latency of the set of high-latency memory entries. Arimilli column 1 line 66 though column 2 line 1 discloses multi-level cache memories typically support a tier structure such that higher each higher level is smaller (in size) and has shorter access time (i.e. shorter latency) than an cache at a lower level. Thus in Fig. 6 of Arimilli detailed in column 6 line 44 through column 7, the L1 cache has the shortest latency (is the highest-latency cache), the L2 cache is slower than the L1 cache, the L3 cache is slower than the L2 cache and the System Memory 46 is slower than the L3 cache. Thus the L1 cache, L2 cache and L3 cache are examples of high-latency memory entries when compared against the L2, L3, and system memory entries respectively. The signal of Arimilli is directed to intermediate caches, thus to the L2 and L3 cache levels and teaches the claimed determination if there is space available within those intermediate caches. Therefore Examiner disagrees with applicants conclusion that the portions of the reference cited fails to teach or suggest the limitations as the eviction of data from the L1 cache will consider the available space in the L2 cache (the low-latency cache) when evicting the data to a lower level cache.
Applicant further argues on page 25 of their remarks “Thus, Arimilli does not teach or suggest the specific write-handling policy required by the quoted limitation. Because the cited disclosure concerns eviction and propagation of cache lines within a hierarchical cache structure rather than placement of newly received write data in response to a memory write request, the Examiner's mapping does not disclose the claimed functionality.”
Examiner respectfully notes that applicant is arguing a limitation not claimed. The claim recites “a write request for storing write data”. It does not claim “newly received write data” and does not claim that the data was not previously written at any time as suggested earlier in applicants arguments. Arimilli executes a write requests generated in response to a need for space within an upper level cache such as a L1 cache and this write request is an example of a “memory write request for storing write data” within a system. See Arimilli column 4 lines 35-40 “by issuing a write request for the castout, prior to filling the castout’s prior location with the read value”.
Applicant further argues on page 25 of their remarks “Accordingly, Arimilli fails to disclose or suggest at least the following limitations of Claim 3: "in response to receiving the memory write request, determine whether at least one of the set of low-latency memory entries is available for storing the write data; and in response to determining that at least one of the set of low-latency memory entries is available, store the write data in one of the available low-latency memory entries." Because the cited reference does not disclose these limitations, Claim 3 is independently patentable for reasons beyond those discussed above with respect to Claim 1.”
Examiner respectfully disagrees. For the reasons cited above, Examiner disagrees with applicant and the cited references discloses the limitations of claim 3 above.
Applicants arguments with respect to dependent claims 2-3, 7-8, 13-14, 16-71, and 20 all rely upon perceived errors in claim 1 and thus have been addressed in the rejection and response to claim 1 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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