Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 07/30/2024. Claims 1-20 are pending on this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Partil et al. U.S. patent No. 11,218,158 in view of Ali et al. Pub. No. 2020/0280320.
Fig. 5 Partil et al. discloses a pipelined bit trails ADC 500 having digital reconstruction 126 with digital estimation of transfer function H(z) 212.
Fig. 6 of Partil et al. discloses digital estimation of transfer function H(z) in Fig. 5
Regarding claim 1. Fig. 5 of Partil et al. discloses an analog-to-digital converter (500; Col. Line 13) comprising: bit trial circuitry (bit trails circuitry of 500) configured to perform ADC bit trials (output bit trails of ADC 104, ADC 122) that compare (110) an input signal (112) to states (Xq 114) of weighted circuit elements (weighted elements of DAC 106); a dither digital-to-analog converter (PRBS DAC 302; Col. 24 lines 18-19 discloses “test signal is a pseudo-random bit sequence or a dither signal”) to receive a dither sequence (-prbs[n]) and apply a dither signal (dithered output signal 304) to the bit trial circuitry (bit trails circuitry of 500); and calibration circuitry (Digital Reconstruction 126) configured to: input a dither sequence (prbs[n]) into the ADC bit trials (output bit trails of ADC 104, ADC 122; also see Fig. 6) as dithered bit trials (dithered bits trails of 308); determine an effect (see Fig. 6 for discloses the determination an effect of dither prbs[n])) of the dither sequence (prbs[n]) on results of the dithered bit trials (dithered bit trail 308 and 124).
However, Partil et al. do not discloses update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.
Fig. 15 of Ali et al. discloses an analog-to-digital converter (1304; paragraph 0150) comprising calibration circuitry (1310) configured to input a dither signal (Dither) into the ADC (Fig. 15) as dithered bit trials (bits trails of ADC 1304 by Dither); determine an effect (1508, 1310) of the dither (Dither) on results of the dithered bit trials (dither bit trails of ADC 104) ; and update (1310; paragraph 1151 discloses “calibration updates, the calibration circuitry 1310”) correction factors (1314) used to adjust (1316) results of the ADC bit trials ( dither bit trails of ADC 104) using the determined effect (1508, 1310) of the dither (Dither).
Partil et al. and Ali et al. are common subject matter of dither for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art the which the claimed invention pertains to incorporate Ali et al. into Partil et al. for the purpose of providing a corrected output for subsequent error estimation and calibration updates, the calibration circuitry can enable the calibration to converge towards a value for the estimate of the component of the circuit that can best reduce the error (paragraph 0151 of Ali et al.).
Regarding claim 10. Fig. 5 of Partil et al. disclose a method of calibration (Digital Reconstruction 126) of an analog-to-digital converter (ADC 104, ADC 122), the method comprising: performing ADC bit trials (bit trails of ADC 104, ADC 122) for an analog-to-digital (ADC 104, ADC 122) conversion of an input signal (102) , wherein an ADC bit trial (bit trails of ADC 104, ADC 122) includes comparing (110) the input signal (102) to a state (stage of Xq 114) of a weighted circuit element (weighted of circuit element DAC); inputting a dither sequence (prsb [n]) into the ADC bit trials (bit trails of ADC 104, ADC 122) as dithered bit trials (dithered bit trails of 308 and 124) ; determining an effect of the dither sequence (see Fig. 6 for discloses the determination an effect of dither prbs[n]) on results of the dithered bit trials (308 and 124).
However, Partil et al. do not discloses update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.
Fig. 15 of Ali et al. discloses an analog-to-digital converter (1304; paragraph 0150) comprising calibration circuitry (1310) configured to input a dither signal (Dither) into the ADC (Fig. 15) as dithered bit trials (bits trails of ADC 1304 by Dither); determine an effect (1508, 1310) of the dither (Dither) on results of the dithered bit trials (dither bit trails of ADC 104) ; and update (1310; paragraph 1151 discloses “calibration updates, the calibration circuitry 1310”) correction factors (1314) used to adjust (1316) results of the ADC bit trials ( dither bit trails of ADC 104) using the determined effect (1508, 1310) of the dither (Dither).
Partil et al. and Ali et al. are common subject matter of dither for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art the which the claimed invention pertains to incorporate Ali et al. into Partil et al. for the purpose of providing a corrected output for subsequent error estimation and calibration updates, the calibration circuitry can enable the calibration to converge towards a value for the estimate of the component of the circuit that can best reduce the error (paragraph 0151 of Ali et al.).
5. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Partil et a. and Ali et al. applied to claim 1 above in further view of Bodnar et al. U.S. patent No. 10,505,561.
Partil et al. and Ali et al. applied to claim 1 above, Fig. 5 of Partil et al. further discloses wherein the ADC (500) is a multi-bit ADC (bits output of ADC 104 and ADC 122), and the calibration circuitry (calibration circuitry of Bodnar as applied to claim 1 above) is configured to perform the dithered bit trials and calibrate the correction factors for the ADC (dither bit trails and calibration updates 1310 correction factors 1314 of Bodnar as applied to claim 1 above).
However, Paril et al. and Ali et al. do not disclose the multi-bit ADC is a multi-bit SAR ADC as claimed.
Fig. 10 and Fig. 11 of Bodnar et al. discloses a multi- bit trails SAR ADC (200) with dither 400 wherein the multi-bit ADC (Fig. 10 or Fig. 11) is a multi-bit SAR ADC (200) as claimed.
Partil et al./Ali et al. and Bodnar et al. are common subject matter of dither for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art the which the claimed invention pertains to incorporate Bodnar et al. into Partil et al./Ali et al. for the purpose of providing the analog to digital converter of the stage may include an ADC operated in accordance with a suitable conversion strategy, such as (but not limited to) a successive approximation register (SAR) conversion scheme (as suggested by Bodnar et al. on Col. 2 lines 24-lines 27).
6. Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Partil et a. land Ali et al. applied to claims 1 and 10 above, respectively, in further view of Ali et al. Pub. No. 2019/0131992.
Partil et al. and Ali et al. applied to claims 1 and 10 above, respectively, do not disclose wherein the calibration circuitry is configured to perform the dithered bit trial parallel to the ADC bit trials.
Fig. 19 of Ali et al. Pub. No. 2019/013992 discloses a bit trails ADC (D1…Dn) comprising a calibration circuitry (1800) is configured to perform the dithered bit trial (Dithers of 1800) parallel to the ADC bit trials (D1…Dn).
Partil et al./Ali et al. and Ali et al. Pub. No. 2019/013992 are common subject matter of dither for bit trails ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art the which the claimed invention pertains to incorporate Ali et al. (Pub. No. 2019/013992) into Partil et al./Ali et al. for the purpose of providing desirable to background calibrate the non-linearities caused by the DAC and reference buffer (paragraph 0035 of Ali et al. Pub. No. 2019/013992).
Allowable Subject Matter
7. Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the calibration circuitry is configured to: compute a midpoint for the dithered bit trials; compare results of the dithered bit trials to the midpoint to measure instantaneous errors in the dithered bit trials; and recurrently initiate dithered bit trials to determine the updated correction factors based on the measured instantaneous errors.
8. Claims 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the determining the effect of the dither sequence includes: determining a midpoint for the dithered bit trials; measuring instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence; and determining updated correction factors based on the measured instantaneous errors in the dithered bit trials.
9. Claims 18-20 are allowed.
With respect to claim 18, in addition to other elements in the claim, prior arts considered individual or combination does/do not teach: determining a midpoint for the dithered bit trials; determining instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence; determining an error in the ADC bit trials using a determined convergence of the instantaneous errors in the dithered bit trials.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/30/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights