Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Amendment dated 3/6/2026.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-5, 7-10, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sebastian Artur Ciesluk (“Ciesluk”), U.S. Patent Publication No. 2023/0178979 and Fayao Zheng (“Zheng”), U.S. Patent Publication No. 2022/0294431.
Regarding Claims 1 and 10, Ciesluk teaches an apparatus [Fig-5], comprising:
voltage sensing circuitry (voltage sensor 512) configured to:
detect a voltage associated with a system-on-chip (SoC) [Para: 0048(“voltage transient sensor 512 senses transients of the voltage supply 320 near a power supply input to the SOC or within the SOC”)]; and
determine when the voltage transitions from a first voltage to a second voltage [Para: 0050(as “voltage drops (voltage transients) caused by rapid increases in the processing power of the SOC” suggests a change in voltage from a first voltage to second voltage)]; and
management circuitry (power control processing entity 514) configured to:
generate clocking signals for the SoC [Para: 0048(power control processing entity 514 adjusts the power consumed by the SOC 510 … a clock speed adjustment 518)]; and
alter a frequency of the generated clocking signals in response to the detected voltage transition [Para: 0048(“power control processing entity 514 adjusts … clock speed adjustment 518”) and 0050(“monitored voltage can be used to scale a frequency of a software clock, or to adjust the processing of the SOC”)].
Ciesluk does not disclose expressly altering frequency from a first frequency that corresponds to the first voltage to a second frequency that corresponds to the second voltage.
In the same field of endeavor (e.g., system of power control via adaptive voltage and frequency adjustment circuit ), Zheng teaches a SoC has an adaptive adjustment circuit configure to control clocking signals from a first frequency that corresponds to a first voltage to a second frequency that corresponds to a second voltage in response to voltage transition [Para: 0035 (“an adaptive adjustment circuit which can adaptively adjust the operating frequency and operating voltage of the chip … when the working voltage of the chip changes, the adaptive adjustment circuit can adaptively adjust the working frequency”) and 0049(when a current frequency corresponds a voltage transition to a target frequency “F” which corresponds to a new voltage “V2” by VCO, see 0051, 0054)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ciesluk’s teachings of the management circuitry configured to generate clocking signals for the SoC and alter a frequency of the generated clocking signals in response to the detected voltage transition with Zheng’s teachings of altering frequency from a first frequency that corresponds to the first voltage to a second frequency that corresponds to the second voltage to allow Ciesluk to “adaptively adjust the working frequency and the working voltage of the chip, so as to maintain the performance of the chip and reduce unnecessary power consumption as much as possible” [Zheng, Para: 0087].
Regarding Claim 2, Ciesluk teaches wherein the management circuitry is configured to alter the frequency of the clocking signals by decreasing the frequency of the clocking signals when the first voltage is greater than the second voltage [Para: 0030(where “scale means of varying frequency … lower processing power … slowing down the frequency” or decreasing the frequency)].
Regarding Claim 3, Ciesluk teaches wherein the management circuitry is further configured to alter the frequency of the clocking signals by increasing the frequency of the clocking signals when the first voltage is less than the second voltage [Para: 0004 (“power control processing … adjust a power load of the SOC based on the sensed voltage” where adjusting includes scaling frequency, (see para 0050) where scaling involve increasing frequency according to voltage or when second voltage greater than first voltage)].
Regarding Claims 4 and 14, Ciesluk teaches wherein the management circuitry is further configured to alter the frequency of the clocking signals during a voltage under/overshoot [Para: 0050(clock scaling due to a voltage drop where voltage drop is “detection of the voltage waveform of (V.sub.out) dropping below each of the multiple levels of critical voltages” see para 0047)].
Regarding Claims 5 and 13, Ciesluk teaches wherein the management circuitry is configured to lock the frequency of the clocking signals to the detected voltage [Para: 0050(as “monitored voltage can be used to scale a frequency” or lock the frequency to it’s current voltage)].
Zheng teaches detected voltage such that an increase in the detected voltage results in an increase in the frequency of the clocking signals and a decrease in the detected voltage results in a decrease in the frequency of the clocking signals [Para: 0043].
Regarding Claim 7, Ciesluk teaches wherein the management circuitry is further configured to apply a power mode transition [Para: 0050(“voltage drops (voltage transient) caused by rapid increases in the processing power” or begin a transition of high power mode)] termination during a power mode transition [Para: 0067(sensing of voltage transients can be used to identify what processing is causing the voltage transients … stopping of different operations of the multiple processing” or stopping the transition)].
Regarding Claim 8, Ciesluk teaches wherein the management circuitry comprises throttling circuitry [Para: 0048(“power control processing entity 514 adjusts the power … a clock speed adjustment 518 (also referred to as frequency scaling) of the SOC processing 516”)], clock division circuitry, or a voltage-controlled oscillator, or any combination thereof.
Regarding Claim 9, Ciesluk teaches wherein the voltage sensing circuitry comprises an analog comparator [Para: 0048(“voltage transient sensor 512 … is operative to sense voltage transients on the power supply at greater than a predetermined speed or rate”)], an oscillator circuit, a phase detection circuit, or an analog-to-digital converter, or any combination thereof.
Regarding Claim 15, Ciesluk teaches generating, by the management circuitry, the clock signals in the absence of a speed up pre-requisite that includes increasing the voltage to a target voltage prior to generating the clocking signals [Para: 0050(as scaling frequency based on sensed voltage)].
Regarding Claim 16, Since it is directly related to Claim 1 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claim 1 applies equally as well to Claim 16 and Ciesluk furthermore teaches a system, comprising: a plurality of computing components coupled to a system-on-chip (SoC), wherein the SoC comprises: a voltage regulator [Fig-3(320)];
a voltage sensing circuit (voltage sensor 307) configured to: determine a voltage received from the voltage regulator [Para: 0031 and Fig-3].
Zheng teaches a first frequency that corresponds to a first voltage to a second frequency that corresponds to a second voltage of a voltage transition as set forth above.
Regarding Claim 17, Ciesluk teaches wherein a portion of the plurality of computing components are external to the SoC [Fig-3].
Regarding Claim 18 and 19, Claims reciting variations of power control and various aspects of voltage regulator, a sensing circuit and transition of the SoC from normal mode to retention mode or vice versa. One of ordinary skill in the art would utilize Ciesluk and Zhen’s teaching to achieve these variations such as a secondary voltage regulator coupled to the voltage sensing circuit wherein the voltage regulator, the secondary voltage regulator are coupled to the voltage sensing circuit by a switch and wherein the voltage sensing circuit is configured to determine the voltage transition corresponds to a power mode transition of the SoC, wherein the power mode transition is a transition from a nominal voltage to a retention voltage or a change from a retention voltage to a nominal voltage for the purpose of achieving target result based on user requirement.
Regarding Claim 20, Ciesluk teaches wherein the one or more components of the SoC are resident on the SoC and comprise one or more logic blocks [Fig-6].
4. Claim(s) 6 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ciesluk and Zheng (hereinafter, “Ciesluk-Zheng”) as applied above and further in view of Rangarajan et al. (“Rangarajan”), U.S. Patent Publication No. 2020/0133862.
Regarding Claim 6, Ciesluk-Zheng teaches wherein the management circuitry is further configured to alter the frequency of the generated clocking signals in an absence of clock management timing to force the clocking signals to stop [Ciesluk, Para: 0067(sensing of voltage transients can be used to identify what processing is causing the voltage transients … stopping of different operations of the multiple processing” or stop providing clocks)].
Ciesluk-Zheng does not disclose expressly a retention mode; and
alter frequency during a retention mode and restart the clocking signals when the retention mode is transitioned to a nominal mode.
In the same field of endeavor (e.g., power control in various modes for a system), Rangarajan teaches system having system having a retention mode and a nominal mode [Para: 0003]; and
alter frequency during a retention mode and restart the clocking signals when the retention mode is transitioned to a nominal mode [Para: 0025(“different active power mode (e.g., nominal mode … where the computing cores cluster run at a different frequencies” suggests that cores run on different frequencies in different modes)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ciesluk-Zheng’s teachings of the management circuitry is further configured to alter the frequency of the generated clocking signals in an absence of clock management timing to force the clocking signals to stop with Rangarajan’s teachings of a retention mode and alter frequency during a retention mode and restart the clocking signals when the retention mode is transitioned to a nominal mode for the purpose of dynamically controlling power in order to save power.
Regarding Claim 11, since it is directly related to Claims 2 and 6 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claims 2 and 6 applies equally as well to Claim 11.
Regarding Claim 12, since it is directly related to Claims 3 and 6 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claims 3 and 6 applies equally as well to Claim 12.
Response to Arguments
5. Applicant’s arguments with respect to claim(s) 1, 10 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
