DETAILED ACTION
Claims 1-20 are examined and pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 9, 14-16 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Fairhurst et al. (U.S. 20190334828 A1, hereinafter “Fairhurst”).
As to claims 1, 9 and 15 , Fairhurst discloses an apparatus comprising:
one or more ingress points configured to receive one or more packets, each packet comprising a respective one or more cells (Figure 4, discloses ingress data buffer that receives packets that can be divided into cells); a traffic manager configured to obtain the one or more packets from a buffer, wherein the traffic manager (Figure 4) comprises:
a first storage configured to store one or more pointers associated with a packet of the one or more packets, the one or more pointers comprising a first type of pointer and a second type of pointer (para. [0176] and [0178]; discloses packets arrive into an input traffic manager packet data is immediately stored in the main packet buffer (ITM payload buffer. Packet control information is held in a cell receive block which determines the data cell pointer associated to the path that the packet data takes them either the CT path or SAF path);
a second storage configured to store the respective cell control information of at least part of the one or more cells of the packet (para. [0176]; discloses packet control information is held in a cell receive block ), wherein the cell control information includes a respective first type of pointer for each of the at least part of the one or more cells (para. [0178]; discloses RL passes the cell pointers to the main payload buffer to be read and forwarded to the Egress buffer), wherein the first type of pointer references an address of a location in the buffer where a respective cell of the at least part of the one or more cells is stored (para. [0176]-[0178]; discloses the packet data (in cells) uses data cell pointers that point to location in the main packet buffer that are used by the buffer to be read), wherein the second type of pointer references an address of a location of the cell storage (para. [0176]; discloses packet control information is held in a cell receive block and references the location of the packets);
admission control logic configured to perform an admission check of the one or more packets without the cell control information of the one or more packets, wherein performing the admission check includes determining whether a packet in the buffer should be admitted into a first queue (para. [0030]; discloses the traffic manager has an admission control module that determines whether a packet can be admitted into the packet buffer and queuing involves packets are admitted into the packet buffer are linked together into output queues).
As to claim 2, Fairhurst discloses the apparatus of claim 1, wherein the traffic manager is further configured to group the one or more packets into one or more blocks of packets, the one or more blocks of packets including a first block of one or more first packets and a second block of one or more second packets. (para. [0087]; discloses each cell or packet is assigned an entry in a queue block to hold the packets control state).
As to claim 7, Fairhurst discloses the apparatus of claim 1, wherein the first storage includes a first control queue having a first number of entries (para. [0040]; discloses each ingress buffer is configured to support a single input cell and single output cell), and the second storage includes a second control queue having a second number of entries (para. [0040]; discloses egress buffer is configured to support a single input cell and single output cell), wherein the second number of entries is equal to a total number of cells of the one or more cells of the packet (para. [0041]; discloses each input port or each output port may have access to only a fraction of the total payload memory because the buffer is divided into several smaller portions, where each portion handles a single packet per cycle. As such, the buffering bandwidth-delay product (e.g., the amount of buffering available to any one output port) can be severely limited. Dividing the buffer into smaller portions also means that the control logic that performs admission control and queueing should be replicated at each ingress and egress buffer).
As to claim 9, Fairhurst discloses the network device of claim 8, wherein the traffic manager is further configured to group the one or more packets into one or more blocks of packets, the one or more blocks of packets including a first block of one or more first packets and a second block of one or more second packets (para. [0087]; discloses each cell or packet is assigned an entry in a queue block to hold the packets control state).
As to claim 14, Fairhurst discloses the network device of claim 8, wherein the first storage includes a first control queue having a first number of entries (para. [0040]; discloses each ingress buffer is configured to support a single input cell and single output cell), and the second storage includes a second control queue having a second number of entries (para. [0040]; discloses egress buffer is configured to support a single input cell and single output cell), wherein the second number of entries is equal to a total number of cells of the one or more cells of the packet (para. [0041]; discloses each input port or each output port may have access to only a fraction of the total payload memory because the buffer is divided into several smaller portions, where each portion handles a single packet per cycle. As such, the buffering bandwidth-delay product (e.g., the amount of buffering available to any one output port) can be severely limited. Dividing the buffer into smaller portions also means that the control logic that performs admission control and queueing should be replicated at each ingress and egress buffer).
As to claim 16, Fairhurst discloses the memory management unit of claim 15, wherein the traffic manager is further configured to group the one or more packets into one or more blocks of packets, the one or more blocks of packets including a first block of one or more first packets and a second block of one or more second packets (para. [0087]; discloses each cell or packet is assigned an entry in a queue block to hold the packets control state).
Allowable Subject Matter
Claims 3-6, 10-13, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wynne et al. (U.S. 2003/0016686 A1) discloses a traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus. Data in each cell references the particular forwarding resource to receive the cell. Each cell is assigned to one of several flow queues such that all cells assigned to the same flow queue are to be sent to the same forwarding resource.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOE CHACKO whose telephone number is (571)270-3318. The examiner can normally be reached Monday-Friday 7am-5pm.
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/JOE CHACKO/Primary Examiner, Art Unit 2457