DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 26, 2026 has been entered.
Claim Objections
Claim 18 objected to because of the following informalities:
In claim 18, “the PLL clock and configuration parameters.” in line 9 should be corrected to “the PLL clock and the configuration parameters.”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DP83TG721x-Q1 (“1000BASE-T1 Automotive Ethernet PHY with Advanced TSN and AVB”, Texas Instruments, June 2024).
Re claim 16, DP83TG721x-Q1 discloses of a method comprising: receiving, by Ethernet physical (PHY) including packet decoder circuitry (1722 CRF Packet Decode, Figures 5-2 and 5-3), a reference clock generator (wall clock generator as shown in Figures 5-2 and 5-3) coupled to the packet decoder circuitry (the coupling as shown in Figures 5-2 and 5-3), a media clock generator (PLL, Fig.5-2 and clock generator, Fig.5-3) coupled to the reference clock generator (the coupling as shown in Figures 5-2 and 5-3), and control circuitry (comparator, Fig.5-2) coupled to the reference clock generator and the media clock generator (the coupling as shown in Figures 5-2 and 5-3), a clock reference packet (The “1722 CRF Packet Decode” receives as input a clock reference format (CRF) packet, Page 5 and Figure 5-2); decoding, by the packet decoder circuitry of the Ethernet PHY (1722 CRF Packet Decode, Figures 5-2 and 5-3), a time stamp from the clock reference packet (the “1722 CRF Packet Decode” decodes the received CRF packets to generate CRF time stamps, Figure 5-2); adjusting (comparator, Fig.5-2), by the reference clock generator of the Ethernet PHY, a reference clock signal (wall clock, Figures 5-2 and 5-3) based on the time stamp (based on the CRF time stamps, Figure 5-2); and generating, by the media clock generator of the Ethernet PHY, a media clock based on the adjusted reference clock (output of FRAC-PLL/VCXO, Figure 5-2).
Re claim 19, DP83TG721x-Q1 discloses of further comprising: receiving, by a coder/decoder (CODEC) (Audio Codec, Figure 5-2), media data (Audio data, Figure 5-2); receiving, by the CODEC, a media clock signal (clock signal from Frac-PLL/VCXO, Figure 5-2); and provide a media stream responsive to the media data and the media clock (data output from CODEC, Figure 5-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over DP83TG721x-Q1 in view of Sarda (US 2021/0367748).
Re claim 17, DP83TG721x-Q1 discloses of further comprising receiving, by the Ethernet PHY, a subsequent clock reference packet; decoding, by the Ethernet PHY, a subsequent time stamp from the subsequent clock reference packet; adjusting, by the Ethernet PHY, the reference clock signal based on the subsequent time stamp; and generating, by the Ethernet PHY, a media clock based on the adjusted reference clock signal (see claim 1 for the current synchronization) ( The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables, Col 2, Page 1) (The DP83TG721-Q1 performs subsequent synchronizations for subsequent or different data transmissions/receptions). However, DP83TG721x-Q1 does not specifically disclose of wherein the media clock is adjusted over several cycles using a coarse adjustment and at least one fine adjustment.
Sarda teaches of a clock being adjusted over several cycles using a coarse adjustment and at least one fine adjustment (Figures 7 – 9).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the media clock adjusted over several cycles using a coarse adjustment and at least one fine adjustment for wide range and high precision.
Allowable Subject Matter
Claims 1 – 15 are allowed.
Claims 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633
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