Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2024/0096395 A1) in view of Bains et al. (US 20240211344 A1).
Regarding claim 1: Cho discloses a high bandwidth memory (HBM) device (memory device 120 may be a high bandwidth memory, par. 61) for managing row hammers comprising: a plurality of channels (CH1-CH8 of memory device 1100, FIG. 11) coupled to a host (memory device 1100 connected to host 110, par. 137), each channel associated with a command/address bus (command/address signal line of memory bus, par. 60) and a severity bus (memory bus between host 110 and memory device 120, FIG. 1); and a plurality of vertically stacked memory dies (dies 910 and 920, FIG. 11), each of the memory dies comprising: one or more memory banks (BANK1-BANK4, FIG. 2), each memory bank associated with one of the plurality of channels (each off the channels CH1-CH8 may include a plurality of banks, par. 140); one or more interfaces (logic die may include interfaces 911, par. 139), each interface associated with a channel (channels CH1-CH8 have interfaces, par. 137), from the plurality of channels, associated with a memory bank of the one or more memory banks (par. 140); and a row hammer alert circuit configured to: detect a row hammer attack (row hammer managing circuit detects row hammer attack, par. 14) on a memory bank of the one or more memory banks; transmit a row hammer alert (flag signal FLAG in response to row hammers, par. 96-100) over the severity bus of the channel associated with the memory bank, when the severity bus is not being used to transmit severity information.
Cho does not disclose a row hammer alert circuit configured to: determine whether the severity bus of the channel associated with the memory bank is transmitting severity information.
Bain does disclose a memory system for error checking (100) comprising: determine whether the severity bus (buses, e.g., data (DQ) bus, from I/O 1226, FIG. 12) of the channel associated with the memory bank is transmitting (data of error severity transmitted to host, par. 166) severity information.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Cho with the configuration of Bain to allow the system to monitor and adjust the operation based on the severity of the row hammer attack.
Regarding claim 6: Cho discloses a high bandwidth memory (HBM) device,
wherein the HBM device is comprised of 32 channels (8 channels CH1-CH8, par. 137).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a range of channels for operation, since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2024/0096395 A1) in view of Bains et al. (US 20240211344 A1), in further view of Wang et al. (US 2023/0409708 A1).
Regarding claim 2: Cho discloses an HBM device (120, par. 61) wherein each memory bank (BANK1-BANK4, FIG. 2) includes a plurality of rows of memory cells (memory cells of array 210, FIG. 2).
Cho does not disclose detecting the row hammer attack on the memory bank comprises: determining a number of mitigation queue entries associated with row addresses corresponding to the memory bank; and evaluating whether the determined number of mitigation queue entries exceeds a queue threshold.
Wang does disclose a system configured to mitigate risk from row hammer attacks (100), wherein detecting the row hammer attack on the memory bank comprises: determining a number of rows in the memory bank (number of rows counted for activation, par. 17) associated with an activation count (e.g., 171, 173,…, par. 57-58) that exceeds a first threshold (321) and does not exceed a second threshold (threshold trigger for second threshold different than first threshold, par. 92); and evaluating whether the determined number of rows exceeds a third threshold (activation counts associated with rows compared to threshold 169, par. 58, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho and Bains with the configuration of Wang to allows the system to detect and count the rows being monitored for row hammer attacks.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2024/0096395 A1) in view of Bains et al. (US 20240211344 A1), in further view of Lu (US 20240427497 A1).
Regarding claim 3: Cho discloses an HBM device (120, par. 61), wherein each memory bank includes a plurality of rows of memory cells (rows of memory cells array 210, FIG. 2) wherein the HBM device further comprises a mitigation queue (register 320) configured to queue row addresses (register 320 stores row hammer address detected during monitoring period, par. 91) associated with rows to be refreshed (refresh operation, par. 93).
Cho does not disclose an HBM device, wherein detecting the row hammer attack on the memory bank comprises: determining a number of mitigation queue entries associated with row addresses corresponding to the memory bank; and evaluating whether the determined number of mitigation queue entries exceeds a queue threshold.
Lu does disclose an apparatus for aggressor queue mitigation based threshold (100), wherein detecting the row hammer attack on the memory bank comprises: determining a number of mitigation queue entries (counter 248 counts value of access count of row addresses, par. 43) associated with row addresses corresponding to the memory bank; and evaluating whether the determined number of mitigation queue entries exceeds a queue threshold (compares counter 248 of aggressor queue 244 to threshold MT, par. 43).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho and Bains with the configuration of Lu to allow the system to keep track of the row addresses within the aggressor queue to handle the refresh operation.
Claim(s) 8, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20240427497 A1), in further view of Kim (US 20230143905 A1).
Regarding claim 8: Lu discloses an apparatus for aggressor queue mitigation based threshold (100), comprising: a memory array (118) including a plurality of rows of memory cells (par. 15); a row hammer mitigation circuit configured to determine whether to perform a mitigation action (e.g., moving to aggressor queue and refreshing rows, par. 12) on a row of the plurality of rows.
Lu does not disclose a HBM device, comprising: a row hammer alert circuit configured to: generate a row hammer alert; and transmit the row hammer alert over a severity interface of the memory device.
Kim does disclose a memory system for managing row hammers (20) comprising: a row hammer alert circuit configured to: generate a row hammer alert (alert signal when row hammer occurs, par. 10); and transmit the row hammer alert over a severity interface of the memory device (alert signal ALRT1 sent over interface between controller and memory device, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Lu with the alert system of Kim to have the system generate and send an alert signal to the memory device upon a row hammer detection.
Regarding claim 10: Lu discloses an apparatus for aggressor queue mitigation based threshold (100), wherein each row of the plurality of rows comprises activation count bits (each word line associated with a count value, where the memory cells of the word line storing bits, par. 11 and 17), wherein the memory device is configured to increment the activation count bits of a row when the row is activated (count incremented when row is accessed, par. 12), and wherein determining whether to perform the mitigation action on a row comprises comparing the activation count bits of the row to an activation threshold (row access count compared to a mitigation threshold, par. 12).
Regarding claim 12: Lu discloses an apparatus for aggressor queue mitigation based threshold (100), wherein the memory device further comprises a mitigation queue (aggressor address register 244, FIG. 2) configured to queue row addresses associated with rows (aggressor address register 244 stores identified aggressor addresses, par. 39), on which a mitigation action will be performed (targeted refresh, par. 39), and wherein generating the row hammer alert comprises: determining utilization of the mitigation queue (counter 248 counts value of access count of row addresses, par. 43); and evaluating whether the utilization exceeds a utilization threshold (compares counter 248 to threshold MT, par. 43).
Claim(s) 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20240427497 A1), in further view of Kim (US 20230143905 A1), in further view of Cho et al. (US 2024/0096395 A1).
Regarding claim 16: Lu and Kim do not disclose an HBM device wherein the memory device further comprises a plurality of channel interfaces, the plurality of channel interfaces coupled to a host, and wherein the generated row hammer alert is associated with a first channel interface of the plurality of channel interfaces.
Cho does disclose an HBM device (120, par. 61), wherein the memory device further comprises a plurality of channel interfaces (CH1-CH8 of memory device 1100, FIG. 11), the plurality of channel interfaces coupled to a host (memory device 1100 connected to host 110, par. 137), and wherein the generated row hammer alert is associated with a first channel interface (flag signal FLAG in response to row hammers, par. 96-100) of the plurality of channel interfaces.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Lu and Kim with the configuration of Cho to allow the alert interface to connect and send signals between the memory and coupled host.
Regarding claim 18: Lu and Kim do not disclose an HBM device wherein the memory device is a high bandwidth memory device.
Cho does disclose an HBM device (120, par. 61), wherein the memory device is a high bandwidth memory device (memory device 120 may be a high bandwidth memory, par. 61).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Lu and Kim with the configuration of Cho to the memory system to be a high bandwidth memory device such as the claimed invention.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20240427497 A1), in further view of Kim (US 20230143905 A1), in further view of Song (Song (US 20240428845 A1).)))
Regarding claim 9: Lu and Kim do not disclose a memory device, wherein determining whether to perform the mitigation action on a row comprises: randomly sampling requests received by the memory device from a host, each sampled request comprising a memory address; determining, for each sampled request, the row of the plurality of rows associated with the memory address; and evaluating a frequency of samples associated with the row.
Song does disclose a memory system (10) for row hammer detection wherein determining whether to perform the mitigation action on a row comprises: randomly sampling requests (randomly sampling rows of the memory device, par. 35) received by the memory device from a host, each sampled request comprising a memory address (rows are row hammer addresses, par. 35); determining, for each sampled request, the row of the plurality of rows associated with the memory address (each row associated with a row hammer address, par. 35); and evaluating a frequency of samples (refresh operation checks target rows for high activation frequency, par. 40) associated with the row.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Lu and Kim with the configuration of Song to allow the system to monitor and check the frequency of the row activations for mitigation.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20240427497 A1), in further view of Kim (US 20230143905 A1), in further view of Wang et al. (US 2023/0409708 A1).
Regarding claim 11: Lu and Kim do not disclose a memory device, wherein generating the row hammer alert comprises: determining a number of rows in the memory array associated with an activation count that exceeds a first threshold and does not exceed a second threshold; and evaluating whether the determined number of rows exceeds a third threshold.
Wang does disclose a system configured to mitigate risk from row hammer attacks (100), wherein generating the row hammer alert comprises: determining a number of rows in the memory bank (number of rows counted for activation, par. 17) associated with an activation count (e.g., 171, 173,…, par. 57-58) that exceeds a first threshold (321) and does not exceed a second threshold (threshold trigger for second threshold different than first threshold, par. 92); and evaluating whether the determined number of rows exceeds a third threshold (activation counts associated with rows compared to threshold 169, par. 58, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Lu and Kim with the configuration of Wang to allow the system to monitor the rows for activation frequency compared to a determined threshold.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20240427497 A1), in further view of Bains et al. (US 20240211344 A1), in further view of Ayyapureddi et al. (US 20220223195 A1).
Regarding claim 19: Bain discloses a method for a memory system for error checking (100) comprising: receiving, by a memory controller (e.g., control CTRL 1250), data over a severity interface (command bus 1214, FIG. 12) from a high bandwidth memory (HBM) device (memory subsystem may be an HBM (high bandwidth memory), par. 233) coupled to the severity interface (FIG. 12); determining whether the data is associated with severity information or row hammer alert information (determine the severity of errors related to row hammer attacks, par. 166 and 169); if the data is associated with row hammer alert information, evaluating the data to determine if a row hammer alert is indicated (determines if a row hammer attack has occurred and prepares mitigation, par. 169).
Bains does not disclose suspending, based on the determination that a row hammer alert is indicating, requests transmitted to the HBM device over a command/address interface associated with the severity interface.
Ayyapureddi does disclose a memory system for handling row hammer effects with delays, comprising: suspending, based on the determination that a row hammer alert is indicating (based on detection of row hammer, par 41), requests transmitted to the HBM device over a command/address (pausing commands across lines e.g., command/address bus, par. 41) memory device and controller interface associated with the severity interface.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bains with the configuration of Ayyapureddi to allow the system to have the channels available when needing to send certain alerts and signals across the interface buses at certain times.
Allowable Subject Matter
Claims 4-5,7,13-15, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having the HBM device is configured to transmit read data to the host over each data bus over a burst comprised of a plurality of burst positions, and wherein determining whether the severity bus is transmitting severity information comprises: determining whether the data bus of the channel associated with the severity bus is being used to transmit read data to the host; based on the determination that the data bus is being used to transmit read data, determining a current burst position of a current read burst; and evaluating whether the current burst position is used for severity information as in claim 4; wherein each channel is divided into a first pseudo channel and a second pseudo channel, wherein a first portion of the severity bus associated with a channel is associated with the first pseudo channel of the channel, wherein a second portion of the severity bus associated with the channel is associated with the second pseudo channel of the channel, wherein the row hammer alert is transmitted over the first portion of the severity bus, and wherein the row hammer alert circuit is further configured to transmit a second row hammer alert, over the second portion of the severity bus, in response to detecting a row hammer attack on a portion of the memory bank associated with the second pseudo channel as in claim 7; wherein the row hammer alert circuit is further configured to: determine whether severity information is being transmitted over the severity interface; maintain the generated row hammer alert in a row hammer alert state when severity information is being transmitted over the severity interface; and transmit the maintained row hammer alert, from the row hammer alert state, over the severity interface when severity information is no longer being transmitted as in claim 13; wherein the row hammer alert circuit is further configured to generate a second row hammer alert, associated with a second channel interface of the plurality of channel interfaces, and transmit the second row hammer alert over a second severity interface associated with the second channel interface as in claim 17; and transmitting a request to the HBM device, over a second command/address interface, while requests over the command/address interface are suspended as in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827