DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 08/25/2023. It is noted, however, that applicant has not filed a certified copy of the
KR10-2023-0111675 application as required by 37 CFR 1.55.
Claim Objections
Claim 5 is objected to because of the following informalities:
As to claim 5, the phrase “the predetermined time duration” in line 4 of the claim should be changed to “a predetermined time duration”, since “a predetermined time duration” was not previously recited in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9, 11-14,19, 21-22 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2023/0237965 A1).
As to claim 1, Lin et al. teaches a display device ([0039]: display) comprising: a display panel (14 in Fig. 2;[0043]: display 14) including a plurality of pixels ([0043]: pixels 22); and a power supply for supplying a bias voltage (VOBS in Figs. 18A-18B;[0046]: Bias circuitry 27 driving bias voltages onto pixels) and an anode reset voltage to the plurality of pixels (Var in Figs. 18A-18B;[0118]: transistor Tar to perform anode reset for the OLED;[0122]; Fig. 18A shows transistor Tar connected to anode reset voltage Var), wherein when the display device operates in a variable refresh rate (VRR) mode, the display device is configured to adjust at least one of a level or an application time of the bias voltage based on a refresh rate in an anode reset frame ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate); [0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Bias voltage Vobs adjusted. Fig. 18B shows bias voltage VOBS during period Δt2 and Δt5 is lower than bias voltage VOBS during period Δt8 and Δt9). As to claim 2, Lin et al. teaches the display device of claim 1, wherein when the refresh rate falls within a first reference range, the display device is configured to apply a first bias voltage in a refresh frame ([0086]: Display 14 supports low refresh rate operation, 60 Hz data refresh operation; [0118]; [0121]: during the active/refresh period, selectively pulsing signal SC3(n). Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5), and apply a second bias voltage higher than the first bias voltage in the anode reset frame ([0118]: Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs and will also turn on transistor Tar to perform anode reset for the OLED. Fig. 18B shows bias voltage VoBS during period Δt8 and Δt9 is higher than bias voltage VoBS during period Δt2 and Δt5). As to claim 3, Lin et al. teaches the display device of claim 2, wherein the first reference range is 10 Hz or higher ([0086]: 60 Hz data refresh operation). As to claim 9, Lin et al. teaches the display device of claim 1, wherein the display device further comprises a gate driver for applying a gate signal to the display panel ([0050]: row driver circuitry 18 provides row control signals. Row driver circuitry 18 includes scan line driver circuitry for driving the scan lines;[0053]),wherein the display device is configured to control at least one of the power supply or the gate driver to adjust at least one of the level or the application time of the bias voltage ([0045]: display driver integrated circuit 15 supplies clock signals and other control signals to display driver circuitry such as row driver circuitry 18;[0050]: Row driver circuitry 18 includes scan line driver circuitry referred to as gate driver circuitry; [0118]; [0121-0123]: SC3 signal driver asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor. Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5 is lower than bias voltage VoBS during period Δt8 and Δt9). As to claim 11, Lin et al. teaches the display device of claim 1, wherein the display device is configured to apply the bias voltage of a fixed level in a refresh frame ([0118]; [0121]: active/refresh period, Fig. 18B shows fixed bias voltage VoBS during period Δt2 and Δt5).
As to claim 12, Lin et al. teaches a display device ([0039]: display) comprising: a display panel (14 in Fig. 2;[0043]: display 14) including a plurality of pixels ([0043]: pixels 22), wherein each of the plurality of pixels ([0043]: pixels) includes: a light-emitting element configured to emit light in response to a driving current ([0057]: drive transistor Tdrive controls the amount of current flowing from terminal 300 to terminal 302 through diode 304, and therefore the amount of emitted light); a driving transistor configured to control the driving current ([0057]: drive transistor Tdrive controls the amount of current flowing from terminal 300 to terminal 302 through diode 304); a capacitor (capacitor Cst in Fig. 18A) connected between a high potential driving voltage (VDDEL in Fig. 18A;[0057]: voltage VDDEL) and a gate electrode of the driving transistor (transistor Tdrive in Fig. 18A); a first transistor (transistor Toxide in Fig. 18A) configured to connect the gate electrode and a drain electrode of the driving transistor (transistor Tdrive in Fig. 18A; [0007]: semiconducting-oxide transistor coupled between gate and drain terminals of the drive transistor) to each other in response to a first scan signal ([0087]: Semiconducting-oxide transistor Toxide has a gate terminal configured to receive a first scan control signal SC1(n)); a second transistor configured to apply a data voltage to a source electrode of the driving transistor in response to a second scan signal ([0120]: driving signal SC2 low will turn on transistor Tdata to load the desired data signal onto the source terminal of the drive transistor); a third transistor configured to apply the high-potential driving voltage to the source electrode of the driving transistor in response to a light-emission control signal ([0057];[0062]: emission control signal EM(n) asserted (e.g., driven low or temporarily pulsed low) to turn on transistors Tem1 and Tem2 during an emission phase to allow current to flow through light-emitting diode 304); a fourth transistor configured to connect the drain electrode of the driving transistor and the light-emitting element to each other in response to the light-emission control signal to establish a current flow path between the high-potential driving voltage and the low-potential driving voltage ([0057];[0061-0062]: emission control signal EM(n) asserted (e.g., driven low or temporarily pulsed low) to turn on transistors Tem1 and Tem2 during an emission phase to allow current to flow through light-emitting diode 304); and a fifth transistor configured to apply a bias voltage to the source electrode of the driving transistor in response to a third scan signal ([0118]: Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs to the source terminal of the drive transistor) , wherein when the display device operates in a Variable Refresh Rate (VRR) mode, the display device is configured to adjust at least one of a level or an application time of the bias voltage based on a refresh rate in an anode reset frame ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate); [0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Bias voltage Vobs adjusted. Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5 is lower than bias voltage VoBS during period Δt8 and Δt9). As to claim 13, Lin et al. teaches the display device of claim 12, wherein when the refresh rate falls within a first reference range, the display device is configured to apply a first bias voltage in a refresh frame ([0086]: Display 14 supports low refresh rate operation, 60 Hz data refresh operation; [0118]; [0121]: during the active/refresh period, selectively pulsing signal SC3(n). Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5), and apply a second bias voltage higher than the first bias voltage in the anode reset frame ([0118]: Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs and will also turn on transistor Tar to perform anode reset for the OLED. Fig. 18B shows bias voltage VoBS during period Δt8 and Δt9 is higher than bias voltage VoBS during period Δt2 and Δt5). As to claim 14, Lin et al. teaches the display device of claim 13, wherein the first reference range is 10 Hz or higher ([0086]: 60 Hz data refresh operation). As to claim 19, Lin et al. teaches the display device of claim 12, wherein when the display device operates in the VRR mode, the display device is configured to apply a first bias voltage of a fixed level in a refresh frame ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate; [0118]; [0121]: active/refresh period, Fig. 18B shows fixed bias voltage VoBS during period Δt2 and Δt5).
As to claim 21, Lin et al. teaches a display device comprising: a display panel (14 in Fig. 2;[0043]: display 14) including a plurality of pixels ([0043]: pixels 22),each pixel including a bias transistor ([0118]: Asserting signal SC3(n) will turn on transistor Tobs to apply Vobs to the source terminal of the drive transistor) and a driving transistor ([0057]: drive transistor Tdrive controls the amount of current flowing from terminal 300 to terminal 302 through diode 304); a gate driver configured to control the bias transistor to apply a first bias voltage to a terminal of the driving transistor in a refresh frame ([0050]: Row driver circuitry 18 includes scan line driver circuitry referred to as gate driver circuitry; [0118]; during the active/refresh period, selectively pulsing signal SC3(n);[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor) and to apply a second bias voltage to the terminal of the driving transistor in an anode reset frame, the second bias voltage greater than the first bias voltage ([0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED; Fig. 18B shows bias voltage VOBS during period Δt8 and Δt9 is greater than bias voltage VOBS during period Δt2 and Δt5), and a voltage value of the second bias voltage variable based on a refresh rate of an operation of the display device ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate);[0118]: during the active/refresh period, selectively pulsing signal SC3(n);[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor. Bias voltage Vobs adjusted. Bias voltage Vobs different between the active and blanking periods). As to claim 22, Lin et al. teaches the display device of claim 21, wherein in response to the refresh rate is higher than a threshold ([0049]: greater than 60Hz), the second bias voltage maintains a same value for the anode reset frame ([0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED; Fig. 18B shows bias voltage VOBS maintains a same value during period Δt8 and Δt9).
As to claim 24, Lin et al. teaches the display device of claim 21, wherein an application time of the second bias voltage is variable based on the refresh rate of the operation of the display device ([0086]: blanking period T_blank at least two times, at least ten times, at least 30 times, or at least 60 times longer in duration than T_refresh; [0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor; Fig. 18B shows second bias voltage VoBS during period Δt8 and Δt9 of the blanking period) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 8, 10, 15, 18, 20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2023/0237965 A1) in view of Park et al. (US 2024/0144881 A1).
As to claim 4, Lin et al. teaches the display device of claim 1, wherein when the refresh rate falls within a second reference range ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate), the display device is configured to apply a first bias voltage in a refresh frame ([0118]; [0121]: active/refresh period; Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5), apply a second bias voltage higher than the first bias voltage for a first timed duration of the anode reset frame ([0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Fig. 18B shows bias voltage VoBS during period Δt8 and Δt9 is higher than bias voltage VoBS during period Δt2 and Δt5), but does not disclose apply a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame.
However, Park et al. teaches apply a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame ([0088]:light emitting element initialization switching element T7 (e.g., a seventh transistor) and bias switching element T9 include control electrode receiving gate signal EB; [0091]:[0166-0167]: In FIG. 14, the bias voltage VBIAS in the third duration DR3 is set to be greater than the bias voltage VBIAS in the second duration DR2 and the bias voltage VBIAS in the second duration DR2 is set to be greater than the bias voltage VBIAS in the first duration DR1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin et al. by applying a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame as taught by Park et al. in order to increase the display quality of the display panel.
As to claim 8, Lin et al. in view of Park et al. teaches the display device of claim 4, wherein the second reference range is lower than 10 Hz (Lin et al.,[0086]: low refresh rate (e.g., a refresh rate of 1 Hz, 2 Hz).
As to claim 10, Lin et al. teaches the display device of claim 9, wherein the display device is configured to adjust at least one of the level and the application time of the bias voltage in different manners ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate); [0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5 is lower than bias voltage VoBS during period Δt8 and Δt9), but does not explicitly disclose based on different reference ranges which the refresh rate falls within.
However, Park et al. teaches based on different reference ranges which the refresh rate falls within ([0005]: adjusting a level of a bias voltage when a driving frequency of a display panel is changed from a high driving frequency to a low driving frequency; [0155-0156]: When the difference between the high driving frequency and the low driving frequency is relatively great, the difference between the bias voltage VBIAS in the first low frequency frame FR1 and the bias voltage VBIAS in the high frequency frame (the period prior to FR1) is relatively great;[0166-0167] In FIG. 14, the bias voltage VBIAS in the third duration DR3 is set to be greater than the bias voltage VBIAS in the second duration DR2 and the bias voltage VBIAS in the second duration DR2 is set to be greater than the bias voltage VBIAS in the first duration DR1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin et al. by adjusting at least one of the level and the application time of the bias voltage in different manners based on different reference ranges which the refresh rate falls within as taught by Park et al. in order to increase the display quality of the display panel.
As to claim 15, Lin et al. teaches the display device of claim 12, wherein when the refresh rate falls within a second reference range ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate), the display device is configured to apply a first bias voltage in a refresh frame([0118]; [0121]: active/refresh period; Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5), apply a second bias voltage higher than the first bias voltage for a first timed duration of the anode reset frame ([0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Fig. 18B shows bias voltage VoBS during period Δt8 and Δt9 is higher than bias voltage VoBS during period Δt2 and Δt5), but does not disclose apply a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame.
However, Park et al. teaches apply a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame ([0088]:light emitting element initialization switching element T7 (e.g., a seventh transistor) and bias switching element T9 include control electrode receiving gate signal EB; [0091]:[0166-0167]: In FIG. 14, the bias voltage VBIAS in the third duration DR3 is set to be greater than the bias voltage VBIAS in the second duration DR2 and the bias voltage VBIAS in the second duration DR2 is set to be greater than the bias voltage VBIAS in the first duration DR1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin et al. by applying a third bias voltage higher than the second bias voltage for a second time duration of the anode reset frame as taught by Park et al. in order to increase the display quality of the display panel.
As to claim 18, Lin et al. in view of Park et al. teaches the display device of claim 15, wherein the second reference range is lower than 10 Hz (Lin et al.,[0086]: low refresh rate (e.g., a refresh rate of 1 Hz, 2 Hz).
As to claim 20, Lin et al. teaches the display device of claim 12, wherein the display device is configured to adjust at least one of the level and the application time of the bias voltage in different manners ([0086]: Display 14 supports low refresh rate operation (e.g., a refresh rate of 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low rate); [0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED. Fig. 18B shows bias voltage VoBS during period Δt2 and Δt5 is lower than bias voltage VoBS during period Δt8 and Δt9), but does not explicitly disclose based on different reference ranges which the refresh rate falls within.
However, Park et al. teaches based on different reference ranges which the refresh rate falls within ([0005]: adjusting a level of a bias voltage when a driving frequency of a display panel is changed from a high driving frequency to a low driving frequency; [0155-0156]: When the difference between the high driving frequency and the low driving frequency is relatively great, the difference between the bias voltage VBIAS in the first low frequency frame FR1 and the bias voltage VBIAS in the high frequency frame (the period prior to FR1) is relatively great;[0166-0167]: In FIG. 14, the bias voltage VBIAS in the third duration DR3 is set to be greater than the bias voltage VBIAS in the second duration DR2 and the bias voltage VBIAS in the second duration DR2 is set to be greater than the bias voltage VBIAS in the first duration DR1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin et al. by adjusting at least one of the level and the application time of the bias voltage in different manners based on different reference ranges which the refresh rate falls within as taught by Park et al. in order to increase the display quality of the display panel.
As to claim 23, Lin et al. teaches the display device of claim 21, wherein in response to the refresh rate is smaller than a threshold ([0086]: Display 14 supports low refresh rate operation (e.g. less than 30 Hz, less than 60 Hz, or other low rate), the second bias voltage includes a first voltage value at a first period of time in the anode reset frame and a second voltage value at a second period of time in the anode reset frame ([0118];[0121-0123]: Asserting signal SC3(n) turns on transistor Tobs to apply Vobs to the source terminal of the drive transistor and will also turn on transistor Tar to perform anode reset at the OLED; Fig. 18B shows bias voltage VOBS during period Δt8 and Δt9), the second period of time subsequent to the first period of time (Fig. 18B shows bias voltage VOBS during period Δt9 subsequent to period Δt8), but does not explicitly disclose the second voltage value greater than the first voltage value. However, Park et al. teaches the second voltage value greater than the first voltage value ([0167]: In FIG. 14, the bias voltage VBIAS in the third duration DR3 is set to be greater than the bias voltage VBIAS in the second duration DR2, the bias voltage VBIAS in the second duration DR2 is set to be greater than the bias voltage VBIAS in the first duration DR1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin et al. such that the second voltage value is greater than the first voltage value as taught by Park et al. in order to increase the display quality of the display panel.
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the claim objection(s) in the office action, and in independent form including all of the limitations of the base claim and any intervening claims.
Claim 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624