Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on August 3, 2023. It is noted, however, that applicant has not filed a certified copy of the JP 2023-127274 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 30, 2024, was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the following as described in the specification:
[0050] “The depth of the bottom of the back gate region 16 is smaller than that of a bottom of the drift region 17.” In FIG. 6, 7, and 10, back gate region 16 is shown to have a depth larger than that of drift region 17.
[0056] “…the high concentration portion 35 of the second well region 18.” In FIG. 6, 7, and 10, the high concentration portion 35 and the second well region 18 are distinct and separate. High concentration portion 35 is instead shown to be part of back gate region 16.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “41” has been used to designate both the opening above the first drain 29 (FIG. 3 and 4) and an opening above the silicide layer 60 (FIG. 7). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
[0106] “From FIG. 9, it can be seen that when the fourth width W4 is 0.4 um or more and 0.6 um or less, the on-breakdown voltage of the semiconductor device 1 can be maintained high.” In FIG. 9, it is more so demonstrated that 0.6um to 0.8um represents the high on-breakdown voltage range. Additionally, the claims specify a range of 0.6um to 0.8um.
Appropriate correction is required.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8 and 10-11 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being clearly anticipated by Shin (US 20210028166 A1), hereinafter referred to as “Shin”.
Regarding Claim 1, Shin discloses a semiconductor device ([0053] “the semiconductor device”; FIG. 1-12), comprising:
a semiconductor chip having a first main surface (FIG. 1, 3-5, 8: upper surface of the chip) and a second main surface opposite to the first main surface (FIG. 1, 3-5, 8: lower surface of substrate 10);
a first drain region of a first conductivity type formed in a surface layer portion of the first main surface ([0058] “Highly doped N-type (N+) drain regions 85L and 85R”; FIG. 1, 5, 8: 85L, 85R);
a back gate region of a second conductivity type formed to be spaced apart from the first drain region in the surface layer portion of the first main surface ([0055] “a P-type well (PW) 100”; FIG. 1, 4-5, 8: 100);
a source region of the first conductivity type formed to be spaced inward from a peripheral edge of the back gate region in a surface layer portion of the back gate region ([0058] “Highly doped N-type (N+) source regions 83L and 83R”; FIG. 1, 5, 8: 83L, 83R);
a back gate contact region of the second conductivity type formed to be electrically isolated from the source region in the surface layer portion of the back gate region ([0058] “highly doped P-type (P+) bulk tap region 87”; FIG. 1, 5, 8: 87); and
a gate electrode facing a channel region formed in the back gate region between the peripheral edge of the back gate region and the source region ([0064] “a ring-shaped gate electrode 110”; FIG. 1, 5, 8: 110, It is noted that the existence of a gate electrode implies the existence of a channel region).
Regarding Claim 2, Shin discloses the semiconductor device of claim 1, and further discloses the back gate region having a band shape extending in the first direction along the main surface ([0056] “The semiconductor device further comprises the PW 100 in the shape of a corner-rounded rectangle”; FIG. 2, 6-7, 9-11: 100), and
wherein the source region and back gate contact region are formed while being spaced apart from each other in a second direction intersecting the first direction ([0062] “The first, second, and third insulating isolation regions 72, 73, and 76 have a structure for effectively isolating the respective regions by opening portions of the bulk tap region 87, the source regions 83L and 83R, and the drain regions 85L and 85R.”; FIG. 1, 5, 8: 73, 83L, 83R, 87).
Regarding Claim 3, Shin discloses the semiconductor device of claim 2, and further discloses the source region and the back gate contact region having a band shape extending along the first direction (FIG. 2, 6-7, 9-11: 83L, 83R, 87).
Regarding Claim 5, Shin discloses the semiconductor device of claim 3, and further discloses the source region including a pair of source regions formed to sandwich the back gate contact region in the second direction (FIG. 1, 5, 8: 85L, 85R).
Regarding Claim 6, Shin discloses the semiconductor device of claim 1, and further discloses the source region and the back gate contact region being electrically isolated from each other by a field insulating film in the surface layer portion of the back gate region ([0062] “The first, second, and third insulating isolation regions 72, 73, and 76 have a structure for effectively isolating the respective regions by opening portions of the bulk tap region 87, the source regions 83L and 83R, and the drain regions 85L and 85R.”; FIG. 1, 5, 8: 73, 83L, 83R, 87).
Regarding Claim 8, Shin discloses the semiconductor device of claim 1, and further discloses a first impurity region of the second conductivity type formed below the back gate region ([0055] “a P-type deep well (DPW) 60”; FIG. 1, 3-5, 8: 60).
Regarding Claim 10, Shin discloses the semiconductor device of claim 8, and further discloses a peripheral edge of the first impurity being formed to be3 spaced inward from the peripheral edge of the back gate region in a direction along the main surface ([0057] “the horizontal area (diameter) of the PW 100 is larger than the horizontal area (diameter) of the DPW 60”; FIG. 1, 4-11: 60, 100).
Regarding Claim 11, Shin discloses the semiconductor device of claim 8, and further discloses the first impurity region being in contact with the back gate region (FIG. 1, 4-5, 8: 60, 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shin.
Shin teaches the semiconductor device of claim 3. Shin does not teach the back gate contact region in the second direction being between 0.6 and 0.8 um.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the width of the back gate contact region of Shin with routine experiment and optimization in order to maintain a high on-breakdown voltage. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Murukesan et al. (US 20190131296 A1), hereinafter referred to as Murukesan.
Shin teaches the semiconductor device of claim 1, but does not teach an interlayer insulating film, a back gate wiring, a source wiring, a back gate contact, and a source contact.
Murukesan teaches a LDMOS ([0029] “the bootstrap MOS device 102 may be a laterally diffused metal-oxide-semiconductor (LDMOS) device”) comprising:
an interlayer insulating film covering the first main surface (FIG. 4, 6: It is noted that conductive vias 446 inherently penetrate an insulating layer, as known in the art);
a back gate wiring formed over the interlayer insulating film (FIG. 4A: 444, referencing the wire above bootstrap body contact region 120);
a source wiring which is a wiring different from the back gate wiring and is formed over the interlayer insulating film (FIG. 4A: 444, referencing the wire above the first bootstrap source/drain region 116);
a back gate contact which penetrates the interlayer insulating film and connects he back gate region and the back gate wiring (FIG. 4A: 446, referencing the via above the bootstrap body contact region 120, which is connected to bootstrap body well 114); and
a source contact which penetrates the interlayer insulating film and connects the source region and the source wiring (FIG. 4A: 446, referencing the via above first bootstrap source/drain region 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shin with the wiring and vias of Murukesan. The whole connective structure of the claimed invention serves to electrically couple contact regions of the same type across the entire semiconductor device, similar to Murukesan ([0076] “he conductive paths provide electrically coupling between the various contact regions (e.g., the peripheral contact region 408), the various fields plates (e.g., the bootstrap field plate 416), the various gate electrodes (e.g., the HVMOS gate electrode 134), the various source/drain regions (e.g., the first bootstrap source/drain region 116), and the spiral structure 442.”) Modifying the device of Shin with the interconnect structure of Murukesan would lead to the predictable result of the entire device being one cohesive unit, as opposed to distinct semiconductor devices.
Allowable Subject Matter
Claims 9 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiang et al. (US 20240321894 A1), Naquin et al. (US 20230317846 A1), Edwards (US 20220384636 A1), and Murukesan (US 20210399087 A1) are cited to teach aspects of a LDMOS with circular or looped structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SHEN whose telephone number is (571)272-0642. The examiner can normally be reached M-Th 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW L SHEN/ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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