DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20150318293 A1 – hereinafter Lee).
Regarding independent claim 1, Lee teaches:
A semiconductor device ([0020] – “non-volatile memory device” – this is
a semiconductor device, hereinafter ‘DEV’), comprising:
a source region (116c – Fig. 4F – [0069] – “source region 116c”) in a substrate
(110 – Fig. 4F – [0069] – “substrate 110”);
a drain region (113d – Fig. 4F – [0069] – “drain region 113d”) in the substrate
(110);
a gate structure (120 – Fig. 4F – [0069] – “gate structure 120”) laterally
between the source region (116c) and the drain region (113d);
a first gate spacer (133d – Fig. 4F – [0069] – “first spacer 133d”) on a first
sidewall of the gate structure (120); and
a second gate spacer (134c – Fig. 4F – [0071] – “second spacer 134c”) on a
second sidewall of the gate structure (120), wherein the first gate spacer (133d – [0071] – “first spacer 133d may include a first spacer insulating layer 134d and a second spacer insulating layer 136d”) has more layers than the second gate spacer (134c – Fig. 4F shows this).
Claims 11 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feilchenfeld et al. (US 20120126319 A1 – hereinafter Feilchenfeld).
Regarding independent claim 11, Feilchenfeld teaches:
A semiconductor device (LDMOSFET – [0003] – “lateral diffusion metal-
oxide-semiconductor field effect transistor (LDMOSFET)” – this is a semiconductor device), comprising:
a first doped region (42 – Fig. 9 – [0105] – “source region 42 having a doping”)
in a substrate (10 – Fig. 9 – [0085] – “substrate semiconductor region 10”);
a second doped region (44 – Fig. 9 – [0112] – “drain region 44 having a
doping”) in the substrate (10);
a gate structure (60 – Fig. 9 – [0087] – “gate electrode 60”) laterally between
the first doped region (42) and the second doped region (44), the gate structure (60) being separated from the first doped region (42) and the second doped region (44) by a first distance and a second distance, respectively, wherein the first distance is different from the second distance (Fig. 9 annotated, see below, shows this);
a first spacer (62 and 72 – Fig. 9 – [0095] – “a second gate spacer 72 is formed directly on and around the first gate spacer 62” – this corresponds to the first gate spacer) on a first sidewall of the gate structure (60); and
a second spacer (62) on a second sidewall of the gate structure (60), wherein the first spacer (62 and 72) has more layers than the second spacer (62 – Fig. 9 shows this).
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Regarding claim 19, Feilchenfeld teaches claim 11 from which claim 19 depends. Feilchenfeld further teaches
wherein the first spacer (62 and 72) has a top end higher than a top
end of the second spacer (62 – Fig. 9 shows this).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chang et al. (US 20170200650 A1 – hereinafter Chang).
Regarding claim 2, Lee teaches claim 1 from which claim 2 depends. Lee does not expressly disclose the limitations of claim 1.
However, in an analogous art, Chang teaches
wherein the first gate spacer is a tri-layer spacer (124 – Fig. 6 – [0025] – “The spacer 124 may be, for example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the tri-layer spacer structure as taught by Chang into Lee.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results of [0006] – “a semiconductor device structure, which is capable of reducing the variation of the breakdown voltage of an HV MOS device.”
Regarding claim 3, Lee teaches claim 1 from which claim 3 depends. Lee further teaches
wherein the second gate spacer is a single-layer spacer (134c –
Fig.4F – [0089] – “the second spacer 134c having a single spacer structure”).
Regarding claim 4, Lee teaches claim 1 from which claim 4 depends. Lee further teaches
wherein the first gate spacer (133d) is adjacent the drain region
(113d), and the second gate spacer (134c) is adjacent the source region (116c – Fig. 4F shows this).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Feilchenfeld.
Regarding claim 5, Lee teaches claim 1 from which claim 5 depends. Lee does not expressly disclose the limitations of claim 1.
However, in an analogous art, Feilchenfeld teaches
wherein more than one dielectric material ({[0094] – “first gate spacer 62 may
comprise a dielectric material such as silicon nitride and/or silicon oxide”}, {[0097] – “the second gate spacer 72 may comprise a material selected borophosphosilicate glass (BPSG), an anti-reflective coating material, and a silicon oxide”}) in the first gate spacer (62 and 72 – Fig. 9 – [0095] – “a second gate spacer 72 is formed directly on and around the first gate spacer 62” – this corresponds to the first gate spacer) is in contact with the first sidewall of the gate structure (60 – Fig. 9 – [0095] – “gate electrode 60”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the spacer structure as taught by Feilchenfeld into Lee.
An ordinary artisan would have been motivated to use the known technique of Feilchenfeld in the manner set forth above to produce the predictable results of [0002] – “lateral diffusion metal-oxide-semiconductor field effect transistors (LDMOSFETs) having a drain region that is self-aligned to a gate electrode to provide a constant drift distance, and consequently, a constant drift region resistance, and methods of manufacturing the same.”
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Feilchenfeld in view of Hwang (US 20090115000 A1).
Regarding independent claim 6, Feilchenfeld teaches:
A semiconductor device (LDMOSFET – [0003] – “lateral diffusion metal-
oxide-semiconductor field effect transistor (LDMOSFET)” – this is a semiconductor device), comprising:
a transistor gate (60 – Fig. 9 – [0087] – “gate electrode 60”) over a substrate
(10 – Fig. 9 – [0085] – “substrate semiconductor region 10”);
a multi-layer spacer (62 and 72 – Fig. 9 – [0095] – “a second gate spacer 72 is
formed directly on and around the first gate spacer 62” – this corresponds to the first gate spacer) spacing apart a first sidewall of the transistor gate (60) from a first source/drain region (42/44 – Fig. 9 – [0105] – “the source region 42 and the drain region 44”); and
a spacer spacing apart a second sidewall of the transistor gate from a second source/drain region, wherein the multi-layer spacer (62 and 72) has a top position higher than a top position of the spacer (62) and lower than a top surface of the transistor gate (60), wherein the multi-layer spacer (62 and 72) has more layers than the spacer (62 – Fig. 9 shows this).
Feilchenfeld does not expressly disclose the limitations of claim 5.
However, in an analogous art, Hwang teaches
a spacer (110 – Fig. 3F – [0015] – “spacers 110 and 112”) spacing apart a second sidewall of the transistor gate (108A – Fig. 3F – [0015] – “Poly-gate 108A”) from a second source/drain region (142 – Fig. 3F – [0025] – “silicide layer 142 is formed on and/or over source/drain region 120A” – this corresponds to a second source/drain region).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the spacer structure as taught by Hwang into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Hwang in the manner set forth above to produce the predictable results of [0004] – “a semiconductor device such as a transistor, and more particularly, to a semiconductor device and a method for manufacturing the same that reduces gate depletion.”
Regarding claim 9, Feilchenfeld, as modified by Hwang, teaches claim 6 from which claim 5 depends. Feilchenfeld further teaches
wherein the multi-layer spacer (62 and 72) comprises more than one
dielectric layer ({[0094] – “first gate spacer 62 may comprise a dielectric material such as silicon nitride and/or silicon oxide”}, {[0097] – “the second gate spacer 72 may comprise a material selected borophosphosilicate glass (BPSG), an anti-reflective coating material, and a silicon oxide”}) in contact with the transistor gate (60 – Fig. 9 shows this).
Claims 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Feilchenfeld in view of Hwang and Chang.
Regarding claim 7, Feilchenfeld, as modified by Hwang, teaches claim 6 from which claim 7 depends. Feilchenfeld and Hwang do not expressly disclose the limitations of claim 7.
However, in an analogous art, Chang teaches
wherein the multi-layer spacer (120 – Fig. 6 – [0025] – “silicon nitride layer
120”) has a bottom position lower than a bottom position of the spacer (118 – Fig. 6 – [0025] – “silicon oxide layer 118”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Chang into Feilchenfeld and Hwang.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 8, Feilchenfeld, as modified by Hwang and Chang, teaches claim 7 from which claim 8 depends. Feilchenfeld and Hwang do not expressly disclose the limitations of claim 8.
However, in an analogous art, Chang teaches
further comprising:
a gate dielectric layer (106c – Fig. 6 – [0025] – “gate dielectric layer 106c”)
below the transistor gate (114a – Fig. 6 – [0025] – “gate electrode 114a”), wherein a difference in height between the bottom position of the multi-layer spacer (120) and the bottom position of the spacer (118) is a thickness of the gate dielectric layer (106c – Fig. 6 annotated, see below shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate dielectric layer structure as taught by Chang into Feilchenfeld and Hwang.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 10, Feilchenfeld, as modified by Hwang, teaches claim 6 from which claim 10 depends. Feilchenfeld and Hwang do not expressly disclose the limitations of claim 10.
However, in an analogous art, Chang teaches
wherein the multi-layer spacer (124) comprises more than one dielectric
layer ([0025] – “The spacer 124 may be, for example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”) in contact with a gate dielectric (106c) below the transistor gate (114a – Fig. 6 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer structure as taught by Chang into Feilchenfeld and Hwang.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Feilchenfeld in view of Chang.
Regarding claim 12, Feilchenfeld, teaches claim 11 from which claim 12 depends. Feilchenfeld does not expressly disclose the limitations of claim 12.
However, in an analogous art, Chang teaches
wherein the first spacer (124 – Fig. 6 – [0025] – “The spacer 124 may be, for
example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”) includes a first layer (118 – Fig. 6 – [0025] – “silicon oxide layer 118”), a second layer (120 – Fig. 6 – [0025] – “silicon nitride layer 120”) over the first layer (118), and a third layer (122 – Fig. 6 – [0025] – “silicon oxide layer 122”) over the second layer (120 – Fig. 6 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Chang into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 13, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 13 depends. Feilchenfeld does not expressly disclose the limitations of claim 13.
However, in an analogous art, Chang teaches
wherein the second layer (120) is formed of a different material ([0025] –
“The spacer 124 may be, for example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”) than the first layer (118).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Chang into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 14, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 14 depends. Feilchenfeld does not expressly disclose the limitations of claim 14.
However, in an analogous art, Chang teaches
wherein the third layer (122) is formed of a different material ([0025] – “The
spacer 124 may be, for example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”) than the second layer (120).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Chang into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 15, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 15 depends. Feilchenfeld does not expressly disclose the limitations of claim 15.
However, in an analogous art, Chang teaches
wherein the third layer (122) is formed of a same material ([0025] – “The
spacer 124 may be, for example, an ONO composite spacer that includes a silicon oxide layer 118 nearest to the sidewall of the gate electrode 114a or 114b, a silicon nitride layer 120 on the sidewall of the silicon oxide layer 118, and another silicon oxide layer 122 on the sidewall of the silicon nitride layer 120”) as the first layer (118).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Chang into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Chang in the manner set forth above to produce the predictable results as stated above in claim 2.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Feilchenfeld in view of Chang and Loubet et al. (US 20140151759 A1 – hereinafter Loubet).
Regarding claim 16, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 16 depends. Feilchenfeld and Chang do not expressly disclose the limitations of claim 16.
However, in an analogous art, Loubet teaches
wherein the first (720 – Fig. 7C – [0055] – “nitride spacer layer 720”) and third
(724 – Fig. 7C – [0055] – “nitride spacer layer 724”) layers are formed of a nitride material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Loubet into Feilchenfeld and Chang.
An ordinary artisan would have been motivated to use the known technique of Loubet in the manner set forth above to produce the predictable results of [0007] – “it has been observed that faceting occurs when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary (e.g., silicon dioxide (SiO.sub.2), as shown in FIG. 1A), but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary (as shown in FIG. 1B) or adjacent to a nitride boundary (e.g., silicon nitride (SiN)). Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting are desirable. One such technique, presented herein, is to line the isolation trenches with SiN so that the SiN liner provides a barrier between the oxide and the region in which epitaxial growth is intended.”
Regarding claim 17, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 17 depends. Feilchenfeld and Chang do not expressly disclose the limitations of claim 17.
However, in an analogous art, Loubet teaches
wherein the second layer (722 – Fig. 7C – [0055] – “oxide spacer layer 722”) is
formed of an oxide material.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the multi-layer spacer structure as taught by Loubet into Feilchenfeld and Chang.
An ordinary artisan would have been motivated to use the known technique of Loubet in the manner set forth above to produce the predictable results as stated above in claim 16.
Regarding claim 18, Feilchenfeld, as modified by Chang, teaches claim 12 from which claim 18 depends. Feilchenfeld and Chang do not expressly disclose the limitations of claim 18.
However, in an analogous art, Loubet teaches
wherein the gate structure ([0054] – “a gate stack can be deposited including a
gate dielectric 712, a gate having a first gate layer 714 and a second gate layer 716, and a hard mask 718”) comprises a gate dielectric (712 – Fig. 7C – [0054] – “gate dielectric 712”) and a gate conductor (716 – Fig. 7C – [0054] – “second gate layer 716 can be a silicide such as nickel silicide”) over the gate dielectric (712), wherein the second layer (722) of the first spacer (720, 722, and 724 – this is interpreted as the first spacer) has a same material as the gate dielectric ([0054] – “gate dielectric can be made of silicon dioxide”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate structure as taught by Loubet into Feilchenfeld and Chang.
An ordinary artisan would have been motivated to use the known technique of Loubet in the manner set forth above to produce the predictable results as stated above in claim 16.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Feilchenfeld in view of Kim (US 20220052156 A1).
Regarding claim 20, Feilchenfeld teaches claim 11 from which claim 20 depends. Feilchenfeld does not expressly disclose the limitations of claim 20.
However, in an analogous art, Kim teaches
wherein the gate structure (110 – Fig. 4B – [0087] – “gate electrode 110”)
comprises a gate dielectric layer (50 – Fig. 4B – [0087] – “gate dielectric layer 50”) and gate conductive layer (120 – Fig. 4B – [0115] – “gate silicide layer 120 is designed to be formed on the gate electrode 110”) over the gate dielectric layer (50), the gate dielectric layer (50) has opposite end surfaces, wherein a first one of the end surfaces of the gate dielectric layer (50) is covered by the first spacer (300 – Fig. 4C – [0114] – “first dielectric pattern 300” – this is interpreted as a gate spacer), and a second one of the end surfaces of the gate dielectric layer (50) is completely under the second spacer (310 – Fig. 4C – [0115] – “second dielectric pattern 310” – this is interpreted as a gate spacer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate aand gate dielectric structure as taught by Kim into Feilchenfeld.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable results to prevent [0004] – “when a high electric field such as ESD or EOS is formed, leakage current occurs between the gate electrode-drain electrode or the gate electrode-source electrode. To prevent this phenomenon, the distance between the gate electrode and the drain electrode is increased. Therefore, despite a high electric field due to ESD or EOS, leakage current between the gate electrode and the drain electrode may be blocked. However, in order to form a channel between the gate electrode and the source electrode, the source region and the gate electrode are disposed as close as possible. Due to this structure, when a high electric field is applied to the gate electrode, leakage current becomes a problem between the gate electrode and the source electrode region.”
Pertinent Art
For the benefits of the Applicant, US 20200350419 A1 and US20200044079 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the multi-layer spacer.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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