Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Specifically, “the second logic gate circuit comprising; a third logic function circuit coupled to the input signal line and further coupled between the first output terminal and a second header transistor, the third logic function circuit identical to the first logic function circuit; and a fourth logic function circuit coupled to the input signal line and further complementary to the first logic function circuit and coupled between the first output terminal and the reference voltage, the fourth logic function circuit identical to the second logic function circuit” recited in claims 1, 11, and 20 are not supported by the specification as originally filed.
Claims 2-10 and 12-19 are rejected based on their dependency on claims 1 and 11.
Response to Arguments
Applicant's arguments filed March 3, 2026 have been fully considered but they are not persuasive. Applicant stated at second paragraph on page 11 that “amended describe circuits in which … first logic function circuit comprising transistors 104 and 105 coupled between ground and the output 125 and the second logic function circuit comprising transistors 106 and 107 coupled between the output and the FET 111.” Examiner agrees. However, subject matter which was not described in the specification is the following: “the second logic gate circuit comprising: a third logic function circuit coupled to the input signal line and further coupled between the first output terminal and a second header transistor, the third logic function circuit identical to the first logic function circuit; and a fourth logic function circuit coupled to the input signal line and further complementary to the first logic function circuit and coupled between the first output terminal and the reference voltage, the fourth logic function circuit identical to the second logic function circuit”.
If the “the third logic function circuit” (transistors 118, 119, Fig. 1) is “identical to the first logic function circuit” (transistors 104, 105 as Applicant stated on page 11), the third logic function circuit should be coupled between the second output terminal (122, Fig. 1) and the reference voltage (110).
If the “the fourth logic function circuit” (transistors 118, 119, Fig. 1) is “identical to the second logic function circuit” (transistors 106, 107 as Applicant stated on page 11), the fourth logic function circuit should be coupled between the second output terminal (122, Fig. 1) and a second voltage rail (128, see Fig. 1). And the fourth logic function circuit should further complementary to the third logic function circuit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844