Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Application dated 7/30/2024.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim(s) 1-6, 8-10, 12-15, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suryanarayanan et al. (“Surya”), U.S. Patent Application No. 2015/0378412.
Regarding Claims 1 and 10, Surya teaches a method for voltage regulator noise mitigation with processor control, the method comprising:
monitoring a power consumption (as detecting power change or surge) of a sum of processor threads during thread pipeline execution [Para: 0013(as “one or more detectors may be utilized to identify an onset of power change (e.g., surge) that can result in voltage droop … instructions or micro-operations (μops) in a processor pipeline” where the “physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads”, see 0040)];
detecting a voltage regulator noise when the power consumption exceeds a slew power threshold [Para: 0017(occurrence of voltage droop) and 00125( where “ tracking logic 1610 may compare anticipated power consumption … to determine whether a high power event is in progress that can result in voltage droop … if a weighted sum of instructions (e.g., weighted according to power usage associated with each instruction) over a span of time reaches a threshold level”)]; and
controlling slew ramp-up steps of all the processor threads according to a selected throttle control [Para: 0126(“throttle memory instructions is sent to the memory” where throttle instructions comply with “instructions/ μops dispatch rates” see 0116, or slew rates)].
Regarding Claims 2 and 12, Suria teaches controlling the slew ramp-up steps comprises reducing instruction-issue to stall the slew ramp-up steps of the thread pipeline execution [Para: 0119(“mechanism to throttle instruction dispatch”) and 0126 (“throttle memory instructions”).
Regarding Claims 3 and 13, Suria teaches controlling the slew ramp-up steps comprises modulating the slew ramp-up steps from a lowest performance to a highest performance [Para: 0140(Power ramp-up” is related to higher performance C6 as described in para 0030, 0066)].
Regarding Claims 4 and 14, Surya teaches controlling the slew ramp-up steps comprises setting an inductor cool-off timer as the selected throttle control [Para: 0123(“as logic 1610 “tracking logic may cause the OOO 1604 to throttle flow of the instructions”) and 0125(“instruction tracking logic 1610 may signal to the out of order logic 1604 to throttle throughput of instructions”)].
Regarding Claims 5 and 15, Suria teaches controlling the slew ramp-up steps comprises accessing configuration register values to configure a slew-ramp control circuit [Para: 0119 (throttle instruction accessing memory based on classification where the classifications such as high power classification “condition under which throttling will occur … assigning a classification of one or more instruction to/from a high-power classification …” see 0128, suggests that these classifications are stored in a register for assisting throttle process)], .
Regarding Claim 6, Surya teaches the slew-ramp control circuit is integrated with a multi-threaded processor [Para: 0039(“FIG. 4, an embodiment of a processor including multiple cores” where the cores represent “cores or hardware threads” see para 0040].
Regarding Claims 8 and 18, Surya teaches controlling the slew ramp-up steps comprises feeding a throttle control signal to the thread pipeline execution to modulate the slew ramp-up steps from a lowest performance to a highest performance [Para: 0140(“ the reactive μop tracking logic 1716 can identify a power event (e.g., power ramp-up”) and 0143(“memory μop tracking logic 1760 may track memory μops to be executed in the cache 1750 and may detect a power event associated with a burst of memory traffic”)].
Regarding Claims 9 and 19, Surya teaches detecting the voltage regulator noise comprises detecting a load current ramp rate of the sum of the processor threads greater than the load current ramp rate specified by a power management integrated circuit (PMIC) [Para: 0017(occurrence of voltage droop) and 00125( where “ tracking logic 1610 may compare anticipated power consumption … to determine whether a high power event is in progress that can result in voltage droop … if a weighted sum of instructions (e.g., weighted according to power usage associated with each instruction) over a span of time reaches a threshold level”)].
Regarding Claim 20, Surya teaches the slew-ramp control circuit is integrated in a limits management hardware (LMH) [Para: 0123(as “1604 to throttle flow of the instructions until the high power instruction is executed …”)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 7, 11, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Surya as applies to Claim 1 above and Gurumurthi et al. (“Gurumurthi”), U.S. Patent Application Publication No. US 20210049446.
Regarding Claim 11, Surya teaches all limitations of claim 11 as described rejecting Claim 10 above. Surya does not disclose expressly the multi-threaded processor comprises a neural processor unit (NPU).
In the same field of endeavor (e.g., power control with respect to executing instructions), Huston teaches the multi-threaded processor comprises a neural processor unit (NPU) [Para: 0066 (“processors/cores/central processing units (CPUs), application-specific integrated circuit (ASIC) chips, neural network processors or accelerators, field-programmable gate arrays (FPGAs), compute units, embedded processors, graphics processors (GPUs)/graphics cores, pipelines”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Surya’s teachings of multithreaded processors with Gurumurti’s teachings of multi-threaded processor comprises a neural processor unit (NPU) for the purpose of faster evaluation and higher quality of training data for processing in the system in order to have an efficient system.
Regarding Claims 7 and 17, Surya teaches the slew-ramp control circuit configured with slew weights from the configuration register values [Para: 0125 and 0137]. One of ordinary skill in the art would utilize a control circuit comprises a programmable digital power meter (DPM) averaging circuit having a low pass filter as needed where low pass filters are very common the art for the purpose of fulfilling user requirement and achieving targeted/intended result.
Regarding Claim 16, since it is directly related to Claim 16 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claim 11 applies equally as well to Claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176