Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 2 is objected to because of the following informalities: “the first NS inverter and the second NS inverter of the clock buffer” should be changed to “the third NS inverter and the fourth NS inverter of the clock buffer”.
Claim Rejections - 35 USC § 101
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,199,612. For example, with respect to elements of claim 1 of the present application, the issued claim 1 discloses a primary latch, a second latch, and a clock buffer. As to the feature that (1) the primary latch, secondary latch, and clock buffer are each formed of transistors and (2) that the transistors are formed in active regions of a substrate, wherein transistors are formed of S/D doped regions, with channels regions between S/D doped regions, with gate lines over the channel regions, and with metal-to-S/D contact structures over the S/D doped regions, such features would have been obvious as discussed for claim 1 in Claim Rejections - 35 USC § 103 below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0108989 to Kang et al. (“Kang”).
With respect to claim 1, Kang discloses in Figs. 3-4 a semiconductor device comprising:
a cell region (e.g., Fig. 4A semiconductor layout) including active regions (e.g., a first region between 51 and 52 with transistors having a low threshold voltage according to Para. 60 and Figs. 3 and 4 which disclose that Low Vth (e.g., elements enclosed within the unevenlyly dotted line boxes) transistors of 10, 210, 310, and 30 are laid in the Low Vth voltage first region between 51 and 52 as shown in Fig. 4 and a second region between 52 and 53 with transistors having High Vth voltage according to Para. 60 and Figs. 3 and 4 which disclose that High Vth (e.g., elements with the evenly dotted line) transistors of 20, 220 and 320 are laid in the High Vth second region between 52 and 53) extend in a first direction (e.g., the left to right direction in Fig. 4A) and have components of transistors formed therein;
the transistors of the cell region (e.g., Fig. 4A semiconductor layout) being arranged to function as a D flip-flop (DFF) that includes a primary latch (e.g., 220), a secondary latch (e.g., 320) and a clock buffer (e.g., 10);
the primary latch (e.g., 220) including a first sleepy inverter (e.g., 222) and a first non-sleepy (NS) inverter (e.g., 221);
the secondary latch (e.g., 320) including a second sleepy inverter (e.g., 322) and a second NS inverter (e.g., 321); and
the clock buffer (e.g., 10) including third and fourth NS inverters (e.g., 11 and 12);
a first group (e.g., 220 and 320) of some but not all of the transistors having members which are configured with a standard (e.g., High Vth) threshold voltage (Vt_std members);
a second group (e.g., 10) of some but not all of the transistors having members which are configured with a low threshold voltage (e.g., Low Vth) that is lower than the standard (e.g., High Vth) threshold voltage (Vt_low members); and
ones (e.g., 10 with Low Vth) of the transistors which comprise at least one of the third NS inverter (e.g., 11) or the fourth NS inverter (e.g., 12) being Vt_low (e.g., Low Vth) members of the second group.
Kang does not specifically show in Figs. 3-4 that (1) the above discussed primary latch, secondary latch, and clock buffer are each formed of transistors and (2) that the transistors are formed in active regions of a substrate, wherein transistors are formed of S/D doped regions, with channels regions between S/D doped regions, with gate lines over the channel regions, and with metal-to-S/D contact structures over the S/D doped regions. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that (1) a primary latch, secondary latch, and clock buffer may each be formed of transistors and (2) the transistors may be formed in active regions of a substrate, wherein transistors are formed of S/D doped regions, with channels regions between S/D doped regions, with gate lines over the channel regions, and with metal-to-S/D contact structures over the S/D doped regions; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the above discussed primary latch, secondary latch, and clock buffer in Figs. 3-4 of Kang using the notoriously well-known method of (1) forming a primary latch, secondary latch, and clock buffer with transistors and (2) forming the transistors in active regions of a substrate, wherein transistors are formed of S/D doped regions, with channels regions between S/D doped regions, with gate lines over the channel regions, and with metal-to-S/D contact structures over the S/D doped regions because the Figs. 3-4 circuit of Kang requires a specific implementation in fabrication and the notoriously well-known method provides such a specific implementation.
With respect to claim 2, ones (e.g., 10) of the transistors which comprise the third NS inverter and the fourth NS inverter of the clock buffer (e.g., 10) are Vt_low (e.g., Low Vth) members of the second group.
With respect to claim 3, the DFF further includes an output buffer (e.g., 30); and ones (e.g., 30) of the transistors which comprise the output buffer are Vt_low (e.g., Low Vth as indicated by unevenly dotted lines for 30) members of the second group.
With respect to claim 8, the transistors of the cell region being further arranged to function as a scan-insertion type of DFF (SDFQ) that includes the DFF, a multiplexer (e.g., 111) and a scan buffer (e.g., 20 inverts and buffers SE to generate NSE which together with SE are used to control buffer 112 as shown in Figs. 5A-5B); and ones (e.g., 20) of the transistors which comprise the scan buffer (e.g., 20) are Vt_std (e.g., High Vth as indicated by the evenly dotted line for 20) members of the first group, wherein the multiplexer may be formed of transistors having the above discussed modification for claim 1. Further, the multiplexer (e.g., 112) are Vt_low (e.g., Low Vth as indicated by the unevenly dotted line) members of the second group.
With respect to claim 9, ones (e.g., 221 and 321) of the transistors which comprise the first NS inverter (e.g., 221) of the primary latch and the second NS inverter (e.g., 321) of the secondary latch are Vt_std (e.g., High Vth as indicated by the evenly dotted line) members of the first group.
With respect to claim 10, the Vt_low (e.g., Low Vth) members of the second group are in a first region, the Vt_std (e.g,. High Vth) members of the first group are in a second region (e.g., a first region between 51 and 52 with transistors having a low threshold voltage according to Para. 60 and Figs. 3 and 4 which disclose that Low Vth (e.g., elements enclosed within the unevenly dotted line boxes) transistors of 10, 210, 310, and 30 are laid in the Low Vth voltage first region between 51 and 52 as shown in Fig. 4 and a second region between 52 and 53 with transistors having Low Vth voltage according to Para. 60 and Figs. 3 and 4 which disclose that High Vth (e.g., elements enclosed within the evenly dotted line boxes) transistors of 20, 220 and 320 are laid in the High Vth second region between 52 and 53), a first type of gate is over channel regions in the first region, a second type of gate is over channel regions in the second region (e.g., Para. 54), and the first and second types of gates have different first and second work functions (e.g., Para. 131).
With respect to claims 11 and 15, the above discussion for claim 1 and its dependent claims similarly apply.
Allowable Subject Matter
Claims 4-7, 12-14, and 16-20 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the ground of nonstatutory obviousness-type double patenting is overcome.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842