DETAILED ACTION
The current Office Action is in response to the papers submitted 04/03/2026. Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 - 10 are objected to because of the following informalities:
Claim 1 is worded oddly to the examiner. It appears the phrase “stored and maintain” in line 11 should be “store and maintain”
All remaining claims are objected to for being dependent on an objected to base claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6, 11-12, 14, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Caraccio et al. (U.S. patent application publication 20220035701 A1), hereinafter referred to as Caraccio, in view of Miyazaki et al. (U.S. patent application publication 20110314234 A1), hereinafter referred to as Miyazaki.
Regarding claim 1, Caraccio teaches A memory module (“an interface between the host system 105 and the memory system 110 may support operations or communications according to a Compute Express Link (CXL) standard” [Caraccio paragraph 33]), comprising: a memory device (Caraccio memory system 110); and a controller (Caraccio memory system controller 155) including a non-volatile memory having stored thereon firmware instructions (“The memory system controller 155 may include the hardware, the firmware, or the instructions that enable the memory system 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory system 110.” [Caraccio paragraph 24], wherein including instructions would intrinsically require a non-volatile memory to store the instructions), wherein the instructions when executed by the controller cause the memory module to: determine that a post package repair (PPR) operation, associated with a memory row of the memory device (“In some examples, such maintenance operations may include performing a post-package repair on the memory die 200. For example, the memory die 200 may be configured to remap one or more addresses (e.g., rows, columns)” [Caraccio paragraph 51]), has been requested by a host device (“In some examples, a host system may initiate maintenance operations” [Caraccio abstract]. Furthermore, Caraccio Fig. 6 shows the controller 155 of memory system 110 initiating a PPR operation in response to a maintenance command (which is synonymous with a request) from the host device. Doing the PPR operation in response to the command would intrinsically require a determination of receipt of the command.) communicably coupled to the memory module (”A memory system may include a memory system controller for performing operations on the memory dies, and for interfacing with a host system coupled with the memory system” [Caraccio paragraph 11]).
Caraccio does not appear to explicitly disclose determine a location of a defective bit in the memory row in response to determining that the PPR operation has been requested; and stored and maintain, in the non-volatile memory, retired row data including an address of the memory row and the location of the defective bit for using the address of the memory row after the PPR operation while avoiding the location of the defective bit.
However, Miyazaki teaches determine a location of a defective bit in the memory row (“a write process for writing predetermined data to the first storage region; a check process for checking whether or not data written to the first storage region is correct; an information holding process for storing an association between an address of a defective cell in the first storage region, which has been determined to be defective in the check process…” [Miyazaki claim 6]. Wherein a memory cell stores a bit, so a defective cell is synonymous with a defective bit, and a memory row is a storage region) in response to determining that the PPR operation has been requested ([S4 – S5, Fig 3; S25 – S27, Fig 7] The steps of writing the address information of the defective bit locations is performed in response performing a PPR operation, such as steps S4 and S25. Performing steps S4 and S25 shows a request for the steps was received for the steps to be performed]; ; and stored and maintain, in the non-volatile memory, retired row data including an address of the memory row and the location of the defective bit (“storing an association between an address of a defective cell in the first storage region, which has been determined to be defective in the check process, and an address of an arbitrary memory cell in the second storage region as the address information in the information holder” [Miyazaki claim 6] and “wherein each of the first and second storage regions and the information holder includes a nonvolatile memory” [Miyazaki claim 3]. The association includes the address of the defective cell, which is a location of a defective bit, and a memory cell address further comprises the address of the row that the cell is located on. Therefore, the device of Miyazaki maintains data comprising the row address and defective bit location. Additionally, it is applicant admitted prior art to store defective row address information into a non-volatile memory (“The bit information relating to an address of the defective row and/or column can be programmed (stored) into non-volatile memory circuit” [paragraph 14 of the specification of the instant application, which describes typical prior art technology)) for using the address of the memory row after the PPR operation while avoiding the location of the defective bit (Each memory chip is considered a row of memory and each chip itself is comprised of rows and columns. When a row of memory is accessed only the defective bit locations are not accessed in a given row using the translation information to direct access from a defective bit location to a non-defective bit location [Paragraphs 0023 - 0026, 0042 – 0043, and 0051]).
Caraccio and Miyazaki are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio and Miyazaki before him or her, to modify the apparatus of Caraccio to include the attributes of determine a location of a defective bit in the memory row; and maintain, in the non-volatile memory, retired row data comprising an address of the memory row and the location of the defective bit of Miyazaki because it will enhance apparatus longevity.
The motivation for doing so would be determining defective regions of memory and storing the regions in non-volatile memory would enable the memory device to permanently prevent errors that occur after the device has been manufactured from reoccurring.
Therefore, it would have been obvious to combine Caraccio and Miyazaki to obtain the invention as specified in the instant claim.
Regarding claim 11, it is rejected under the same rationale as claim 1 above.
Regarding claim 16, it is rejected under the same rationale as claim 1 above, with the additional rationale that the memory device of Caraccio has rows and columns, making it a memory array.
Regarding claim 2, Caraccio/Miyazaki teach The memory module of claim 1, wherein determining the location of the defective bit in the memory row comprises: writing a write data pattern to the memory row; reading a read data pattern from the memory row; and comparing the write data pattern and read data pattern (“desired data is written to main memory regions 101a to 104a of the memory chips 101 to 104. The written data may be user data such as, for example, a computer program, text data, image data, and video data (step S3). … Then, the semiconductor memory device 1 to which data has been written is checked. In this check process, the data written in the previous step S3 is read and whether or not the read data is correct is determined. New defects of memory cells that have occurred through the assembly process, defects of memory cells that have been confirmed by reading user data, and the like are detected in this check process (step S4). Addresses of defective cells in the main memory regions 101a to 104a detected in this check process” [Miyazaki paragraphs 40-41]. Wherein step S3 comprises writing a write data pattern, step s4 comprises reading a read data pattern and checking (comparing) the read data, both steps intrinsically involve at least one memory row, and these steps would be capable of identify a location of a defective bit in a memory row).
Regarding claims 12 and 17, they are rejected under the same rationale as claim 2 above.
Regarding claim 4, Caraccio/Miyazaki teach The memory module of claim 1, wherein the retired row data comprises a mask (the “association between an address of a defective cell in the first storage region, which has been determined to be defective in the check process, and an address of an arbitrary memory cell in the second storage region” of Miyazaki claim 6 is a mask), and wherein the instructions cause the memory module to: generate the mask for the memory row based on the determined location of the defective bit in the memory row (“The memories 220a to 220d store address translation tables generated by the controller 210. The address translation tables represent associations between addresses of defective cells in the main memory regions 101a to 104a in the memory chips 101 to 104 and addresses of memory cells (substitute cells)” [Miyazaki paragraph 24]);
store data at the address of the memory row having the defective bit using the mask to avoid using the location of the defective bit; and
read the data from the address of the memory row having the defective bit using the mask to accurately recover the data and without accessing a value from the location of the defective bit (The translation table is used as a mask to direct accesses to the bits in the cell that are defective to other cells while still access the remaining locations in a given row of memory [Miyazaki Paragraphs 0023 - 0026, 0042 – 0043, 0046 – 0048, and 0051]).
Regarding claims 14 and 19, they are rejected under the same rationale as claim 4 above.
Regarding claim 6, Caraccio/Miyazaki teach The memory module of claim 1, wherein the memory device is a byte-addressable volatile or nonvolatile medium (Flash memory includes NOR flash memory which is byte addressable [Miyazaki Paragraph 0022].
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Berman et al. (U.S. patent application publication 20210019082 A1), hereinafter referred to as Berman.
Regarding claim 3, Caraccio/Miyazaki teach The memory module of claim 1, wherein the non-volatile memory further comprises instructions (see the rejection to claim 1 above).
Caraccio/Miyazaki do not appear to explicitly disclose that cause the memory module to: receive non-mission-critical data related to operation of at least one of the host device, the memory module, and the memory device; and store at least a part of the non-mission-critical data in the memory row for monitoring operation of the at least one of the host device, the memory module, and the memory device.
However, Berman teaches that cause the memory module to: receive non-mission-critical data related to operation of at least one of the host device, the memory module, and the memory device; and store at least a part of the non-mission-critical data in the memory row for monitoring operation of the at least one of the host device, the memory module, and the memory device (“upon determining that the written row is bad, writing the write data to a spare address in a spare region of the NVM; and writing the spare address to the bad row so the data can be accessed by referencing the bad row” [Berman paragraph 5]. Wherein the spare address is data related to operation of the memory device, and writing the spare address would involve receiving and storing it in the memory row. The spare address would be additionally non-mission-critical because Berman discloses a failsafe method in case there is an issue with the spare address data “The reading method then determines whether the decoding succeeded (step 660). For example, if the decoding succeeded, the decoding returns the spare address. If the decoding failed, in an exemplary embodiment, the logical address Laddr can be used to reference a mapping table to retrieve the spare address (step 690). In an embodiment, the mapping table is located in a DRAM external to memory 125” [Berman paragraph 44]. The spare address data could also be used for monitoring operation of the memory device, for example to easily observe where memory addresses are being remapped to).
Caraccio/Miyazaki and Berman are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio/Miyazaki and Berman before him or her, to modify the apparatus of Caraccio/Miyazaki to include the attributes of cause the memory module to: receive non-mission-critical data related to operation of at least one of the host device, the memory module, and the memory device; and store at least a part of the non-mission-critical data in the memory row for monitoring operation of the at least one of the host device, the memory module, and the memory device of Berman because it will reduce apparatus cost and increase apparatus longevity.
The motivation for doing so would be “the method is able to reuse a bad row to store the spare address without requiring a separate table in an extra expensive memory like DRAM. For example, instead of storing a mapping of the logical address Laddr to the spare address in this extra memory, the spare address is stored in the bad row. Thus, the life of the memory 126 can be greatly extended, the memory 126 can store more data (i.e., increased data capacity), and the cost of manufacturing (e.g., a PRAM device) can be greatly reduced” [Berman paragraph 37].
Therefore, it would have been obvious to combine Caraccio/Miyazaki and Berman to obtain the invention as specified in the instant claim.
Regarding claim 13, it is rejected under the same rationale as claim 3 above.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Fujisaki et al. (U.S. patent US 5410687 A), hereinafter referred to as Fujisaki.
Regarding claim 5, Caraccio/Miyazaki teach The memory module of claim 1, wherein the instructions cause the memory module to.
Caraccio/Miyazaki do not appear to explicitly disclose determine a number of defective bit locations in the memory row; and store the number of defective bit locations in the retired row data.
However, Fujisaki discloses determine a number of defective bit locations in the memory row; (“the number of failing cells on the row address line RA.sub.i and the number of failing cells on the column address line CA.sub.j in the memory area 11 are counted as indicated by RFC(i) and CFC(j) [Fujisaki col. 1 lines 45-48]” wherein counting the number of failing cells would be a determining of the number of defective bit locations) and store the number of defective bit locations in the retired row data (“the number of defective cells on each row address line of the memory under test is stored in the corresponding address of the RFC memory to provide the row address fail count RFC” [Fujisaki col. 4 lines 22-25]).
Caraccio/Miyazaki and Fujisaki are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio/Miyazaki and Fujisaki before him or her, to modify the apparatus of Caraccio/Miyazaki to include the attributes of determine a number of defective bit locations in the memory row; and store the number of defective bit locations in the retired row data of Fujisaki because it will enhance apparatus efficiency.
The motivation for doing so would be “failing addresses on the row side can be obtained from the fail counts CFC and RFC for the analysis blocks 11.sub.1 and 11.sub.2, by generating once the row addresses from 0 to the maximum address, while failing addresses on the column side can be obtained through parallel processing; therefore, the processing time can be reduced accordingly” [Fujisaki col. 15 lines 56-62].
Therefore, it would have been obvious to combine Caraccio/Miyazaki and Fujisaki to obtain the invention as specified in the instant claim.
Regarding claim 20, it is rejected under the same rationale as claim 5 above.
Claims 7 - 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Song (U.S. patent application publication 20140317338 A1), hereinafter referred to as Song ‘338.
Regarding claim 7, Caraccio/Miyazaki teach The memory module of claim 1 and determining the location of the defective bit (see the rejection to claim 1 above).
Caraccio/Miyazaki do not appear to explicitly disclose determining that the PPR operation has been requested is performed in a mission mode of operation, and determining the location of the defective bit is performed in a test mode of operation that is different from the mission mode.
However, Song ‘338 teaches determining that the PPR operation has been requested is performed in a mission mode of operation (“the operating method may include … entering a post package repair mode under the control of the memory controller, receiving an additional fail address from the memory controller, temporarily storing the additional fail address, programming the temporarily stored additional fail address in the programmable storage unit, and exiting from the post package repair mode under the control of the memory controller.” [Song ‘338 paragraph 22]. Wherein to enter a PPR mode, the device would have had to have been in a different mode (such as a mission mode) first, and the determination to enter the PPR mode would also be made in that different mode), and determining the location of the defective bit is performed in a test mode of operation that is different from the mission mode (the PPR mode of Song ‘338 would be the test mode, and determining the location of the defective bit would be performed as taught by the PPR operations of Caraccio/Miyazaki as explained above).
Caraccio/Miyazaki and Song ‘338 are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio/Miyazaki and Song ‘338 before him or her, to modify the apparatus of Caraccio/Miyazaki to include the attributes of determining that the PPR operation has been requested is performed in a mission mode of operation, and determining the location of the defective bit is performed in a test mode of operation that is different from the mission mode of Song ‘338 because it will enhance apparatus functionality.
The motivation for doing so would be that the apparatus of Song ‘338 can accurately track its capacity as it degrades (“According to the embodiments of the present invention, it may be possible to easily comprehend a remaining capacity available in the storage unit and store the repair information. Therefore, it may be possible to know how much repairing may be further performed. Further, it may be possible to obtain an advantage of easily designating a place in which additional repair information may be stored in the storage unit.” [Song ‘338 paragraph 66]). Therefore, a person having ordinary skill in the art would have been motivated to utilize the functions of Song ‘338.
Therefore, it would have been obvious to combine Caraccio/Miyazaki and Song ‘338 to obtain the invention as specified in the instant claim.
Regarding claim 8, Caraccio/Miyazaki further in view of Song ‘338 teaches The memory module of claim 1, wherein the instructions cause the memory module to: in response to determining that the PPR operation has been requested, switch from a mission mode of operation to a test mode of operation that is different from the mission mode (see the rejections to claims 1 and 7 above. Additionally, it would have been obvious to switch modes after a PPR operation request in view of Song ‘338’s requesting a PPR operation after switching modes as both orders achieve the same function/outcome regardless of the order).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Song (U.S. patent 5850512 A), hereinafter referred to as Song ‘512.
Regarding claim 9, Caraccio/Miyazaki teach The memory module of claim 1.
Caraccio/Miyazaki do not appear to explicitly disclose wherein determining the location of the defective bit comprises: writing 10 data patterns to the memory row; and reading the 10 data patterns from the memory row.
However, Song ‘512 discloses wherein determining the location of the defective bit comprises: writing 10 data patterns to the memory row; and reading the 10 data patterns from the memory row (“a test controller for controlling outputs of said plurality of test data patterns from said plurality of pattern registers to all signal lines of said system bus in response to information from said control register for comparison with said plurality of test data patterns read from said trace memory” [Song ‘512 claim 8]. The apparatus of Song ‘512 writes a plurality of data patterns, wherein a plurality could be 10 data patterns, and then reads the plurality of data patterns back from the trace memory for comparison. A person having ordinary skill in the art would recognize that this apparatus is capable of detecting a defective bit in the memory trace, for example, if upon comparison, a read value of a bit of the trace memory does not match value of the bit that was intended to be written).
Caraccio/Miyazaki and Song ‘512 are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio/Miyazaki and Song ‘512 before him or her, to modify the apparatus of Caraccio/Miyazaki to include the attributes of wherein determining the location of the defective bit comprises: writing 10 data patterns to the memory row; and reading the 10 data patterns from the memory row of Song ‘512 because it will enhance the effectiveness of the apparatus.
The motivation for doing so would be writing and reading a plurality of data patterns would increase the rigor of the memory cell/bit testing, increasing the likelihood of a defective cell/bit being detected, thus improving the ability of the memory device’s post package repair mechanisms to repair the device.
Therefore, it would have been obvious to combine Caraccio/Miyazaki and Song ‘512 to obtain the invention as specified in the instant claim.
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Bair et al. (U.S. patent 6065134 A), hereinafter referred to as Bair.
Regarding claim 10, Caraccio/Miyazaki teach The memory module of claim 1, wherein the instructions cause the memory module to.
Caraccio/Miyazaki do not appear to explicitly disclose determine a number of defective bit locations in the memory row; and determine whether the number of defective bit locations is less than a threshold number.
However, Bair teaches determine a number of defective bit locations in the memory row; and determine whether the number of defective bit locations is less than a threshold number (“repairing the ASIC memory array by selectively repairing a single memory row line in response to the determination that the number of defective cells along the memory row line exceeds the first threshold” [Bair claim 1]. Wherein a defective cell is a defective bit location.).
Caraccio/Miyazaki and Bair are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Caraccio/Miyazaki and Bair before him or her, to modify the apparatus of Caraccio/Miyazaki to include the attributes of determine a number of defective bit locations in the memory row; and determine whether the number of defective bit locations is less than a threshold number of Bair because it will enhance apparatus efficiency.
The motivation for doing so would be error correcting methods can typically account for a small number of defective/incorrect bits, so it would be inefficient to do a post package repair operation on every row containing a defective bit. Instead repairing only rows that have a larger threshold number of defective bits would reduce the number of post package repair operations performed, improving the efficiency of the memory device.
Therefore, it would have been obvious to combine Caraccio/Miyazaki and Bair to obtain the invention as specified in the instant claim.
Regarding claim 15, it is rejected under the same rationale as claim 10 above, with the additional rationale that Bair teaches "The threshold value of a mandatory-row repair" [col. 3 lines 20-21], and percentage is a value. Furthermore, since the threshold is for performing repair, being less than the threshold implies the row is acceptable for use, as a repair is not necessary. Therefore, it would have been obvious to store data in a row with a less than a percentage threshold of defects (such as the retired row data taught by Caraccio/Miyazaki).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Caraccio/Miyazaki, further in view of Berman, further in view of Song ‘338.
Regarding claim 18, it is rejected under the combined rationales of the rejections to claims 3 and 7 above.
A person having ordinary skill in the art would have been motivated to combine Caraccio/Miyazaki/Berman with Song ‘338 under the same motivation rationale as described in the rejection to claim 7 above.
Response to Arguments
Applicant's arguments filed 03/06/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 8 – 10 that claims 1 – 2, 4, 11 – 12, 14, 16 – 17, and 19 are allowable since Caraccio and Miyazaki fail to teach storage and maintenance of the retired row data in the nonvolatile memory within the controller. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The claims do not require the storing and maintaining of the retired row data to be in a non-volatile memory within the controller as argued. The claim discloses “stored and maintained, in the non-volatile memory of the controller, retired row data”. The non-volatile memory of the controller merely means the controller can interact with the memory, it does not have to mean the non-volatile memory is actually within the controller as argued. Any memory the controller can interact with is a memory of the controller. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the non-volatile memory being within the controller) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on pages 10 – 13 that all remaining dependent claims are allowable for being dependent on an independent claim above that has been argued allowable. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above showing how the prior art reads on the argued independent claims. The rejections of the remaining dependent claims are maintained based in part on the rejections of the independent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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