DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Pat. App. Pub. No. 2015/0116896) in view of JP 2019-4097.
With respect to claim 1, Inazuka teaches a multilayer ceramic capacitor (see abstract) comprising: a multilayer body including a plurality of dielectric layers that are laminated (see FIG. 2, elements 2 and 3, and paragraph [0033]), a first main surface and a second main surface opposed to each other in a lamination direction, a first lateral surface and a second lateral surface opposed to each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction (see FIG. 1 and paragraph [0041]); a plurality of first internal electrode layers each on a corresponding one of the plurality of dielectric layers and each exposed at the first end surface (see FIG. 2, elements 4 and paragraph [0033]); a plurality of second internal electrode layers each on a corresponding one of the plurality of dielectric layers and each exposed at the second end surface (see FIG. 2, elements 4 and paragraph [0033]); a first external electrode on the first end surface and connected to the plurality of first internal electrode layers (see FIG. 2, element 5a and paragraph [0032]); and a second external electrode on the second end surface and connected to the plurality of second internal electrode layers (see FIG. 2, element 5b and paragraph [0032]); wherein the multilayer body includes exposed portions each exposed from the first external electrode and the second external electrode (see FIG. 2, at least the top and bottom surfaces), first covered portions each covered by the first external electrode, and second covered portions each covered by the second external electrode (see FIG. 2); each of the plurality of first internal electrode layers includes a first counter portion opposed to a corresponding one of the plurality of second internal electrode layers and a first extension portion extending from the first counter portion toward the first end surface and exposed at the first end surface (see paragraph [0038], which teaches effective area 9, as well as extension portions 4c1 in FIG. 2); each of the plurality of second internal electrode layers includes a second counter portion opposed to a corresponding one of the plurality of first internal electrode layers and a second extension portion extending from the second counter portion toward the second end surface and exposed at the second end surface (see paragraph [0038], which teaches effective area 9, as well as extension portions 4c2 in FIG. 2); the first counter portion includes: a first region adjacent to the first end surface; a second region adjacent to the second end surface; and a first middle region between the first region and the second region (see FIG. 2, noting that the internal electrodes have regions adjacent both ends where the internal electrodes are angled and center region which is relatively flat); the second counter portion includes: a third region adjacent to the second end surface; a fourth region adjacent to the first end surface; and a second middle region between the third region and the fourth region (see FIG. 2, noting that the internal electrodes have regions adjacent both ends where the internal electrodes are angled and center region which is relatively flat); a dimension of the first middle region in the length direction is shorter than a distance between the first external electrode and the second external electrode (see FIG. 2); a dimension of the second middle region in the length direction is shorter than the distance between the first external electrode and the second external electrode (see FIG. 2); and a dimension in the lamination direction at a center of each of the exposed portions in the length direction is longer than a maximum distance in the lamination direction between surfaces adjacent to the first main surface and the second main surface of each of the first covered portions and the second covered portions, and shorter than a maximum distance in the lamination direction between a first main surface-side surface and a second main surface-side surface of each of the first external electrode and the second external electrode, the first main surface-side surface and the second main surface-side surface each functioning as an outermost surface and being exposed to outside (see FIG. 2, dimensions g1 and g2).
Inazuka fails to teach that a first middle region includes coverage higher than coverage of the first region and coverage of the second region and a second middle region includes coverage higher than coverage of the third region and coverage of the fourth region.
JP ‘097, on the other hand, teaches that a first middle region includes coverage higher than coverage of the first region and coverage of the second region and a second middle region includes coverage higher than coverage of the third region and coverage of the fourth region. See FIGS. 2 and 3, element 18a3. Such an arrangement results in improved heat dissipation. See paragraph [0036].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Inazuka, as taught by JP ‘097, to increase the coverage and thickness of the middle region of the internal electrodes in order to improve heat dissipation for the capacitor.
With respect to claim 2, the combined teachings of Inazuka and JP ‘097 teach that the first main surface includes a first exposed surface exposed from the first external electrode and the second external electrode, a first covered portion covered by the first external electrode, and a second covered surface covered by the second external electrode, and the first exposed surface includes a first flat surface parallel or substantially parallel to the lamination direction, a first sloped surface coupling the first flat surface and the first covered surface, and a second sloped surface coupling the first flat surface and the second covered surface. See FIG. 2, noting that at least a small portion of the first exposed surface will be flat between the sloped surfaces; the Office notes that the claim does not specify a dimension or relationship for the amount of first exposed surface that is flat.
With respect to claim 4, the combined teachings of Inazuka and JP ‘097 teach that a dimension of the multilayer body in the length direction is about 0.2 mm or more and about 6 mm or less; a dimension of the multilayer body in the lamination direction is about 0.05 mm or more and about 5 mm or less; and a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 5 mm or less. See Inazuka, paragraph [0117].
With respect to claim 5, the combined teachings of Inazuka and JP ‘097 teach that each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. See Inazuka, paragraph [0046].
With respect to claim 6, the combined teachings of Inazuka and JP ‘097 teach that each of the plurality of dielectric layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a secondary component. See Inazuka, paragraph [0046].
With respect to claim 7, the combined teachings of Inazuka and JP ‘097 teach that a thickness of each of the plurality of dielectric layers is about 0.2 μm or more and about 10 μm or less. See Inazuka, paragraph [0045].
With respect to claim 8, the combined teachings of Inazuka and JP ‘097 teach that a number of the plurality of dielectric layers is fifteen or more and 1200 or less. See Inazuka, paragraph [0052], noting that the number of dielectric layers would correspond to the number of internal electrode layers.
With respect to claim 9, the combined teachings of Inazuka and JP ‘097 teach that each of the plurality of first and second internal electrodes includes Ni, Cu, Ag, Pd or Au, or an alloy including at least one of Ni, Cu, Ag, Pd or Au. See Inazuka, paragraph [0051].
With respect to claim 10, the combined teachings of Inazuka and JP ‘097 teach that a thickness of each of the plurality of first and second internal electrodes is about 0.2 μm or more and about 2.0 μm or less. See Inazuka, paragraph [0053].
With respect to claim 11, the combined teachings of Inazuka and JP ‘097 teach that a number of the plurality of first and second internal electrodes is fifteen or more and 1000 or less. See Inazuka, paragraph [0052].
With respect to claim 12, the combined teachings of Inazuka and JP ‘097 teach that the first external electrode includes a first base electrode layer and a first plated layer; and the second external electrode includes a second base electrode layer and a second plated layer. See Inazuka, paragraph [0158].
With respect to claim 13, the combined teachings of Inazuka and JP ‘097 teach that each of the first and second base electrode layers is a fired layer including a metal component and a glass component or a ceramic component. See Inazuka, paragraph [0167].
With respect to claim 14, the combined teachings of Inazuka and JP ‘097 teach that the metal component is at least one of Cu, Ni, Ag, Pd, Ag-Pd alloys, or Au. See Inazuka, paragraph [0167].
With respect to claim 17, the combined teachings of Inazuka and JP ‘097 teach that each of the first and second plated layers includes at least one of Cu, Ni, Sn, Ag, Pd, a Ag-Pd alloy, or Au. See Inazuka, paragraph [0158].
With respect to claim 18, the combined teachings of Inazuka and JP ‘097 teach that each of the first and second plated layers includes a plurality of layers. See Inazuka, paragraph [0158].
With respect to claim 19, the combined teachings of Inazuka and JP ‘097 teach that each of the first and second plated layers has a two-layer structure including a Ni plated layer and a Sn plated layer on the Ni plated layer. See Inazuka, paragraph [0158].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Pat. App. Pub. No. 2015/0116896) in view of JP 2019-4097, and further, in view of Okuda (US Pat. App. Pub. No. 2021/0104364).
With respect to claim 3, the combined teachings of Inazuka and JP ‘097 fails to explicitly teach that a length of the first sloped surface in the length direction and a length of the second sloped surface in the length direction are shorter than a length of the first flat surface in the length direction.
Okuda, on the other hand, teaches that a length of the first sloped surface in the length direction and a length of the second sloped surface in the length direction are shorter than a length of the first flat surface in the length direction. See FIG. 2, the upper and lower exposed surface being completely flat, with short sloped covered surfaces; see also paragraph [0034]. Such an arrangement is known to help prevent moisture intrusion. See paragraph [0003].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify the combined teachings of Inazuka and JP ‘097, as taught by Okuda, in order to help prevent moisture intrusion.
Claims 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Pat. App. Pub. No. 2015/0116896) in view of JP 2019-4097, and further, in view of Katsube et al. (US Pat. App. Pub. No. 2023/0126382).
With respect to claim 15, the combined teachings of Inazuka and JP ‘097 fails to teach that the ceramic component includes at least one of BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, or CaZrO3.
Katsube, on the other hand, teaches that an external electrode base layer may include both a glass and ceramic component, the component including at least one of BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, or CaZrO3. See paragraphs [0121] and [0125]. Such an arrangement results in improved adhesion to the ceramic body. See paragraph [0120].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to further modify the combined teachings of Inazuka and JP ‘097, as taught by Katsube, in order to improve the adhesion to the ceramic body.
With respect to claim 16, the combined teachings of Inazuka and JP ‘097 fails to teach that a thickness of each of the first and second base electrode layers is about 3 μm or more and about 200 μm or less in a middle of the respective first and second base electrode layers.
Katsube, on the other hand, teaches that a thickness of each of the first and second base electrode layers is about 3 μm or more and about 200 μm or less in a middle of the respective first and second base electrode layers. See paragraph [0128]. Such an arrangement maintains the proper sizing for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to further modify the combined teachings of Inazuka and JP ‘097, as taught by Katsube, in order to maintain a proper sizing for the capacitor.
With respect to claim 20, the combined teachings of Inazuka and JP ‘097 fail to teach that a thickness of each of the Ni plated layer and the Sn plated layer is about 2 μm or more and about 10 μm or less.
Katsube, on the other hand, teaches that a thickness of each of the Ni plated layer and the Sn plated layer is about 2 μm or more and about 10 μm or less. See paragraph [0193]. Such an arrangement maintains the proper sizing for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to further modify the combined teachings of Inazuka and JP ‘097, as taught by Katsube, in order to maintain a proper sizing for the capacitor
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 8,335,072) and KR 10-2014-0041235 each teach a ceramic component having sloped upper surfaces.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2848