CTNF 18/789,810 CTNF 79656 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-14 have been presented for examination. Drawings 06-36-01 AIA Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 and 5-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al., A New Prediction Based Digital Control DC-DC Converter . A power conversion regulator circuit, comprising: a regulator input configured to be dynamically supplied with a feedback signal (e 0 / E eo /N eo ) representative of an output parameter of a power converter circuit [Figs. 1, 3; pg. 720]. The digital DC-DC buck converter of Fig. 1 is interpreted as the claimed power converter circuit. a regulator output configured to dynamically provide a control signal to the power converter circuit, for making adjustments to the output of the power converter circuit [Figs. 1, 3]; The output of the Digital Control Circuit is received by the Drive Circuit which naturally controls the duty cycle of the Digital buck DC-DC converter via MOSFET (Tr) which inherently adjusts the output of the buck converter. a processing circuit configured to (a) implement an artificial neural network configured to compute an error signal, based on at least the feedback signal and a target level for the output parameter, and (b) output a correction signal, based at least in part on the ML-based error signal [Eqn. 13; pgs. 721-722 cols. 2-1]; and regulator circuitry configured to generate the control signal for outputting via the regulator output, based at least in part on the correction signal [drive circuit Figs. 1, 3; pg. 721 col. 2]. In summary, Kurokawa teaches incorporating a neural network predictor in the digital buck converter control loop to predict fluctuations and improve transient response. It does this by feeding back the output e 0 into the Digital Control Circuit (DCC) which includes both a PID Controller (PIDC) and Neural Network Predictor (NNP). The output of the DCC is received by the Drive Circuit to control the duty cycle of the Buck converter thus controlling its output in response to the predictions. The PIDC and NNP together are interpreted as including both the claimed processing circuit and regulator circuitry. With respect to the PIDC and NNP working together, the NNP estimates the output voltage/feedback signal e 0 which is based on the monitored feedback signal e 0 and uses the estimated output voltage N e0 E st in its error determination along with a target level N R . The difference between these two values represents the error signal [Eqn. 13] used to determine the output N T0n [Eqn. 13] which is the basis for controlling the Drive Circuit and output of the digital buck converter. While Kurokawa teaches the invention substantially as claimed above, it is not explicitly taught that the PIDC/NNP combination comprises a plurality of artificial neurons for computing a ML based error signal. In other words, Kurokawa is silent with respect to the NNP including artificial neurons. The examiner is taking official notice that neural networks include artificial neurons in their architecture wherein the neurons (i.e., nodes) are weighted according to the neural networks training. Specifically, neural networks include a plurality of neurons in their input, output and hidden layers to configure how it and thus would have been obvious to one of ordinary skill in the art before the effective filing date to include in the NNP in Kurokawa so that the NNP can also operate as required. Referring to claim 5, Kurokawa teaches training using time series values of the feedback signal (i.e., [pgs. 721-22 cols. 2-1]. Referring to claim 6, Kurokawa teaches the e 0 signal is the output voltage [pg. 720 col. 2]. Referring to claim 7, Kurokawa teaches receiving a plurality of feedback signals (e o , e s and E i ) [Figs. 1, 3]. Referring to claim 8, while Kurokawa teaches the use of a neural network, it is not explicitly taught to implement at least a portion with analog artificial neurons. The examiner is taking official notice that analog artificial neurons are well known in the art and it would have been obvious to one of ordinary skill in the art before the effective filing date to use at least some analog artificial neurons in Kurokawa because it improves energy efficiency compared to digital neurons. Referring to claim 9, Kurokawa teaches a feedforward neural network [pg. 721 col. 2]. Referring to claims 10-14, while Kurokawa teaches using a neural network, it is not explicitly taught to implement the neural network as a dilated causal convolutional neural network (claim 10), a recurrent neural network (claim 11), that the neural network is a long short-term memory network and/or includes one or more gated recurrent units (claim 12), including an attention mechanism (claim 13), or the neural network includes any form of residual neural network architecture (claim 14). Rather, Kurokawa is silent as to the type of neural network being used. The examiner is taking official notice that each of those above are well known in the art and would have been obvious before the effective filing date to try including in the Kurokawa system because each have known benefits (i.e., dilated causal convolutional NN allows patterns to be learned with longer time dependencies; a recurrent/long short-term memory NN allows for processing of time series data as is present in Kurokawa; an attention mechanism to weigh more heavily more relevant parts of input data to utilize memory more efficiently; and residual NN can simplify training) and a person has rood reason to pursue the known options within his or her technical grasp and the application of the above network types would yield predictable results . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. REASONS FOR ALLOWANCE The prior art of record does not teach or suggest either individually or in combination, generating the correction signal by computing a weighted combination of the ML-based error signal and a value that represents a difference between the current state of the output and the target level (i.e., a non-ML-based error signal). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK A CONNOLLY whose telephone number is (571)272-3666. The examiner can normally be reached Monday-Friday 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached at 571-272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARK A CONNOLLY/Primary Examiner, Art Unit 2115 6/12/26 Application/Control Number: 18/789,810 Page 2 Art Unit: 2115 Application/Control Number: 18/789,810 Page 3 Art Unit: 2115 Application/Control Number: 18/789,810 Page 4 Art Unit: 2115 Application/Control Number: 18/789,810 Page 5 Art Unit: 2115 Application/Control Number: 18/789,810 Page 6 Art Unit: 2115 Application/Control Number: 18/789,810 Page 7 Art Unit: 2115
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