Prosecution Insights
Last updated: August 18, 2026
Application No. 18/789,816

ELECTRONIC COMPONENT AND MOUNTING STRUCTURE FOR ELECTRONIC COMPONENT

Final Rejection §102§103
Filed
Jul 31, 2024
Priority
Oct 28, 2022 — JP 2022-173005 +1 more
Examiner
SINCLAIR, DAVID M
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
861 granted / 1259 resolved
At TC average
Strong +20% interview lift
Without
With
+19.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
1296
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
13.2%
-26.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1259 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-4, & 6-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP08162357A hereafter referred to as Yoneda. In regards to claim 1, Yoneda discloses An electronic component, comprising: a component body (11 & 17 – fig. 1-2; [0026] & [0032]) with a length in a length direction; and a pair of external electrodes (13a & 13b – fig. 1-2; [0028]) at both ends of the component body, respectively, in the length direction; wherein the component body includes a protrusion (17) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes; the protrusion extends completely across the portion of the area exposed between the pair of external electrodes in the length direction and directly contacts the pair of external electrodes (seen in fig. 1-2); at least a portion of the pair of external electrodes is exposed from a material of the protrusion (seen in fig. 1-2); and the protrusion includes resin ([0032]). In regards to claim 3, Yoneda discloses The electronic component according to claim 1, wherein the protrusion is provided around an entire or substantially an entire outer periphery of the component body (seen in fig. 1-2). In regards to claim 4, Yoneda discloses The electronic component according to claim 1, wherein the component body includes a base body (11)including an internal electrode (12 – fig. 2; [0026]); and the protrusion is provided on a surface of the base body (seen in fig. 1-2). In regards to claim 6, Yoneda discloses The electronic component according to claim 1, wherein each of the pair of external electrodes includes a multilayer film including a sintered metal layer (14a/14b – fig. 2; [0029] & [0083]) and a plated layer (15a/15b/16a/16b – fig. 2; [0030-0031] & [0083]). In regards to claim 7, Yoneda discloses The electronic component according to claim 6, wherein the sintered metal layer includes Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au ([0029]). In regards to claim 8, Yoneda discloses The electronic component according to claim 6, wherein the plated layer includes a Ni plated layer (15a/15b) and a Sn plated layer (16a/16b) covering the Ni plated layer ([0030-0031]). In regards to claim 9, Yoneda discloses The electronic component according to claim 1, wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1-2). In regards to claim 10, Yoneda discloses The electronic component according to claim 1, wherein the component body includes a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternatively stacked in a lamination direction (fig. 2; [0026-0027]). In regards to claim 11, Yoneda discloses The electronic component according to claim 10, wherein each of the plurality of dielectric ceramic layers includes barium titanate ([0026]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda in view of JPH0533568U hereafter referred to as JP568. In regards to claim 2, Yoneda fails to disclose wherein the protrusion protrudes outwardly from the external electrodes by at least about 15 μm in the one direction. JP568 discloses that gap between the external electrodes and lands of a circuit board (i.e. the amount the protrusion protrudes outwardly from the external electrodes), is a result effective variable, particularly for reducing solder fatigue fracture ([0004]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the protrusion of Yoneda such the protrusion protrudes outwardly from the external electrodes by at least about 15 μm in the one direction in order to reduce solder fatigue fracture, as taught by JP568. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 1, 4-12, & 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa et al. (US 2015/0223334) in view of Nishikawa et al. (US 2005/0017373). In regards to claim 1, Nakagawa ‘334 discloses an electronic component, comprising: a component body (11 – fig. 1-2; [0050]) with a length in a length direction; and a pair of external electrodes (15 & 16 – fig. 1-2; [0050]) at both ends of the component body, respectively, in the length direction. Nakagawa ‘334 fails to disclose the component body includes a protrusion protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes; the protrusion extends completely across the portion of the area exposed between the pair of external electrodes in the length direction and directly contacts the pair of external electrodes; at least a portion of the pair of external electrodes is exposed from a material of the protrusion; and the protrusion includes resin. Nishikawa ‘373 discloses an electronic component, comprising: a component body (32 & 6 – fig. 1; [0037-0038]) with a length in a length direction; and a pair of external electrodes (34 – fig. 1; [0038]) at both ends of the component body, respectively, in the length direction; wherein the component body includes a protrusion (6) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes; the protrusion extends completely across the portion of the area exposed between the pair of external electrodes in the length direction and directly contacts the pair of external electrodes (fig. 1); at least a portion of the pair of external electrodes is exposed from a material of the protrusion (fig. 1); and the protrusion includes resin ([0048]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a protruding portion as taught by Nishikawa ‘373 with the capacitor of Nakagawa ‘334 to improve shearing strength. In regards to claim 4, Nakagawa ‘334 as modified by J Nishikawa ‘373 further discloses wherein the component body includes a base body including an internal electrode (13 – fig. 2; [0051] of Nakagawa ‘334); the protrusion is provided on a surface of the base body (fig. 1 of Nishikawa ‘373). In regards to claim 5, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein dimensions of the electronic component are between about 0.2 mm and about 1.2 mm inclusive in the length direction, between about 0.1 mm and about 0.7 mm inclusive in a width direction, and between and about 0.1 mm and about 0.7 mm inclusive in a lamination direction ([0069] of Nakagawa ‘334). In regards to claim 6, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein each of the pair of external electrodes includes a multilayer film including a sintered metal layer and a plated layer ([0056] of Nakagawa ‘334). In regards to claim 7, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the sintered metal layer includes Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au ([0056] of Nakagawa ‘334). In regards to claim 8, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the plated layer includes a Ni plated layer and a Sn plated layer covering the Ni plated layer ([0056] of Nakagawa ‘334). In regards to claim 9, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1-2 of Nakagawa ‘334). In regards to claim 10, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the component body includes a plurality of dielectric ceramic layers (12 – fig. 2; [0051] of Nakagawa ‘334) and a plurality of internal electrode layers (13 – fig. 2; [0051] of Nakagawa ‘334) alternatively stacked in a lamination direction. In regards to claim 11, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein each of the plurality of dielectric ceramic layers includes barium titanate ([0051] of Nakagawa ‘334). In regards to claim 12, Nakagawa ‘334 discloses a mounting structure for an electronic component comprising: a pair of external electrodes (15 & 16 – fig. 1-2; [0050]) respectively connected to a pair of lands (25 & 26 – fig. 4-5 & 7; [0065]) spaced apart on a surface of a board (20A – fig. 7; [0072]); wherein the electronic component includes a component body (11 – fig. 1-2; [0050]) with a length in a length direction and the pair of external electrodes provided on the component body; and the component body is in contact with the board, and a gap is provided between each of the pair of external electrodes and the board (seen in fig. 7 – solder is between the external electrodes and lands thus forming a gap) a gap is provided between each of the pair of external electrodes and the board (seen in fig. 7 – solder is between the external electrodes and lands thus forming a gap). Nakagawa ‘334 fails to disclose the component body includes a protrusion protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes, the component body is in contact with the board, and the protrusion extends completely across the portion of the area exposed between the pair of external electrodes in the length direction and directly contacts the pair of external electrodes; at least a portion of the pair of external electrodes is exposed from a material of the protrusion; and the protrusion includes resin Nishikawa ‘373 discloses a mounting structure for an electronic component comprising: a pair of external electrodes (34 – fig. 1; [0038]) respectively connected to a pair of lands (2 – fig. 1; [0035]) spaced apart on a surface of a board (1 – fig. 1; [0035]); wherein the electronic component includes a component body with a length in a length direction and the pair of external electrodes provided on the component body; and the component body (32 & 6 – fig. 1; [0037-0038]) includes a protrusion (6) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes; the component body is in contact with the board, and a gap is provided between each of the pair of external electrodes and the board (fig. 1); the protrusion extends completely across the portion of the area exposed between the pair of external electrodes in the length direction and directly contacts the pair of external electrodes (fig. 1); at least a portion of the pair of external electrodes is exposed from a material of the protrusion (fig. 1); and the protrusion includes resin ([0048]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a protruding portion as taught by Nishikawa ‘373 with the capacitor of Nakagawa ‘334 to improve shearing strength. In regards to claim 15, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein dimensions of the electronic component are between about 0.2 mm and about 1.2 mm inclusive in the length direction, between about 0.1 mm and about 0.7 mm inclusive in a width direction, and between and about 0.1 mm and about 0.7 mm inclusive in a lamination direction ([0069] of Nakagawa ‘334). In regards to claim 16, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein each of the pair of external electrodes includes a multilayer film including a sintered metal layer and a plated layer ([0056] of Nakagawa ‘334). In regards to claim 17, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the sintered metal layer includes Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au ([0056] of Nakagawa ‘334). In regards to claim 18, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the plated layer includes a Ni plated layer and a Sn plated layer covering the Ni plated layer ([0056] of Nakagawa ‘334). In regards to claim 19, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1-2 of Nakagawa ‘334). In regards to claim 20, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the component body includes a plurality of dielectric ceramic layers (12 – fig. 2; [0051] of Nakagawa ‘334) and a plurality of internal electrode layers (13 – fig. 2; [0051] of Nakagawa ‘334) alternatively stacked in a lamination direction. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa ‘334 as modified by Nishikawa ‘373 as applied to claim 12 above, and further in view of JP568. In regards to claim 13, Nakagawa ‘334 as modified by Nishikawa ‘373 fails to disclose wherein the gap is at least about 15 µm. JP568 discloses that gap between the external electrodes and lands of a circuit board, is a result effective variable, particularly for reducing solder fatigue fracture ([0004]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakagawa ‘334 as modified by Nishikawa ‘373 such that the gap is at least about 15 µm in order to reduce solder fatigue fracture, as taught by JP568. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa ‘334 as modified by Nishikawa ‘373 as applied to claim 12 above, and further in view of JPS5966189A hereafter referred to as Nishimura. In regards to claim 14, Nakagawa ‘334 as modified by Nishikawa ‘373 further discloses wherein the board includes a fiber orientation extending in one direction ([0073]). Nakagawa ‘334 as modified by Nishikawa ‘373 fails to explixtly disclose the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation. Nishimura discloses the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation (fig. 1; [0001]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakagawa ‘334 as modified by Nishikawa ‘373 such the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation as taught by Nishimura to reduce the stress on the electronic component. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 6,915,944 – fig. 1 Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David M Sinclair/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Jul 31, 2024
Application Filed
Feb 17, 2026
Non-Final Rejection mailed — §102, §103
Apr 16, 2026
Interview Requested
Apr 23, 2026
Examiner Interview Summary
Apr 23, 2026
Applicant Interview (Telephonic)
May 13, 2026
Response Filed
May 29, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
88%
With Interview (+19.9%)
2y 6m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1259 resolved cases by this examiner. Grant probability derived from career allowance rate.

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