DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, & 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US 2016/0268047).
In regards to claim 1, Shin ‘047 discloses
An electronic component, comprising:
a component body (110 & 115 – fig. 2; [0026]) with a length in a length direction; and
a pair of external electrodes (122 & 124 – fig. 1 & 3; [0026]) at both ends of the component body, respectively, in the length direction; wherein
the component body includes a protrusion (115 – fig. 2-3; [0026]) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes.
In regards to claim 3, Shin ‘047 discloses
The electronic component according to claim 1, wherein the protrusion is provided around an entire or substantially an entire outer periphery of the component body (fig. 1-3).
In regards to claim 4, Shin ‘047 discloses
The electronic component according to claim 1, wherein the component body includes a base body (120) including an internal electrode (114 & 116 – fig. 2; [0026]);
the protrusion is provided on a surface of the base body (fig. 2-3); and
the protrusion includes at least one of ceramic and resin ([0026]).
In regards to claim 9, Shin ‘047 discloses
The electronic component according to claim 1, wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1 & 3).
In regards to claim 10, Shin ‘047 discloses
The electronic component according to claim 1, wherein the component body includes a plurality of dielectric ceramic layers (112 – fig. 2; [0030]) and a plurality of internal electrode layers (114 & 116 – fig. 2; [0026]) alternatively stacked in a lamination direction.
Claim(s) 12 & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2000252606A hereafter referred to as Kubota.
In regards to claim 12, Kubota discloses
A mounting structure for an electronic component comprising:
a pair of external electrodes (3 & 4 – fig. 1; [0016]) respectively connected to a pair of lands (8 & 9 – fig. 1; [0018]) spaced apart on a surface of a board (7 – fig. 1; [0018]); wherein
the electronic component includes a component body (2 & 10 – fig. 1; [0016] & [0019]) and the pair of external electrodes provided on the component body; and
the component body is in contact with the board (fig. 1; [0019]), and
a gap is provided between each of the pair of external electrodes and the board (fig. 1).
In regards to claim 20, Kubota discloses
The mounting structure according to claim 12, wherein the component body includes a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternatively stacked in a lamination direction ([0016]).
Claim(s) 1-2, 4, 10, 12-13, & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peters (US 2021/0212200).
In regards to claim 1, Peters ‘200 discloses
An electronic component, comprising:
a component body (104 & 108 – fig. 1; [0018] & [0025]) with a length in a length direction; and
a pair of external electrodes (130 & 132 – fig. 1; [0023]) at both ends of the component body, respectively, in the length direction; wherein
the component body includes a protrusion (108 – fig. 1) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes.
In regards to claim 2, Peters ‘200 discloses
The electronic component according to claim 1, wherein the protrusion protrudes outwardly from the external electrodes by at least about 15 μm in the one direction ([0025]).
In regards to claim 4, Peters ‘200 discloses
The electronic component according to claim 1, wherein the component body includes a base body (104 – fig. 1) including an internal electrode (fig. 1; [0023]);
the protrusion is provided on a surface of the base body (fig. 1); and
the protrusion includes at least one of ceramic and resin ([0026]).
In regards to claim 10, Peters ‘200 discloses
The electronic component according to claim 1, wherein the component body includes a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternatively stacked in a lamination direction (fig. 1; [0023]).
In regards to claim 12, Peters ‘200 discloses
A mounting structure for an electronic component comprising:
a pair of external electrodes (130 & 132 – fig. 1; [0023]) respectively connected to a pair of lands spaced apart on a surface of a board; wherein
the electronic component includes a component body (104 & 108 – fig. 1; [0018] & [0025]) and the pair of external electrodes provided on the component body; and
the component body is in contact with the board (fig. 1), and
a gap is provided between each of the pair of external electrodes and the board (fig. 1).
In regards to claim 13, Peters ‘200 discloses
The mounting structure according to claim 12, wherein the gap is at least about 15 μm ([0025]).
In regards to claim 20, Peters ‘200 discloses
The mounting structure according to claim 12, wherein the component body includes a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternatively stacked in a lamination direction(fig. 1; [0023]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 13, & 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa et al. (US 2015/0223334) in view of JPH0533568U hereafter referred to as JP568.
In regards to claim 1,
Nakagawa ‘334 discloses an electronic component, comprising:
a component body (11 – fig. 1-2; [0050]) with a length in a length direction; and
a pair of external electrodes (15 & 16 – fig. 1-2; [0050]) at both ends of the component body, respectively, in the length direction. Nakagawa ‘334 fails to disclose the component body includes a protrusion protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes.
JP’568 discloses an electronic component, comprising: a component body (3 & 6 or 3 alone – fig. 1-2; [0008-0009) with a length in a length direction; and
a pair of external electrodes (4 – fig. 1-2) at both ends of the component body, respectively, in the length direction; wherein
the component body includes a protrusion (6 – fig. 1 or protruding portion of 3 – fig. 2) protruding outwardly beyond the pair of external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a protruding portion as taught by JP’568 with the capacitor of Nakagawa ‘334 to improve the solder connection between the component and circuit board by reducing fatigue fracture.
In regards to claim 2,
Nakagawa ‘334 as modified by JP568 disclose all the claimed limitations discussed above with respect to claim 2, except for wherein the protrusion protrudes outwardly from the external electrodes by at least about 15 μm in the one direction. However, JP568 discloses that gap between the external electrodes and lands of a circuit board (i.e. the amount the protrusion protrudes outwardly from the external electrodes), is a result effective variable, particularly for reducing solder fatigue fracture ([0004]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakagawa ‘334 as modified by JP568 such the protrusion protrudes outwardly from the external electrodes by at least about 15 μm in the one direction in order to reduce solder fatigue fracture, as taught by JP568. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 4,
Nakagawa ‘334 as modified by JP568 further discloses wherein the component body includes a base body including an internal electrode (13 – fig. 2; [0051] of Nakagawa ‘334);
the protrusion is provided on a surface of the base body (fig. 2 of JP568); and
the protrusion includes at least one of ceramic and resin ([0051] of Nakagawa ‘334 & fig. 2 of JP568 – protrusion is formed of same material as base body).
In regards to claim 5,
Nakagawa ‘334 as modified by JP568 further discloses wherein dimensions of the electronic component are between about 0.2 mm and about 1.2 mm inclusive in the length direction, between about 0.1 mm and about 0.7 mm inclusive in a width direction, and between and about 0.1 mm and about 0.7 mm inclusive in a lamination direction ([0069] of Nakagawa ‘334).
In regards to claim 6,
Nakagawa ‘334 as modified by JP568 further discloses wherein each of the pair of external electrodes includes a multilayer film including a sintered metal layer and a plated layer ([0056] of Nakagawa ‘334).
In regards to claim 7,
Nakagawa ‘334 as modified by JP568 further discloses wherein the sintered metal layer includes Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au ([0056] of Nakagawa ‘334).
In regards to claim 8,
Nakagawa ‘334 as modified by JP568 further discloses wherein the plated layer includes a Ni plated layer and a Sn plated layer covering the Ni plated layer ([0056] of Nakagawa ‘334).
In regards to claim 9,
Nakagawa ‘334 as modified by JP568 further discloses wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1-2 of Nakagawa ‘334).
In regards to claim 10,
Nakagawa ‘334 as modified by JP568 further discloses wherein the component body includes a plurality of dielectric ceramic layers (12 – fig. 2; [0051] of Nakagawa ‘334) and a plurality of internal electrode layers (13 – fig. 2; [0051] of Nakagawa ‘334) alternatively stacked in a lamination direction.
In regards to claim 11,
Nakagawa ‘334 as modified by JP568 further discloses wherein each of the plurality of dielectric ceramic layers includes barium titanate ([0051] of Nakagawa ‘334).
In regards to claim 12,
Nakagawa ‘334 discloses a mounting structure for an electronic component comprising:
a pair of external electrodes (15 & 16 – fig. 1-2; [0050]) respectively connected to a pair of lands (25 & 26 – fig. 4-5 & 7; [0065]) spaced apart on a surface of a board (20A – fig. 7; [0072]); wherein
the electronic component includes a component body (11 – fig. 1-2; [0050]) and the pair of external electrodes provided on the component body,
a gap is provided between each of the pair of external electrodes and the board (seen in fig. 7 – solder is between the external electrodes and lands thus forming a gap). Nakagawa ‘334 fails to disclose the component body is in contact with the board, and a gap is provided between each of the pair of external electrodes and the board.
JP’568 discloses a mounting structure for an electronic component comprising:
a pair of external electrodes (4 – fig. 1-2) respectively connected to a pair of lands (2 – fig. 1-2) spaced apart on a surface of a board (1 – fig. 1-2); wherein
the electronic component includes a component body (3 & 6 or 3 alone – fig. 1-2; [0008-0009) and the pair of external electrodes provided on the component body; and
the component body is in contact with the board (fig. 1-2), and
a gap is provided between each of the pair of external electrodes and the board (fig. 1-2).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a protruding portion as taught by JP’568 with the capacitor of Nakagawa ‘334 to improve the solder connection between the component and circuit board by reducing fatigue fracture.
In regards to claim 13,
Nakagawa ‘334 as modified by JP568 disclose all the claimed limitations discussed above with respect to claim 2, except for wherein the gap is at least about 15 μm. However, JP568 discloses that gap between the external electrodes and lands of a circuit board, is a result effective variable, particularly for reducing solder fatigue fracture ([0004]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakagawa ‘334 as modified by JP568 such the gap is at least about 15 μm in the one direction in order to reduce solder fatigue fracture, as taught by JP568. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 15,
Nakagawa ‘334 as modified by JP568 further discloses wherein dimensions of the electronic component are between about 0.2 mm and about 1.2 mm inclusive in the length direction, between about 0.1 mm and about 0.7 mm inclusive in a width direction, and between and about 0.1 mm and about 0.7 mm inclusive in a lamination direction ([0069] of Nakagawa ‘334).
In regards to claim 16,
Nakagawa ‘334 as modified by JP568 further discloses wherein each of the pair of external electrodes includes a multilayer film including a sintered metal layer and a plated layer ([0056] of Nakagawa ‘334).
In regards to claim 17,
Nakagawa ‘334 as modified by JP568 further discloses wherein the sintered metal layer includes Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au ([0056] of Nakagawa ‘334).
In regards to claim 18,
Nakagawa ‘334 as modified by JP568 further discloses wherein the plated layer includes a Ni plated layer and a Sn plated layer covering the Ni plated layer ([0056] of Nakagawa ‘334).
In regards to claim 19,
Nakagawa ‘334 as modified by JP568 further discloses wherein each of the pair of external electrodes extends from the respective end surface of the component body to lateral side surfaces and main side surfaces of the component body (fig. 1-2 of Nakagawa ‘334).
In regards to claim 20,
Nakagawa ‘334 as modified by JP568 further discloses wherein the component body includes a plurality of dielectric ceramic layers (12 – fig. 2; [0051] of Nakagawa ‘334) and a plurality of internal electrode layers (13 – fig. 2; [0051] of Nakagawa ‘334) alternatively stacked in a lamination direction.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa ‘334 as modified by JP568 as applied to claim 12 above, and further in view of JPS5966189A hereafter referred to as Nishimura.
In regards to claim 14,
Nakagawa ‘334 as modified by JP568 further discloses wherein the board includes a fiber orientation extending in one direction ([0073]). Nakagawa ‘334 as modified by JP568 fails to explixtly disclose the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation.
Nishimura discloses the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation (fig. 1; [0001]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakagawa ‘334 as modified by JP568 such the electronic component is arranged such that a direction in which the pair of external electrodes are spaced apart from each other is parallel or substantially parallel to the fiber orientation as taught by Nishimura to reduce the stress on the electronic component.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JPS59041888A – fig. 2 US 2021/0065988 – fig. 4-5
US 2017/0352485 – fig. 4 US 2023/0207220 – fig. 3
US 4,750,084 – fig. 10
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2848