Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on January 23rd, 2026. Claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/23/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Ganapathy et al. (USPGPUB No. 2013/0138877 A1, hereinafter referred to as Ganapathy) in view of Raval et al. (USPGPUB No. 2022/0206942 A1, hereinafter referred to as Raval) and further in view of Ansari (USPGPUB No. 2024/0394216 A1) and further in view of Iyer et al. (USPGPUB No. 2025/0086129, hereinafter referred to as Iyer).
Referring to claim 1, Ganapathy discloses a direct memory access (DMA) device router of a system-on-chip (SoC), {“system on a chip” (see Fig. 1 [0018]) with “address lines used by the bus to perform DMA transfers” ([0020], 1st sentence)}, the logic comprising:
a plurality of action groups {“DMA [action groups] descriptor registers”, see Fig. 3 [0030], 2nd sentence} and each configured with at least one DMA action {“instructions for DMA transfer [actions]… start, stop, continue, suspend, and resume”, see Fig. 3 [0030] 1st sentence};
a plurality of interrupt inputs {“programmed I/O, interrupt driven I/O,” (see Fig. 1 [0003], 2nd sentence; “DMA data transfer were more efficient than either programmed I/O or interrupt driven I/O methods”, [0004]};
a logic to initiate {“that couples to [logic] bus arbitrator 201A.”, see Fig. 2, [0023], last sentence} a transfer using a selected channel {a transfer using “multi-channel serial port 206 includes”, see Fig. 2 [0023] last sentence} of a selected DMA controller {“serial DMA controller 207 [and 203a-203n]”, see Fig. 2 [0023] last sentence} for at least one DMA action listed in an action group associated {“control logic 808 includes logic to provide data flow control and to provide DMA control structures [listed]… as queue handles” as claimed, see Fig. 8 [0050], 3rd and 4th sentences} with a corresponding one of the plurality of interrupt inputs triggered by assertion {“[host DMA controller 215] status/control register 807… provide access to control and status information to an external host and status notification” outputs serve as inputs to respective logic “bus arbitrator 201a” and each “core DMA controller 203a-203N” (see Figs. 2 and 8 [0050], 5th sentence)} of a corresponding interrupt signal {“core logic 808” providing at least two corresponding interrupts “INT BUS” and “INT HOST”(see Fig. 8, [0050], 9th and 10th sentences};
Ganapathy does not appear to explicitly disclose a plurality of interrupt inputs, each configured to receive a corresponding one of a plurality of interrupt signals;
a plurality of action groups, each associated with a corresponding one of the plurality of interrupt inputs and each configured with at least one DMA action;
wherein each DMA action is configured to select one of a plurality of DMA controllers and to select a channel of the selected DMA controller;
wherein the logic is a DMA router engine configured to initiate a transfer using a selected channel of a selected DMA controller for at least one DMA action listed in an action group associated with a corresponding one of the plurality of interrupt inputs triggered by assertion of a corresponding interrupt signal.
However, Raval discloses a plurality of interrupt inputs {“[plurality of interrupt inputs] registers for controlling if GA Logs triggered by SDXI engine AVIC interrupts to the particular context DTE” (see Figs. 1 and 2, [0029] last sentence}, each configured to receive a corresponding one of a plurality of interrupt signals {“DTE segments supported by the particular IOMMU context” that includes RTE table and interrupts “IOMMU will use DTE and IRTE structures from requested IOMMU context to service interrupts” (see Fig. 3 [0053])};
a plurality of action groups {“including re-fetching DTE”, “implement a DTE IGNORE bit” to name a few, see Fig. 3 [0056]}, each associated with a corresponding one of the plurality of interrupt inputs {“an interrupt remapping table, which the IOMMU uses”, see Fig. 3 [0020]} and each configured with at least one DMA action {“provide permission checking and interrupt remapping for peripheral component endpoints interrupts”, see Fig. 3 [0020]};
wherein each DMA action is configured to select one of a plurality of DMA controllers {“SDXI engines 204a and 204b including DMA engines 240A and 240B,”, see Fig. 2 [0036]} and to select a channel of the selected DMA controller {“SDXI engines can require communicating over a physical channel… connected through cable or interconnect”, see Fig. 3 [0020]};
wherein the logic is a DMA router engine configured to initiate a transfer {“[DMA router] IOMMU can process memory transactions that are routed” including “IOMMU provides address translation and page protection for DMA” (both cited in [0021], see Fig. 1)} using a selected channel {“[channel] grouping of SDXI engines can include a collection of interconnected instances referred to as a function group”, see Fig. 1 [0017]; another example “multiple [channel] links and buses to peripheral component endpoints, multiple IOMMUs ensure that each I/O link or bus has appropriate protection and translation”, see Fig. 1, [0021], last sentence} of a selected DMA controller {“[selected controller SDXI engine] DMA port 114 facilitates DMA transactions that have already been translated.”, see Fig. [0024] 1st sentence} for at least one DMA action listed in an action group {“Work queue 120 is used for executing operations, along with all associated memory data structures such as control and status information”, see Fig. 1 [0024], 2nd sentence} associated with a corresponding one of the plurality of interrupt inputs {“[plurality of interrupt inputs] registers for controlling if GA Logs triggered by SDXI engine AVIC interrupts to the particular context”, see Fig. 1 [0029] last sentence} triggered by assertion of a corresponding interrupt signal {“When the IOMMU detects an event of any kind [including interrupt(s)], event logger 124 writes an appropriate event entry into the event log located in system memory”, see Fig. 1 [0024], last three sentences}.
Ganapathy and Raval are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganapathy and Raval before him or her, to modify Dalal’s “HOPLITE router 300” incorporating Raval’ “weightage-based scheduling schemes” (see Fig. 3, [0033]).
The suggestion/motivation for doing so would have been to implement a count indicating a number of input ports of the input group arbiter having queued data packets targeting the set of output ports (Raval [0002]).
Therefore, it would have been obvious to combine Raval with Ganapathy to obtain the invention as specified in the instant claim(s).
Neither Ganapathy or Raval appears to explicitly disclose wherein the SOC having a plurality of DMA controllers distributed among multiple device groups of the SoC, the DMA router wherein the logic is a DMA router engine configured to initiate a transfer each configured to receive a corresponding one of a plurality of interrupt signals;
a plurality of action groups, each associated with a corresponding one of the plurality of interrupt inputs and each configured with a corresponding plurality of DMA actions;
and a DMA router engine configured to initiate DMA transfers of a DMA, wherein each DMA action of the corresponding plurality of DMA actions of the action group is configured to indicate:
a selected DMA controller of the plurality of DMA controllers of the SoC and a selected DMA channel of the plurality of corresponding DMA channels within the selected DMA controller to perform a corresponding DMA transfer, wherein at least two DMA actions of the action group perform corresponding DMA transfers by selected DMA controllers located in different device groups of the SoC;
wherein each DMA controller includes a plurality of corresponding DMA channels;
Furthermore, Ansari discloses wherein the SOC having a plurality of DMA controllers {see Fig. 7, plurality of DMA controllers “distributed management circuitry 703-1 through 703-n”, see Fig. 7, [0096]} distributed among multiple device groups {different device groups in hierarchy “NPI root bridge 746 and a NPI switch 748 to permit CIM circuit 704-1 to access LCI circuitry 738”, see Fig. 7, [0108], last two sentences} of the SoC, the DMA router comprising:
a DMA router engine {“stream circuit routes” (see Fig. 5, 0090], 2nd sentence) which initiates “direct memory access (DMA) circuit in the stream circuit distributes” (see Fig. 1, [0072], 2nd sentence)} configured to initiate DMA transfers of a DMA {see Fig. 5, “packet headers for the packets in the partitions 510”, said packet headers/payload include DMA transfer “direct memory access (DMA) engine 722 that distributes the packets” ([0106], 1st sentence)}, wherein each DMA action {see Fig. 7, “DMA engines 816 may automatically load [one example DMA action] the SHA hash value contained in a head”, [0130], last sentence} of the corresponding plurality of DMA actions of the action group is configured to indicate {see Fig. 7, other types actions “may send an error message/interrupt to central management circuitry” ([0132], last sentence), where DMA actions include read/write/busy signals/selecting channels and so on.}:
a selected DMA controller {see Fig. 7, “when the packet is pushed or pulled to [selected DMA controller] distributed management circuitry 703”, [0129], last sentence} of the plurality of DMA controllers of the SoC {see Fig. 7, plurality of DMA controllers “distributed management circuitry 703-1 through 703-n”, [0096]} and a selected DMA channel {see Fig. 7, “may directly access registers 736 and/or other features of functional circuitry 706-1 via GCI circuit 720, [a selected DMA channel] link 719-1” [0129], last sentence} of the plurality of corresponding DMA channels {see Fig. 7, “second communication channel is a tree-type interconnect that includes a global control interconnect (GCI) circuit 720 rooted… [in conjunction with] local control interconnect circuits rooted in respective distributed management circuitry 703, and [DMA channels] respective links 719-1 through 719-n.”, [0107], 2nd sentence} within the selected DMA controller to perform a corresponding DMA transfer {see Fig. 7, “includes DMA engines 816 that stream [a corresponding DMA transfer] commands and data to and from CIM circuit 704-1.”, [0128]}, wherein at least two DMA actions of the action group perform {at least two DMA actions “headers of configuration packets include SHA hash values (e.g., in 3 quadwords of the header) for respective [DMA] subsequent packets”, see Fig. 7 [0130], 1st sentence} corresponding DMA transfers by selected DMA controllers {“management circuitry 703-1 further includes a NPI switch 747 and end-point circuitry 749 that permit central management circuitry 702 to access and configure CIM circuit 704-1 through”, see Fig. 7 [0108], 1st sentence} located in different device groups {different device groups in hierarchy “NPI root bridge 746 and a NPI switch 748 to permit CIM circuit 704-1 to access LCI circuitry 738”, see Fig. 7, [0108], last two sentences} of the SoC {“adaptive system-on-chip IC devices may include programmable logic, fixed/hardened circuitry” ([0037) where “programmable logic” referred to as “first and second circuits 135A and 135B may be homogeneous circuitry (e.g., both may be memory controllers, or both are programmable logic blocks” which may/may not be homogenous circuitry (see Fig. 1, [0048], last two sentences};
wherein each DMA controller {see Fig. 7, “when the packet is pushed or pulled to [each DMA controller] distributed management circuitry 703”, [0129], last sentence} includes a plurality of corresponding DMA channels {{see Fig. 7, “second communication channel is a tree-type interconnect that includes a global control interconnect (GCI) circuit 720 rooted… [in conjunction with] local control interconnect circuits rooted in respective distributed management circuitry 703, and [DMA channels] respective links 719-1 through 719-n.”, [0107], 2nd sentence};
Ganapathy/Raval and Ansari are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganapathy/Raval and Ansari before him or her, to modify Dalal/Raval’s system incorporating Ansari’s “distributed management circuitry 703-1 through 703-n” (see Fig. 7).
The suggestion/motivation for doing so would have been to implement a SDXI function may analyze the descriptor to infer a source AKey table entry of an AKey table and a destination AKey table entry of the AKey table to initiate the data movement operation (Ansari [0031], 1st sentence) facilitating memory to memory data movement and acceleration among entities including “offload direct memory access DMA engines” (Ansari [0028] paraphrased) overcoming problems associated with I/O intensive workloads and (b) network and storage workloads are becoming noticeable in terms of how they take away compute cycles available within a computing system (Ansari [0026], last sentence).
Therefore, it would have been obvious to combine Ansari with Ganapathy/Raval to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting, Ganapathy, Raval, and Ansari appears to explicitly disclose wherein each corresponding DMA channel having a corresponding transfer control descriptor (TCD) which provides information for conducting a DMA transfer by the DMA controller: and wherein each DMA action is configured to select one of a plurality of DMA controllers and to select a channel of the selected DMA controller; a DMA router engine configured to initiate DMA transfers of an action group associated with a corresponding one of the plurality of interrupt inputs triggered by assertion of a corresponding interrupt signal;
Additionally, Iyer discloses wherein each corresponding DMA channel {“after the RDMA connection establishment process is completed”, see Fig. 6.2, [0282], 1st sentence} having a corresponding transfer control descriptor (TCD) {“producer enqueues a work descriptor into an SDXI descriptor ring”, see Fig. 6.1 [0283, 1st sentence} which provides information for conducting a DMA transfer {“acting as a DMA hardware to read the descriptor to determine, at least, whether [information for the DMA transfer]”, step 514, see Figs. 5.2 and 5.3 [0264]} by the DMA controller {respective controllers “NIC A (280A) … a NIC B 280B”, see Fig. 2.2, [0150]}:
and wherein each DMA action is configured {see Figs. 3.6 and 3.7, DMA listed action group “AKey table entry (of the AKey table shown in Embodiment A) may specify [action group] one or more fields”, [0211], 1st sentence} to select one of a plurality of DMA controllers {“SDXI hardware (272) may include the SDXI DMA engine (274) and one or more smart data accelerators (e.g., SDXI Function 276”, see Fig. 2.2 [0157], 2nd sentence} and to select a channel of the selected DMA controller {“to allow the SDXI hardware to [selecting a channel] manage/perform the data movement operation over the RDMA connection”, step 502, see Figs. 5.2 and 5.3 [0256], last sentence};
a DMA router engine {see Figs. 7, 3.3, 3.7, one example DMA router engine “network-enabled subcomponents may then route each data packet in the network to distribute network traffic uniformly” ([0085], last sentence); other example includes network interface controller “NIC A (278A)” with steer tag in respective AKey or RKey tables (see Fig. 2.3, [0173], 2nd sentence} configured to initiate DMA transfers {see Fig. 2.3, “NIC A (278A)) initiates an RDMA connection establishment process between the IHS (200) and the HIS 201”, [0173], 2nd sentence} of an action group {see Figs. 3.6 and 3.7, DMA listed action group “AKey table entry (of the AKey table shown in Embodiment A) may specify [action group] one or more fields”, [0211], 1st sentence} associated with a corresponding one {see Figs. 3.6 and 3.7, “a steering tag (stag) field at bits 079:064 (e.g., when ste=1 and tgt_sfunc=0, this field supplies information used as part of DSH” ([0211]), the DSH referring to a DMA descriptor “steering hint (DSH) information when requested through the corresponding descriptor” ([0211]) for a specified group “which asset/data that a user wants to transfer and which source/destination memory buffers that the user wants to target” (see Fig. 3.3, [0209], 1st sentence} of the plurality of interrupt inputs {see Fig. 3.4, “RKey table entries … to selectively expose data buffers and/or interrupts to different [corresponding DMA] requesting functions”, [0214]} triggered by assertion of a corresponding interrupt signal {see Figs. 3.6 and 3.7, “[corresponding triggered] interrupts generated using this AKey table entry”, [0211]};
Ganapathy/Raval/Ansari and Iyer are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ganapathy/Raval/Ansari and Iyer before him or her, to modify Dalal/Raval/Ansari’s system incorporating Iyer’s “RDMA connection establishment process” and corresponding AKey/RKey (see Fig. 6.2).
The suggestion/motivation for doing so would have been to implement inline configuration interface processing are described such as an integrated circuit (IC) device that includes functional circuitry, a packet-switched network-on-chip (NoC), and distributed management circuitry that includes a plurality of configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over the NoC the size and heterogeneous nature of programming images for such devices has rendered configuration through a centralized processing manager inefficient. (Ansari [0004] paraphrased).
Therefore, it would have been obvious to combine Iyer with Ganapathy/Raval/Ansari to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Ansari discloses wherein each DMA action comprises a corresponding DMA controller select value that selects one {see Fig. 7, “when the packet is pushed or pulled to distributed management circuitry 703”, [0129], last sentence} of the plurality of DMA controllers {see Fig. 7, plurality of DMA controllers “distributed management circuitry 703-1 through 703-n”, [0096]} and a corresponding channel select value that selects one {see Fig. 7, “may directly access registers 736 and/or other features of functional circuitry 706-1 via GCI circuit 720, [a selected DMA channel] link 719-1” [0129], last sentence} of the plurality of corresponding DMA channels {see Fig. 7, “second communication channel is a tree-type interconnect that includes a global control interconnect (GCI) circuit 720 rooted… [in conjunction with] local control interconnect circuits rooted in respective distributed management circuitry 703, and [DMA channels] respective links 719-1 through 719-n.”, [0107], 2nd sentence} of the DMA controller selected by the corresponding DMA controller select value {see Fig. 7, “reads contents of configuration registers/memory of functional circuitry 706-1 through configuration circuitry” [0154], 2nd sentence}.
As per claim 3, the rejection of claim 1 is incorporated and Iyer discloses wherein the action group associated with the corresponding one of the plurality of interrupt inputs comprises:
a first DMA action configured {at least a DMA action “headers of configuration packets include SHA hash values (e.g., in 3 quadwords of the header) for respective [DMA] subsequent packets”, see Fig. 7 [0130], 1st sentence} to select first DMA controller of the plurality of DMA controllers {see Fig. 7, “when the packet is pushed or pulled to [selected DMA controller] distributed management circuitry 703”, [0129], last sentence} and a first DMA channel {“a selected DMA channel] link 719-1” [0129], last sentence} within the first DMA controller to perform a first DMA transfer {see Fig. 7, “includes DMA engines 816 that stream [a corresponding first DMA transfer] commands and data to and from CIM circuit 704-1.”, [0128]} and a second DMA action {repeatedly a DMA action “headers of configuration packets include SHA hash values (e.g., in 3 quadwords of the header) for respective [DMA] subsequent packets”, see Fig. 7 [0130], 1st sentence} configured to select a second DMA controller {see Fig. 7, “when the packet is pushed or pulled to [another selected DMA controller] distributed management circuitry 703”, [0129], last sentence} of the plurality of DMA controllers and a second DMA channel within the second DMA controller {see Fig. 7, “[a selected DMA channel] link 719-1” [0129], last sentence} to perform a second DMA transfer {see Fig. 7, “includes DMA engines 816 that stream [a second corresponding DMA transfer] commands and data to and from CIM circuit 704-1.”, [0128]};
wherein the DMA router engine {see Figs. 7, 3.3, 3.7, one example DMA router engine “network-enabled subcomponents may then route each data packet…”, [0085], last sentence}, upon assertion of the corresponding interrupt signal {see Figs. 3.6 and 3.7, “[corresponding triggered] interrupts generated using this AKey table entry”, [0211]} provided to the corresponding one of the plurality of interrupt inputs {see Fig. 3.4, “RKey table entries … to selectively expose data buffers and/or interrupts to different [corresponding DMA] requesting functions”, [0214]}, and initiates the second DMA transfer {see Fig. 2.3, “NIC A (278A)) initiates an [plurality of] RDMA connection establishment process between the IHS (200) and the HIS 201”, [0173], 2nd sentence} using the second channel of the second DMA controller {see Fig. 2.4, “represent a data movement operation over an [at least one or more] RDMA connection between different user spaces located in different IHSs”, [0172], 2nd sentence}.
As per claim 4, the rejection of claim 3 is incorporated and Ganapathy discloses wherein the first and second DMA transfers are allowed to overlap each other in time {“bus multiplexes a number of DMA transactions concurrently”, see Figs. 1 and 2 [0020], 2nd sentence}.
As per claim 5, the rejection of claim 3 is incorporated and Raval discloses wherein the second DMA action is configured {“can stall issuing more commands [including DMA actions] until” a dependency is resolved, see Fig. 3 [0060]} to indicate a dependence upon the first DMA action {“When a [first DMA action] Completion Wait Command received through IOMMU Command Processor is forwarded”, see Fig. 3 [0060]}, and wherein the DMA router engine is configured to initiate the second DMA transfer {“so wait for all credits as a synchronization mechanism [for a second transfer].”, see Fig. 3 [0060]} only after completion of the first DMA transfer {“performing [first transfer implied by] Completion Wait write back or Interrupt.”, see Fig. 3 [0060]}.
As per claim 6, the rejection of claim 3 is incorporated and Ansari discloses wherein each device group {“NPI root bridge 746 and a NPI switch 748 to permit CIM circuit 704-1 to access LCI circuitry 738”, see Fig. 7, [0108]} of the SoC is characterized {“IC 110 can be a SoC or an application specific integrated circuit (ASIC [0115], last two sentences} as a processing device group {“Packet processor 804 may directly read residual data in a FIFO buffer of CFrame circuitry 744, and may push the residual data to a read FIFO buffer 906 of data engine 904, such as described below with respect to a support mode”, see Fig. 9a, [0149], last sentence} or a peripheral device group {“coherent peripheral component interconnect express (PCIe) modules CPMs”, see Fig. 1, [0002]}}, and the first and second DMA controllers are located {see Fig. 7, plurality of DMA controllers “distributed management circuitry 703-1 through 703-n”, [0096]} in different device groups {maintain different device groups per “NPI root bridge 746 and a NPI switch 748 to permit CIM circuit 704-1 to access LCI circuitry 738” which in turn each switch per DMA controller “distributed management circuitry 703-1 through 703-n”, see Fig. 7, [0096]} of the SoC.
As per claim 7, the rejection of claim 1 is incorporated and Ganapathy discloses wherein at least two of the corresponding DMA transfers are allowed to overlap in time {“bus multiplexes a number of DMA transactions concurrently”, see Figs. 1 and 2 [0020], 2nd sentence}.
As per claim 8, the rejection of claim 1 is incorporated and Raval discloses wherein each DMA action comprises an action dependency value {“PPR auto response messages, and normal PPR response messages fetched from Command Buffer”, see Fig. 3 [0057], 1st sentence} that may be used to indicate a dependence upon {“When a [first DMA action] Completion Wait Command received through IOMMU Command Processor is forwarded”, see Fig. 3 [0060]} at least one other DMA action within the same action group {“into most significant bits of [same action group] PPR Page Request Group Index field”, see Fig. 3 [0057], 2nd sentence}, and wherein the DMA router engine is configured to initiate at least one of the corresponding DMA transfers {“[other transfers] Messages received by other IOMMUs from the data fabric”, see Fig. [0046], last sentence} only after completion of at least one other one of the corresponding DMA transfers based upon indicated dependencies {“GA Logs [depends on] triggered by SDXI engine AVIC interrupts to the particular context will be forwarded to a context owning IOMMU”, see Figs. 1 and 2”, see Fig. [0029], last sentence}.
As per claim 9, the rejection of claim 1 is incorporated and Raval discloses further comprising a location value associated with a programmable interrupt {“checking and interrupt remapping for peripheral component endpoints interrupts”, see Figs. 1 and 2 [0020]}, wherein the DMA router engine is further configured, in response to assertion of an interrupt signal {“IOMMU will use DTE and IRTE structures from requested IOMMU context to service interrupts” (see Fig. 3 [0053])} provided to the programmable interrupt {“data structures such Device Table, etc., that can be programmed independently” including interrupts, see Fig. 5 [0063] last sentence}, to access a remote action group using the location value {“Work queue 120 is used for executing operations, along with all associated memory data structures such as control and status information”, see Fig. 1 [0024], 2nd sentence} and to initiate a DMA transfer for each DMA action {“[other transfers] Messages received by other IOMMUs from the data fabric”, see Fig. [0046], last sentence} listed in the remote action group {“engine bus number ranges, which are derived on hubs numbers, such as NBIF Secondary/Subordinate Bus numbers, are also context specific”, see Fig. 2 [0039]}.
Referring to claim 10 is a system claim reciting claim functionality corresponding to the apparatus claim of claim 1, thereby rejected under the same rationale as claims 1 recited above, inter alia, Ganapathy discloses a system-on-chip (SoC), comprising {“system on a chip” (see Fig. 1 [0018])}: a direct memory access (DMA) router, comprising {routing via “address lines used by the bus to perform DMA transfers” ([0020], 1st sentence)}
Raval discloses a programmable control module {“data structures such Device Table, etc., that can be programmed independently” including interrupts, see Fig. 5 [0063] last sentence} that is configured to route an interrupt signal {“[other transfers] Messages received by other IOMMUs from the data fabric”, see Fig. [0046], last sentence; } to one of the plurality of interrupt inputs of the DMA router {“IOMMU messages are sent with [selected channel] Route By ID decoding and are expected to only target other IOMMUs.”, see Figs. 1 and 2 [0045], last sentence}.
The 103 motivation relied upon in this independent claim as recited in claim 1 above.
Referring to claims 11-20 are method claims reciting claim functionality corresponding to the apparatus claims of claims 1-9, respectively, thereby rejected under the same rationale as claims 1-9 recited above, inter alia, Ganapathy discloses a system-on-chip (SoC), comprising {“system on a chip” (see Fig. 1 [0018])}: a direct memory access (DMA) router, comprising {routing via “address lines used by the bus to perform DMA transfers” ([0020], 1st sentence)}
Raval discloses a programmable control module {“data structures such Device Table, etc., that can be programmed independently” including interrupts, see Fig. 5 [0063] last sentence} that is configured to route an interrupt signal {“[other transfers] Messages received by other IOMMUs from the data fabric”, see Fig. [0046], last sentence} to one of the plurality of interrupt inputs of the DMA router {“IOMMU messages are sent with [selected channel] Route By ID decoding and are expected to only target other IOMMUs.”, see Figs. 1 and 2 [0045], last sentence}.
The 103 motivation relied upon in this independent claim as recited in claim 1 above.
Response to Arguments
Applicant’s arguments filed on 01/23/2026 have been considered but deemed moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “DMA controller”, “NOC”, or “interrupt input”: US 20110022767 A1, US 20180203815 A1, US 20190236022 A1, US 20210157312 A1, US 20230048836 A1, US 20230308199 A1, and US 8799529 B2.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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