DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites that “the plurality of second pads are exposed on a second surface of the carrier where the inner bending surface is located on”. However, this is incongruent with the previously recited limitations in claims 1 and 2 from which claim 5 depends. Specifically in claim 1 “the bonding layer” [which is on the chip] “located on the nonplanar surface is bonded to the plurality of second pads.”, and in claim 2, “the at least one chip is mounted on the outer bending surface.” Therefore, the chip is both on the outer side and bonded to the inner side, which does not make sense in light of the specification of the instant application. For the purposes of applying art, the limitation in claim 5 was taken to be “the plurality of second pads are exposed on a first surface of the carrier where the outer bending surface is located on.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chao et al. (US 20240395991 A1), hereinafter referred to as "Chao", in view of Chang et al. (US 20070222072 A1), hereinafter referred to as "Chang".
Regarding claim 1, Chao discloses a display panel package comprising: a carrier (100 in Chao figure 7) including a plurality of first pads (123 in Chao figure 7) and a plurality of second pads (113 in Chao figure 7); a plurality of light-emitting elements disposed on the carrier (400 in Chao figure 7; they may be light-emitting diodes, see Chao paragraph 0041) and electrically connected to the plurality of first pads (Chao paragraph 0040; the electronic component 400 can be electrically connected to the pad 123); and at least one chip disposed on a portion to be bent of the carrier (200 in Chao figure 7; it is on a bent portion).
Chao does not explicitly teach the specific structure of the chip or how it is connected to the carrier.
Chang teaches a plurality of second pads (224 in Chang figure 2) and a chip including a plurality of chip pads (212 in Chang figure 2) and a plurality of bumps (230+240+226 in Chang figure 2), each of the plurality of bumps includes at least one composite contact which includes a base (240 on the upper part of 230 in Chang figure 2) and a bonding layer (surface bonding layer 226 in Chang figure 2), the bonding layer is electrically connected to one of the plurality of chip pads (226 is connected to 212 through 230 and 240), the base is covered by the bonding layer such that each of the plurality of bumps has a nonplanar surface (the surface of the upper segment of 240 is nonplanar, and is covered by 226), and the bonding layer located on the nonplanar surface is bonded to the plurality of second pads (226 is bonded to the pads 224). Chang also teaches that this is a way to connect a chip to a carrier with a short transmission pathway (Chang paragraphs 0006 and 0007).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the chip from Chao using the bumps and pads from Chang in order to connect it to the carrier with a short transmission pathway.
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Regarding claim 2, Chao in view of Chang discloses all of the limitations of claim 1. Chao further discloses that the portion to be bent of the carrier includes an outer bending surface and an inner bending surface opposite to each other (see Chao figure 7),
In that embodiment, Chao does not specifically teach the chip is mounted on the outer bending surface. However, in a separate embodiment, Chao discloses the at least one chip is mounted on the same side of the carrier as the electronic component 400 (See 200 in Chao figure 3), which if taken with the embodiment in figure 7 would result in the chip being mounted on the outer bending surface. Chao also teaches that this layout can simplify the wiring connections between those components.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the chip be mounted on the outer bending surface in order to simplify the wiring connections.
Chang further discloses that an active surface of the at least one chip has a middle area, an outer area and an edge (210 in Chang figure 2; left and right sidewalls can be the edges, the center can be the middle area and the area between those can be the outer area), the outer area is located between the middle area and the edge, and the plurality of bumps are disposed on the outer area (the bumps are along the full middle and outer area, and are thus on the outer area).
Regarding claim 3, Chao in view of Chang discloses all of the limitations of claim 1. Chao further discloses that the portion to be bent of the carrier includes an outer bending surface and an inner bending surface opposite to each other (see Chao figure 7), the at least one chip is mounted on the inner bending surface (200 in figure 7 is on the inner surface, the bottom of the carrier in figure 7).
Chang further discloses that an active surface of the at least one chip has a middle area, an outer area and an edge (210 in Chang figure 2; left and right sidewalls can be the edges, the center can be the middle area and the area between those can be the outer area), the outer area is located between the middle area and the edge, and the plurality of bumps are disposed on the middle area (the bumps are along the full middle and outer area, and are thus on the middle area).
Regarding claim 4, Chao in view of Chang discloses all of the limitations of claim 1. Chao further discloses that the carrier further includes a first circuit board (120 in Chao figure 7), a second circuit board (110 in Chao figure 7), an adhesive layer (130 in Chao figure 7) and a conductive via (140 in Chao figure 7), the first and second circuit boards are connected with each other by the adhesive layer (Chao paragraph 0032), a first circuit layer of the first circuit board includes the plurality of first pads (Chao paragraph 0028) a second circuit layer of the second circuit board (Chao paragraph 0026) the conductive via is electrically connected to the first and second circuit layers (Chao paragraph 0034), the plurality of first pads are exposed on a first surface of the carrier where the outer bending surface is located on (123 in Chao figure 7 are on the outer bending surface).
Chao does not explicitly teach that the second circuit layer includes the pads that connect the chips 200, or that those pads are on the inner bending surface.
Chang teaches that a circuit layer includes the plurality of second pads (pads 224 are a part of the underlying circuit layer in the substrate 220 in Chang figure 2), and the plurality of second pads are exposed on a second surface of the carrier where the chip is located on (pads 224 are on the side of the substrate that connects to the chip 210). As applied to Chao, the pads being on the side of the carrier that has the chip would mean that they are on the inner bending surface, since that’s the surface with the chips 200 in Chao figure 7. This allows for the chip to be electrically connected to the carrier and other electronic components in the package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the pads be included in the circuit layer and on the inner bending side in order to electrically connect the chip to other components in the package.
Regarding claim 5, Chao in view of Chang discloses all of the limitations of claim 2. Chao further discloses that the carrier further includes a first circuit board (120 in Chao figure 7), a second circuit board (110 in Chao figure 7), an adhesive layer (130 in Chao figure 7) and a conductive via (140 in Chao figure 7), the first and second circuit boards are connected with each other by the adhesive layer (Chao paragraph 0032), a first circuit layer of the first circuit board includes the plurality of first pads (Chao paragraph 0028) a second circuit layer of the second circuit board (Chao paragraph 0026) the conductive via is electrically connected to the first and second circuit layers (Chao paragraph 0034), the plurality of first pads are exposed on a first surface of the carrier where the outer bending surface is located on (123 in Chao figure 7 are on the outer bending surface).
Chao does not explicitly teach that the second circuit layer includes the pads that connect the chips 200, or that those pads are on the outer bending surface (see 112b rejection above).
Chang teaches that a circuit layer includes the plurality of second pads (pads 224 are a part of the underlying circuit layer in the substrate 220 in Chang figure 2), and the plurality of second pads are exposed on a first surface of the carrier where the chip is located on (pads 224 are on the side of the substrate that connects to the chip 210). As applied to Chao, the pads being on the side of the carrier that has the chip would mean that they are on the outer bending surface, since that’s the surface with the chips 200 in Chao figure 7. This allows for the chip to be electrically connected to the carrier and other electronic components in the package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the pads be included in the circuit layer and on the inner bending side in order to electrically connect the chip to other components in the package.
Regarding claim 6, Chao in view of Chang discloses all of the limitations of claim 3. Chao further discloses that the carrier further includes a first circuit board (120 in Chao figure 7), a second circuit board (110 in Chao figure 7), an adhesive layer (130 in Chao figure 7) and a conductive via (140 in Chao figure 7), the first and second circuit boards are connected with each other by the adhesive layer (Chao paragraph 0032), a first circuit layer of the first circuit board includes the plurality of first pads (Chao paragraph 0028) a second circuit layer of the second circuit board (Chao paragraph 0026) the conductive via is electrically connected to the first and second circuit layers (Chao paragraph 0034), the plurality of first pads are exposed on a first surface of the carrier where the outer bending surface is located on (123 in Chao figure 7 are on the outer bending surface).
Chao does not explicitly teach that the second circuit layer includes the pads that connect the chips 200, or that those pads are on the inner bending surface.
Chang teaches that a circuit layer includes the plurality of second pads (pads 224 are a part of the underlying circuit layer in the substrate 220 in Chang figure 2), and the plurality of second pads are exposed on a second surface of the carrier where the chip is located on (pads 224 are on the side of the substrate that connects to the chip 210). As applied to Chao, the pads being on the side of the carrier that has the chip would mean that they are on the inner bending surface, since that’s the surface with the chips 200 in Chao figure 7. This allows for the chip to be electrically connected to the carrier and other electronic components in the package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the pads be included in the circuit layer and on the inner bending side in order to electrically connect the chip to other components in the package.
Regarding claim 7, Chao in view of Chang discloses all of the limitations of claim 1.
Chang further discloses that the at least one composite contact further includes a metal layer which is located between the base and the bonding layer (230 in Chang figure 2) and electrically connected to the plurality of second pads and the bonding layer (Chang paragraph 0026).
Regarding claim 11, Chao in view of Chang discloses all of the limitations of claim 1. Chao does not disclose a filling material between the carrier and the chip.
Chang teaches a filling material, wherein the filling material is provided between the carrier and the at least one chip to cover an exposed surface of the bonding layer (250 in Chang figure 2). Chang teaches that this protects the bumps and alleviates the mismatch of thermal strains generated by the package substrate and the chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the filling material of Chang in order to protect the bumps and alleviate the mismatch of thermal strains generated by the package substrate and the chip.
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Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chao in view of Chang as applied to claim 1 above, and further in view of Ryu et al. (US 20170373028 A1), hereinafter referred to as "Ryu".
Regarding claim 8, Chao in view of Chang discloses all of the limitations of claim 1. Neither Chao nor Chang tech a terminal of the bump inserted into the second pads.
Ryu teaches a bump structure where a terminal of the at least one composite contact of each of the plurality of bumps is inserted into the plurality of second pads (Ryu figures 6A and 6B. Bottom most portions of 642 are inserted into the pad structure 420). Ryu also teaches that this makes the two tightly bonded together (Ryu paragraphs 0125-0127).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to insert a terminal of the bump into the pad as in Ryu in order to ensure a tight bond between the bumps and the pads.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chao in view of Chang as applied to claims 2 and 3 above, respectively, and further in view of Lee et al. (US 20250357291 A1), hereinafter referred to as "Lee".
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Regarding claim 9, Chao in view of Chang discloses all of the limitations of claim 2. Neither Chao nor Chang teach that the chip has several bumps without a composite contact.
Lee teaches a bonding structure where the bumps decrease in height along the length of a substrate (Lee figure 11). Lee teaches that the heights vary with the warpage of the substrate, and increase package flatness (Lee paragraphs 0133 and 0134). The additional layers added in a composite contact naturally increase the size of the bump, and thus, removing them is a natural way to decrease the height of the bumps. Therefore, incorporating Lee’s teachings would have the bumps without composite contacts be in the middle area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have some of the bumps in the middle portion of the chip be without a composite contact in order to decrease the height of the bumps, as taught by Lee, in order to follow the curving of the substrate and improve the package flatness.
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Regarding claim 10, Chao in view of Chang discloses all of the limitations of claim 3. Neither Chao nor Chang teach that the chip has several bumps without a composite contact.
Lee teaches a bonding structure where the bumps increase in height along the length of a substrate (Lee figure 1). Lee teaches that the heights vary with the warpage of the substrate, and increase package flatness (Lee paragraphs 0052 and 0053). The additional layers added in a composite contact naturally increase the size of the bump, and thus, removing them is a natural way to decrease the height of the bumps. Therefore, incorporating Lee’s teachings would have the bumps without composite contacts be in the outer area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have some of the bumps in the outer portion of the chip be without a composite contact in order to decrease the height of the bumps, as taught by Lee, in order to follow the curving of the substrate and improve the package flatness.
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Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chao in view of Chang as applied to claim 1 above, and further in view of Wu et al. (US 20230326894 A1), hereinafter referred to as "Wu".
Regarding claim 12, Chao in view of Chang discloses all of the limitations of claim 1. Neither Chao nor Chang teach that the composite contact is a strip or a cone.
Wu teaches a composite contact that is a cone (140 in Wu figure 3A, Wu paragraph 0027). Wu also teaches that this structure reduces the impedance between the chip and the substrate (Wu paragraph 0003).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the composite contact a cone as in Wu in order to reduce the impedance between the chip and the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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