DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 13-14, 18-19 and 23-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the first physical storage space" in line 5. There is insufficient antecedent basis for this limitation in the claim. The first instance of this term was cancelled in the amendment. This limitation is considered to be referring back to “a physical storage space” from claim 1. This applies to claims 3, 13, 14, 18, 19 and 23-26 with their respective independent claims as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9-14, 17-19 and 23-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sabol et al. (US 2018/0285257) and further in view of “how to use Rsync Command in Linux: 16 practical examples” henceforth referred to as Tarunika and KSR.
Consider claim 1, Sabol et al. a system, comprising: a host configured to send a copy command comprising a first logical address, a second logical address; wherein the first logical address and the second logical address are logical block addresses (LBAs) identified by the host, the copy command instructs copying data stored in a memory system from the first logical address to the second logical address, the memory system coupled to the host, wherein the memory system comprises a non-volatile memory device and a memory controller coupled to the non-volatile memory device, wherein the memory system is configured to: receive the copy command; in response to the copy command, establish mapping relationship between the second logical address and a physical storage space of the data in which the data is stored in the non-volatile memory device (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Sabol et al. discloses deallocating memory based on a command, but after further consideration of the amended claim language and to further elaborate on this concept, the following limitations: “the copy command comprising a flag bit, the flag bit indicates whether to deallocate the first logical address and determine whether to deallocate the first logical address based on the flag bit of the copy command without receiving a separate deallocation command from the host for the first logical address, and wherein the memory system is configured to: in response to the flag bit comprising a first value, deallocate the first logical address” are further being rejected with the addition of the Tarunika reference. Tarunika discloses the use of Rsync which is a command used to transfer data and this command can also include flags such as “-remove-source-files”. Therefore the absence of this flag does not deallocate the data at the source and having this flag does deallocate. Sobal et al. discloses updating a correspondence to indicate the movement of data between memories. (Tarunika first page and item 14 in the table of contents.).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the write command of Sabol et al. to be a Rsync command of Tarunika, because this type of command provides efficient file transfer and allows for multiple types of flags which provides more utility to the command (Tarunika: beginning of reference to the Rsync Command Syntax section.).
As for the limitation: “and in response to the flag bit comprising a second value different from the first value, retain the correspondence of the data to the first logical address”, Tarunika teaches the absence of the flag bit indicates to retain the claimed data, not that the flag bit has a different value. However the absence of a flag bit and a different value for a flag bit are functionally equivalent to each other in producing the desired outcome and therefore the examiner is utilizing the KSR rationale of “obvious to try” to reject this minor difference between the claim language and the Tarunika reference.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the combination of references to include the “-remove-source-files” flag in either situation (to remove or not remove) with two different values instead of the flag either being present or not, because these two options are functionally equivalent to each other (a true or false representation in either implementation) and choosing to have the flag remain with a different value is a choice made from a finite number of identified, predictable solutions with a reasonable expectation of success.
Consider claim 2, Sabol et al. in view of Tarunika discloses the system of claim 1, wherein the memory system is configured to establish the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non-volatile memory device by reading the data from the first physical storage space of the memory system corresponding to the first logical address; writing the data to a second physical storage space of the memory system; and establishing a mapping relationship between the second logical address and the second physical storage space (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address and update a correspondence to indicate the movement of data.).
Consider claim 3, Sabol et al. in view of Tarunika discloses the system of claim 1, wherein the memory system is configured to establish the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non-volatile memory device by establishing a mapping relationship between the second logical address and the first physical storage space of the memory system corresponding to the first logical address (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses updating a correspondence to indicate the movement of data between memories.).
Consider claim 9, Sabol et al. in view of Tarunika discloses the system of claim 1, wherein the memory system is further configured to: in response to a completion of an execution of the copy command, send a response signal to the host; and upon receiving a read command instructing reading out the data corresponding to the first logical address following the completion of the execution of the copy command, return an invalid data or other data different from the data (Fig. 1-6, [0027]-[0054], [0062], [0091]-[0098], Sobal et al. discloses the use of acknowledgement signal and further being able to return error/different data due to a read.).
Consider claim 10, Sabol et al. in view of Tarunika discloses the system of claim 1, wherein the host comprises an interface comprising a driver and an interconnector, the interconnector coupled to the driver and the memory system, and wherein: the driver is configured to generate the copy command that complies with protocol standards based on a request from an operating system in the host; and the interconnector is configured to transfer the copy command to the memory system through a communication bus (Fig. 1-6, [0027]-[0054], [0062], [0091]-[0098], Sobal et al. discloses the use of drivers and protocols as claimed.).
Consider claim 11, Sabol et al. discloses a memory system, comprising: a non-volatile memory device; and a memory controller coupled to the non-volatile memory device and configured to: receive a copy command comprising a first logical address and a second logical address; wherein the first logical address and the second logical address are logical block addresses (LBAs) associated with the non-volatile memory device, copy command instructs copying data stored in the memory system from the first logical address to the second logical address; in response to the copy command, establish a mapping relationship between the second logical address and a physical storage space of the data in which the data is stored in the non-volatile memory device; and deallocate the first logical address based on the command (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Sabol et al. discloses deallocating memory based on a command, but after further consideration of the amended claim language and to further elaborate on this concept, the following limitations: “the copy command comprising a flag bit, the flag bit indicates whether to deallocate the first logical address and determine whether to deallocate the first logical address based on the flag bit of the copy command without receiving a separate deallocation command from the host for the first logical address, and wherein the memory system is configured to: in response to the flag bit comprising a first value, deallocate the first logical address;” are further being rejected with the addition of the Tarunika reference. Tarunika discloses the use of Rsync which is a command used to transfer data and this command can also include flags such as “-remove-source-files”. Therefore the absence of this flag does not deallocate the data at the source and having this flag does deallocate. Sobal et al. discloses updating a correspondence to indicate the movement of data between memories. (Tarunika first page and item 14 in the table of contents.).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the write command of Sabol et al. to be a Rsync command of Tarunika, because this type of command provides efficient file transfer and allows for multiple types of flags which provides more utility to the command (Tarunika: beginning of reference to the Rsync Command Syntax section.).
As for the limitation: “and in response to the flag bit comprising a second value different from the first value, retain the correspondence of the data to the first logical address”, Tarunika teaches the absence of the flag bit indicates to retain the claimed data, not that the flag bit has a different value. However the absence of a flag bit and a different value for a flag bit are functionally equivalent to each other in producing the desired outcome and therefore the examiner is utilizing the KSR rationale of “obvious to try” to reject this minor difference between the claim language and the Tarunika reference.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the combination of references to include the “-remove-source-files” flag in either situation (to remove or not remove) with two different values instead of the flag either being present or not, because these two options are functionally equivalent to each other (a true or false representation in either implementation) and choosing to have the flag remain with a different value is a choice made from a finite number of identified, predictable solutions with a reasonable expectation of success.
Consider claim 12, Sabol et al. in view of Tarunika discloses the memory system of claim 11, wherein the memory controller comprises: a first interface coupled to a host and configured to: receive the copy command, and decode the copy command; and a processor coupled to the first interface and configured to establish the correspondence of the data to the second logical address based on the correspondence of the data to the first logical address and deallocate the first logical address based on the copy command (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command, and in response that data can be written to a buffer, the written to storage, have the buffer freed and update a correspondence to indicate the movement of data. Tarunika first page and item 14 in the table of contents. If the flag is set the source data is deleted.).
Consider claim 13, Sabol et al. in view of Tarunika discloses the memory system of claim 12, wherein the memory system is configured to establish the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non- volatile memory device by: sending, to the non-volatile memory device, a read command to read the data from the first physical storage space of the non-volatile memory device; sending, to the non-volatile memory device, a write command to write the data to a second physical storage space of the non-volatile memory device; and establishing a mapping relationship between the second logical address and the second physical storage space (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Consider claim 14, Sabol et al. in view of Tarunika discloses the memory system of claim 12, wherein the memory system is configured to establish the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non- volatile memory device by: establishing a mapping relationship between the second logical address and the first physical storage space of the non-volatile memory device corresponding to the first logical address (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Consider claim 17, Sabol et al. discloses a method of operating a memory system, comprising: receiving, by a memory controller of the memory system, a copy command comprising a first logical address and a second logical address; wherein the first logical address and the second logical address are logical block addresses (LBAs) associated with the non-volatile memory device of the memory system, the copy command instructs copying data stored in a memory system from the first logical address to the second logical address,; in response to the copy command, establishing a mapping relationship between the second logical address and a physical storage space of the data in which the data is stored in the non-volatile memory device; and deallocating the first logical address based on the command (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Sabol et al. discloses deallocating memory based on a command, but after further consideration of the amended claim language and to further elaborate on this concept, the following limitations: “the copy command comprising a flag bit, the flag bit indicates whether to deallocate the first logical address and determine whether to deallocate the first logical address based on the flag bit of the copy command without receiving a separate deallocation command from the host for the first logical address, and wherein the memory system is configured to: in response to the flag bit comprising a first value, deallocate the first logical address;” are further being rejected with the addition of the Tarunika reference. Tarunika discloses the use of Rsync which is a command used to transfer data and this command can also include flags such as “-remove-source-files”. Therefore the absence of this flag does not deallocate the data at the source and having this flag does deallocate, this deallocation is considered to be equivalent to cancelling the correspondence of the data to the first logical address (source data is deleted). Sobal et al. discloses updating a correspondence to indicate the movement of data between memories. (Tarunika first page and item 14 in the table of contents.).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the write command of Sabol et al. to be a Rsync command of Tarunika, because this type of command provides efficient file transfer and allows for multiple types of flags which provides more utility to the command (Tarunika: beginning of reference to the Rsync Command Syntax section.).
As for the limitation: “and in response to the flag bit comprising a second value different from the first value, retain the correspondence of the data to the first logical address”, Tarunika teaches the absence of the flag bit indicates to retain the claimed data, not that the flag bit has a different value. However the absence of a flag bit and a different value for a flag bit are functionally equivalent to each other in producing the desired outcome and therefore the examiner is utilizing the KSR rationale of “obvious to try” to reject this minor difference between the claim language and the Tarunika reference.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the combination of references to include the “-remove-source-files” flag in either situation (to remove or not remove) with two different values instead of the flag either being present or not, because these two options are functionally equivalent to each other (a true or false representation in either implementation) and choosing to have the flag remain with a different value is a choice made from a finite number of identified, predictable solutions with a reasonable expectation of success.
Consider claim 18, Sabol et al. in view of Tarunika discloses the method of claim 17, wherein establishing the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non-volatile memory device comprises: reading the data from the first physical storage space of a non-volatile memory device of the memory system corresponding to the first logical address; writing the data to a second physical storage space of the non-volatile memory device; and establishing a mapping relationship between the second logical address and the second physical storage space (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Consider claim 19, Sabol et al. in view of Tarunika discloses the method of claim 17, wherein establishing the mapping relationship between the second logical address and the physical storage space of the data in which the data is stored in the non-volatile memory device comprises: establishing a mapping relationship between the second logical address and first physical storage space of a non-volatile memory device of the memory system corresponding to the first logical address (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory. The system updates a correspondence to indicate the movement of data. Data can be moved in bulk.).
Consider claim 23, Sabol et al. in view of Tarunika discloses the memory system of claim 1, wherein the first logical address corresponds to the first physical storage space of the non-volatile memory device, and the second logical address corresponds to one of the first physical storage space and a second physical storage space of the non-volatile memory device (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory storage space.).
Consider claim 24, Sabol et al. in view of Tarunika discloses the memory system of claim 1, wherein the memory system is configured to: in response to deallocating the first logical address, mark pages in the first physical storage space of the memory system as invalid, the data corresponding to the first logical address and being stored in the first physical storage space, and discard the data in the first physical storage space, without migrating the data in the first physical storage space to another physical storage space of the memory system during garbage collection (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses performing Garbage collection which includes not moving deleted/invalidated data.).
Consider claim 25, Sabol et al. in view of Tarunika discloses the memory system of claim 11, wherein the first logical address corresponds to the first physical storage space of the non-volatile memory device, and the second logical address corresponds to one of the first physical storage space and a second physical storage space of the non-volatile memory device (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses a system where a host sends a command, such as a write command. This write command includes at least a source and destination address which are both associated with a non-volatile memory storage space.).
Consider claim 26, Sabol et al. in view of Tarunika discloses the memory system of claim 11, wherein the memory system is configured to: in response to deallocating the first logical address, mark pages in the first physical storage space of the memory system as invalid, the data corresponding to the first logical address and being stored in the first physical storage space, and discard the data in the first physical storage space, without migrating the data in the first physical storage space to another physical storage space of the memory system during garbage collection (Fig. 1-6, [0027]-[0054], [0091]-[0098], Sobal et al. discloses performing Garbage collection which includes not moving deleted/invalidated data.).
Consider claim 27, Sabol et al. in view of Tarunika discloses the memory system of claim 12, wherein the memory system is further configured to: in response to a completion of an execution of the copy command, send a response signal to the host; and upon receiving a read command instructing reading out the data corresponding to the first logical address following the completion of the execution of the copy command, return an invalid data or other data different from the data (Fig. 1-6, [0027]-[0054], [0062], [0091]-[0098], Sobal et al. discloses the use of acknowledgement signal and further being able to return error/different data due to a read.).
Consider claim 28, Sabol et al. in view of Tarunika discloses the memory system of claim 12, wherein the host comprises an interface comprising a driver and an interconnector, the interconnector coupled to the driver and the memory system, and wherein: the driver is configured to generate the copy command that complies with protocol standards based on a request from an operating system in the host; and the interconnector is configured to transfer the copy command to the memory system through a communication bus (Fig. 1-6, [0027]-[0054], [0062], [0091]-[0098], Sobal et al. discloses the use of drivers and protocols as claimed.).
Consider claim 29, Sabol et al. in view of Tarunika discloses the system of claim 1, wherein the first value of the flag bit is logic 1 and the second value of the flag bit is logic 0 (Tarunika first page and item 14 in the table of contents. Tarunika in view of the KSR rationale presented in claim 1 describes that having flag bits with two different values is equivalent to a flag value being present or not.).
Consider claim 30, Sabol et al. in view of Tarunika discloses the system of claim 11, wherein the first value of the flag bit is logic 1 and the second value of the flag bit is logic 0 (Tarunika first page and item 14 in the table of contents. Tarunika in view of the KSR rationale presented in claim 1 describes that having flag bits with two different values is equivalent to a flag value being present or not.).
Response to Arguments
Applicant’s arguments filed 7/24/2026 have been fully considered but they are not persuasive.
The applicant first argues, with respect to claim 1, that Sabol does not disclose changes of logical addresses during data migration. However, Sabol et al. discloses in paragraphs [0091], [0095] and [0098], for example, that a write request includes logical addressing with source and destination addresses and that as data is moved from the source location to the destination location, the mapping table is updated to reflect the new logical and physical address mapping.
The applicant next argues, with respect to claim 3, that Sabol does not disclose an internal controller mechanism that maps a new logical address directly to an already occupied physical storage space. This claim does not appear to require this interpretation. Claim 3 is being interpreted as a mapping relationship established between the second logical address and the physical storage space of the data (which can just be a large storage area that includes the data) where this physical storage space also as correspondence (some broad relationship) to the first logical address. As stated in the rejection and directly above in the previous paragraph, Sabol discloses updating address mappings of where data is moved to from its previous storage location and the memories involved in Sabol all have some correspondence/relationship to each other.
The applicant further argues, with respect to claim 24, that Sabol does not disclose garbage collection being performed by the memory system. Sabol discloses that the management module 114 may perform garbage collection. The memory system is not claimed to explicitly exclude this module form being a part of the memory system. It is performing memory management functions and therefore is considered part of the memory system, even if it is also part of the host.
The Tarunika reference was not used in the part of the claim rejections related to the arguments presented by the applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2136
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