DETAILED ACTION
This action is responsive to the amendments filed 10 Aug 2026. Claims 1, 3-6, 8, 11-17 and 19-20 are pending. Claims 1, 8 and 15 are independent. Claim 2, 7, 9, 10, 18 have been cancelled.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10 Aug 2026 has been entered.
Application Title
Applicant has accepted the below title as more descriptive of the invention.
“APPARATUSES SYSTEMS AND METHODS FOR LINKED BANK OPERATIONS AND BANK REFRESH ACTIVATIONS”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
1) According to applicant’s specification [0047], refresh commands can be “activation commands”; therefore the claimed “activation commands”, which can include at least refresh, read and write commands, which is a broader limitation than the limitation “a refresh operation”.
2) The limitation “linked activation command” can comprise multiple ACT messages simply strung together (or linked) and is not limited to a single, 36-bit string command, shown in applicant’s fig. 4, unless explicitly limited.
3) The ACT messages can occur on different days, and the ACT messages are not limited to serial, parallel or simultaneous execution unless explicitly limited.
Response to Arguments
Applicant’s arguments filed on 10 Aug 2026 have been fully considered. The previous 112(b) rejections have been overcome. Applicant’s arguments are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
1) According to applicant’s specification [0047], refresh commands can be “activation commands”; therefore the claimed “activation commands”, which can include at least refresh, read and write commands, which is a broader limitation than the limitation “a refresh operation”.
2) The limitation “linked activation command” can comprise multiple ACT messages simply strung together (or linked) and is not limited to a single, 36-bit string command, shown in applicant’s fig. 4, unless explicitly limited.
3) The ACT messages can occur on different days, and the ACT messages are not limited to serial, parallel or simultaneous execution unless explicitly limited.
4) The arguments presented are moot because new art, Madhukar N, has been used in this office action.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 has the limitation “the apparatus of claim 2”. However claim 2 was cancelled. The claim has been interpreted as depending on claim 1.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3 – 6, 8, 11 – 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Madhukar N, U.S. Patent Application Publication 2025/0217051 (“Madhukar”) in view of Bell, et al, U.S. Patent Application Publication 2022/0107905 (“Bell”).
Regarding claim 1, Madhukar teaches:
(Currently amended) An apparatus comprising: a plurality of memory banks including a first bank and a second bank, (Madhukar, fig 1, 2, “[0034] FIG. 1 illustrates an apparatus 100 incorporating a host 110, memories 150, and channels 190 coupling the host 110 and the memories 150. [0050] The memory system 250 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, Flash memory cells) that store values. The memory array 175 may be divided into a plurality of banks with each bank organized as a plurality of pages. [0052] The memory system 250 may use the command and address clock CK to clock ( e.g., to receive) the CAs. A signal connection for each of the signaling may include a pin at the host 110, a pin at the memory system 250, and a conductive trace or traces electrically connecting the pins.”; a memory device with multiple “memory banks”; that the multiple memory banks can be accessed using CAs command on the command bus, connected with pins, and clocked to receive the CAs commands).
a refresh control circuit configured to perform a refresh operation on the second bank responsive to the linked activation command. (Madhukar, fig 8A, 8B, “[0070] A refresh command may be configured to include instructions to perform a precharge, refresh, and activate operation on one or more rows of a particular bank of a flexible bank group or to a flexible bank of a particular bank group. … A bank to be precharged and refreshed may be indicated by bits BAO, BAl, BGO, and BGl of the third row of the chart 800. Bits dBAO, dBAl, dBGO, and dBGl may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and activate operation are to be performed, and which rows and/or banks to which the operations are to be applied.”; a single “refresh command” of fig 8A can be used to refresh operations and an activate operation).
the first bank and the second bank being members of a bank link group; (Madhukar, fig 8A, 8B, “[0071] If AB, dBA0, and dBAl are set to 111, the command may indicate that a precharge operation is to be performed on a row of a current bank of the bank pair and a corresponding row of another bank of the bank pair, that a refresh operation is to be performed on both banks of the bank pair, and an activate operation is to be applied to both the row of the current bank indicated by the BAO, BAl, BG0, and BGl bits and the corresponding row of the other bank indicated by the BAO, BAl, dBG0, and dBGl bits.”; that different banks in different bank pairs (bank link group) can be treated differently from the same command; in this case a 111 sequence refreshes and activates both banks; with a 110 or 101 sequence, one bank can be refreshed while the other bank is activated).
Madhukar does not explicitly teach:
a command decoder configured to receive a linked activation command and a bank address associated with the first bank;
a row decoder configured to activate a word line in the first bank responsive to the linked activation command; and.
Bell teaches:
a command decoder configured to receive a linked activation command and a bank address associated with the first bank; (Bell, fig 1, “[0019] In the illustrated embodiments below, the memory devices and systems are, for the sake of clarity and understanding, primarily described in the context of embedding refresh single bank commands (REFsb) into other commands issued to and/or received by a memory device. The command signals CMD may be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands.”; an explicit “command decoder” that accepts embedded commands to perform multiple commands, such as refresh and read/write with a single command).
a row decoder configured to activate a word line in the first bank responsive to the linked activation command; and (Bell, fig 1, 2, 4, “[0026] In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells (e.g., half memory banks, subarrays in a memory bank, etc.). In these and other embodiments, the memory regions of the memory array 150 can be arranged in one or more groups (e.g., one or more groups of memory banks, The selection of a word line WL may be performed by a row decoder 140, and the selection of a bit line BL may be performed by a column decoder 145. [0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read)”; that word lines, pages, and memory banks can be controlled with embedded commands comprising more than one memory operation).
In view of the teachings of Bell it would have been obvious for a person of ordinary skill in the art to apply the teachings of Bell to Madhukar before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Bell, in the same or in a similar field of endeavor with Madhukar, can combine Bell’s explicit embedded commands and Madhukar’s explicit merged command to operate multiple memory banks and memory groups. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 3, Madhukar, as modified by Bell, teaches the apparatus of claim 2.
Madhukar further teaches:
wherein a bit of the activation command indicates if the activation command is a linked activation command or a normal activation command, and (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks).
wherein when the activation command is a normal activation command, the refresh control circuit does not perform the refresh operation on the second bank. (Madhukar, fig 8A, 8B, “[0071] For example, when values of the bits marked AB, dBA0, dBAl, dBG0, and dBGl are all 1, the command may indicate that an all bank refresh operation is to be performed.”; set of bits all 1 indicates a “normal” all bank refresh command).
Regarding claim 4, Madhukar, as modified by Bell, teaches the apparatus of claim 1.
Madhukar further teaches wherein the bank address includes a linked bank address which specifies the second bank. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon).
Regarding claim 5, Madhukar, as modified by Bell, teaches the apparatus of claim 1.
Madhukar further teaches wherein the refresh control circuit is configured to perform a normal refresh operation, a targeted refresh operation, or skip performing the refresh operation as the refresh operation on the second bank. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon; that a “normal refresh” of all banks can be performed with the proper bit signals).
Regarding claim 6, Madhukar, as modified by Bell, teaches the apparatus of claim 1.
Bell further teaches wherein the command decoder is configured to receive (Bell, fig 1, “[0019] In the illustrated embodiments below, the memory devices and systems are, for the sake of clarity and understanding, primarily described in the context of embedding refresh single bank commands (REFsb) into other commands issued to and/or received by a memory device. The command signals CMD may be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands.”; an explicit “command decoder” that accepts embedded commands to perform multiple commands, such as refresh and read/write with a single command).
In view of the teachings of Bell it would have been obvious for a person of ordinary skill in the art to apply the teachings of Bell to Madhukar before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Bell, in the same or in a similar field of endeavor with Madhukar, can combine Bell’s explicit embedded commands and Madhukar’s explicit merged command to operate multiple memory banks and memory groups. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Madhukar teaches a second activation command and a second bank address associated with the second bank, the apparatus comprising a second refresh control circuit configured to perform a refresh operation on the first bank. (Madhukar, fig 5A, 5C, “As a result of the transmission of the merged command at block 544, additional opportunities at blocks 548 and 550 may be available for transmission of other commands from the host device to the memory system via the bus. As another example, a merged precharge command may include a command to perform a refresh operation on a first, current, bank and a second bank and a precharge operation on a first, current, row of the first bank and a second, corresponding, row, of the second bank, without including a command to perform an activate operation.”; that additional commands can be sent in the same time frame because of the reduced commands necessary to perform multiple steps with a single merged command of 8A-8B, that 2nd, 3rd and other commands can each be sent which can perform multiple operations on multiple word group pairs).
Regarding claim 8, Madhukar teaches:
(Currently Amended) A method comprising: receiving a linked activation command and a bank address; (Madhukar, fig 1, 2, “[0034] FIG. 1 illustrates an apparatus 100 incorporating a host 110, memories 150, and channels 190 coupling the host 110 and the memories 150. [0050] The memory system 250 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, Flash memory cells) that store values. The memory array 175 may be divided into a plurality of banks with each bank organized as a plurality of pages. [0052] The memory system 250 may use the command and address clock CK to clock ( e.g., to receive) the CAs. A signal connection for each of the signaling may include a pin at the host 110, a pin at the memory system 250, and a conductive trace or traces electrically connecting the pins.”; a memory device with multiple “memory banks”; that the multiple memory banks can be accessed using CAs command on the command bus, connected with pins, and clocked to receive the CAs commands).
performing a refresh operation in a second bank (Madhukar, fig 8A, 8B, “[0070] A refresh command may be configured to include instructions to perform a precharge, refresh, and activate operation on one or more rows of a particular bank of a flexible bank group or to a flexible bank of a particular bank group. … A bank to be precharged and refreshed may be indicated by bits BAO, BAl, BGO, and BGl of the third row of the chart 800. Bits dBAO, dBAl, dBGO, and dBGl may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and activate operation are to be performed, and which rows and/or banks to which the operations are to be applied.”; a single “refresh command” of fig 8A can be used to refresh operations and an activate operation).
which is in a same bank link group with the first bank responsive to the linked activation command. (Madhukar, fig 8A, 8B, “[0071] If AB, dBA0, and dBAl are set to 111, the command may indicate that a precharge operation is to be performed on a row of a current bank of the bank pair and a corresponding row of another bank of the bank pair, that a refresh operation is to be performed on both banks of the bank pair, and an activate operation is to be applied to both the row of the current bank indicated by the BAO, BAl, BG0, and BGl bits and the corresponding row of the other bank indicated by the BAO, BAl, dBG0, and dBGl bits.”; that different banks in different bank pairs (bank link group) can be treated differently from the same command; in this case a 111 sequence refreshes and activates both banks; with a 110 or 101 sequence, one bank can be refreshed while the other bank is activated).
Madhukar does not explicitly teach activating a word line in a first bank associated with the bank address responsive to the linked activation command; and.
Bell teaches activating a word line in a first bank associated with the bank address responsive to the linked activation command; and (Bell, fig 1, 2, 4, “[0026] In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells (e.g., half memory banks, subarrays in a memory bank, etc.). In these and other embodiments, the memory regions of the memory array 150 can be arranged in one or more groups (e.g., one or more groups of memory banks, The selection of a word line WL may be performed by a row decoder 140, and the selection of a bit line BL may be performed by a column decoder 145. [0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read)”; that word lines, pages, and memory banks can be controlled with embedded commands comprising more than one memory operation).
In view of the teachings of Bell it would have been obvious for a person of ordinary skill in the art to apply the teachings of Bell to Madhukar before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Bell, in the same or in a similar field of endeavor with Madhukar, can combine Bell’s explicit embedded commands and Madhukar’s explicit merged command to operate multiple memory banks and memory groups. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Madhukar, as modified by Bell, teaches the method of claim 8.
Madhukar further teaches:
further comprising: receiving a second linked activation command and a second bank address, (Madhukar, fig 5A, 5C, “As a result of the transmission of the merged command at block 544, additional opportunities at blocks 548 and 550 may be available for transmission of other commands from the host device to the memory system via the bus. As another example, a merged precharge command may include a command to perform a refresh operation on a first, current, bank and a second bank and a precharge operation on a first, current, row of the first bank and a second, corresponding, row, of the second bank, without including a command to perform an activate operation.”; that additional commands can be sent in the same time frame because of the reduced commands necessary to perform multiple steps with a single merged command of 8A-8B, that 2nd, 3rd and other commands can each be sent which can perform multiple operations on multiple word group pairs).
wherein the second bank address is associated with a third bank which is not in the same bank link group as the first bank or the second bank; activating a word line in the third bank responsive to the second linked activation command; and (Madhukar, fig 1, “[0046] In some examples, the memories 150-1-150-4 may be LPDDR DRAM… In FIG. 1, four channels are shown, however the apparatus 100 may include more or less channels, such as 8 or 16 channels.”; that multiple memory arrays can be controlled by the same controller, that each can be controlled independently similar to the single memory array 250 of fig 2).
performing a refresh operation in a fourth bank which is in a second bank link group with the third bank responsive to the linked activation command. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon; that the same actions can be performed on a memory bank pair, or that different operations can be performed on memory bank pairs).
Regarding claim 12, Madhukar, as modified by Bell, teaches the method of claim 8.
Madhukar further teaches further comprising determining whether or not to perform the refresh operation. (Madhukar, fig 5A, 5C, “[0065] An example flow diagram 520 of a sequence of commands including a merged refresh command is shown in FIG. 5B. For example, at block 522, a read command for bank 0, row 0, column 64 may be transmitted from a host device to a memory system, such as to a memory controller of a memory system, via a bus, such as a command bus.”; a sequence 520 using the same command structure of fig 8A-8B which does not perform a refresh operation).
Regarding claim 13, Madhukar, as modified by Bell, teaches the method of claim 12.
Madhukar further teaches further comprising performing a normal refresh operation, at least one targeted refresh operation, or combinations thereof as the refresh operation. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon; that a “normal refresh” of all banks can be performed with the proper bit signals).
Regarding claim 14, Madhukar, as modified by Bell, teaches the method of claim 8.
Madhukar further teaches receiving an activation command and determining if the activation command is a normal activation command or a linked activation command based on at least one bit of the activation command. (Madhukar, fig 8A, 8B, “[0070] A refresh command may be configured to include instructions to perform a precharge, refresh, and activate operation on one or more rows of a particular bank of a flexible bank group or to a flexible bank of a particular bank group. … A bank to be precharged and refreshed may be indicated by bits BAO, BAl, BGO, and BGl of the third row of the chart 800. Bits dBAO, dBAl, dBGO, and dBGl may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and activate operation are to be performed, and which rows and/or banks to which the operations are to be applied.”; a single “refresh command” of fig 8A can be used to refresh operations and an activate operation; that the bits direct the memory system which of plural operations should be performed on which of plural word banks or word group pairs).
Regarding claim 15, Madhukar teaches:
(Currently amended) An apparatus comprising: a plurality of memory banks; a command address input circuit configured to receive a linked activation command, a bank address, and a linked bank address; a row decoder (Madhukar, fig 1, 2, “[0034] FIG. 1 illustrates an apparatus 100 incorporating a host 110, memories 150, and channels 190 coupling the host 110 and the memories 150. [0050] The memory system 250 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, Flash memory cells) that store values. The memory array 175 may be divided into a plurality of banks with each bank organized as a plurality of pages. [0052] The memory system 250 may use the command and address clock CK to clock ( e.g., to receive) the CAs. A signal connection for each of the signaling may include a pin at the host 110, a pin at the memory system 250, and a conductive trace or traces electrically connecting the pins.”; a memory device with multiple “memory banks”; that the multiple memory banks can be accessed using CAs command on the command bus, connected with pins, and clocked to receive the CAs commands).
a refresh control circuit configured to perform a refresh operation on a second memory bank of the plurality of memory banks responsive to the linked activation command, (Madhukar, fig 8A, 8B, “[0070] A refresh command may be configured to include instructions to perform a precharge, refresh, and activate operation on one or more rows of a particular bank of a flexible bank group or to a flexible bank of a particular bank group. … A bank to be precharged and refreshed may be indicated by bits BAO, BAl, BGO, and BGl of the third row of the chart 800. Bits dBAO, dBAl, dBGO, and dBGl may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and activate operation are to be performed, and which rows and/or banks to which the operations are to be applied.”; a single “refresh command” of fig 8A can be used to refresh operations and an activate operation).
wherein the second memory bank is associated with the linked bank address and is in a bank link group with the first memory bank. (Madhukar, fig 8A, 8B, “[0071] If AB, dBA0, and dBAl are set to 111, the command may indicate that a precharge operation is to be performed on a row of a current bank of the bank pair and a corresponding row of another bank of the bank pair, that a refresh operation is to be performed on both banks of the bank pair, and an activate operation is to be applied to both the row of the current bank indicated by the BAO, BAl, BG0, and BGl bits and the corresponding row of the other bank indicated by the BAO, BAl, dBG0, and dBGl bits.”; that different banks in different bank pairs (bank link group) can be treated differently from the same command; in this case a 111 sequence refreshes and activates both banks; with a 110 or 101 sequence, one bank can be refreshed while the other bank is activated; Note: nothing in the claim prevents both a refresh and activation to be performed on BOTH memory banks).
Madhukar does not explicitly teach configured to activate word line in a first memory bank of the plurality of memory banks responsive to the linked activation command, wherein the first memory bank is associated with the bank address; and.
Bell teaches configured to activate word line in a first memory bank of the plurality of memory banks responsive to the linked activation command, wherein the first memory bank is associated with the bank address; and (Bell, fig 1, 2, 4, “[0026] In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells (e.g., half memory banks, subarrays in a memory bank, etc.). In these and other embodiments, the memory regions of the memory array 150 can be arranged in one or more groups (e.g., one or more groups of memory banks, The selection of a word line WL may be performed by a row decoder 140, and the selection of a bit line BL may be performed by a column decoder 145. [0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read)”; that word lines, pages, and memory banks can be controlled with embedded commands comprising more than one memory operation).
In view of the teachings of Bell it would have been obvious for a person of ordinary skill in the art to apply the teachings of Bell to Madhukar before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Bell, in the same or in a similar field of endeavor with Madhukar, can combine Bell’s explicit embedded commands and Madhukar’s explicit merged command to operate multiple memory banks and memory groups. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Madhukar, as modified by Bell, teaches the apparatus of claim 15.
Madhukar further teaches wherein the command address input circuit is configured to receive a command address packet which includes the linked activation command, the bank address, the linked bank address, and a row address. (Madhukar, fig 5A, 5C, “For example, at block 562, a merged read command, such as a command to perform a read operation, a precharge operation, a refresh operation, and an activate operation on one or more rows of one or more banks of the memory system may be transmitted from a host device to a memory system, such as to a memory controller of a memory system, via a bus, such as a command bus. For example, the read operation may be a read operation for bank 0, row 0, column 64, the precharge operation may be for bank 0, row 0, the refresh operation may be for bank 0, and the activate operation may be for bank 0, row 0.”; that the CMD contains all of the necessary information to perform all of the desired operations on the memory bank, or the correct row within the bank).
Regarding claim 17, Madhukar, as modified by Bell, teaches the apparatus of claim 16.
Madhukar further teaches wherein one or more bits of the command address packet is shared between the bank address and the linked bank address. (Madhukar, fig 8A, 8B, “[0070] A refresh command may be configured to include instructions to perform a precharge, refresh, and activate operation on one or more rows of a particular bank of a flexible bank group or to a flexible bank of a particular bank group. … A bank to be precharged and refreshed may be indicated by bits BAO, BAl, BGO, and BGl of the third row of the chart 800. Bits dBAO, dBAl, dBGO, and dBGl may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and activate operation are to be performed, and which rows and/or banks to which the operations are to be applied.”; a single “refresh command” of fig 8A can be used to refresh operations and an activate operation; that the bits direct the memory system which of plural operations should be performed on which of plural word banks or word group pairs; that the bits of the three command lines of the merged command detail multiple operations across multiple word banks and word bank pairs).
Regarding claim 19, Madhukar, as modified by Bell, teaches the apparatus of claim 15.
Madhukar further teaches wherein the refresh control circuit is configured to perform a normal refresh operation, one or more targeted refresh operations, or skip performing a refresh operation as the refresh operation on the second memory bank. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon; that a “normal refresh” of all banks can be performed with the proper bit signals).
Regarding claim 20, Madhukar, as modified by Bell, teaches the apparatus of claim 15.
Madhukar further teaches wherein the command address input circuit is further configured to receive a normal activation command and the bank address, and wherein the row decoder is configured to activate the word line in the first memory bank responsive to the normal activation command and the refresh control circuit is configured to not perform the refresh operation responsive to the normal activation command. (Madhukar, fig 8A, 8B, “[0071] For example, the bit values and corresponding operations of FIG. SB may correspond to a configuration of a memory device and/or host to support a fixed bank for the operations but allow for selection of banks having a same bank number from different bank groups. For example, a current bank of a bank pair to which a precharge and/or refresh operation is to be applied may be indicated by bits BAO, BAl, BG0 and BGl, while another bank in the bank pair may be indicated by BAO, BAl, dBG0 and dBGl, allowing for flexible selection of bank groups for the bank pair using dBG0 and dBGl with a particular bank fixed by the values of BAO and BAl.”; the individual bits of figs 6A and 8A can indicate which merged commands should be performed on which memory banks or linked memory banks and specify which banks are acted upon; that a “normal refresh” of all banks can be performed with the proper bit signals).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
