DETAILED ACTION
This action is responsive to the application filed 31 Jul 2024 and the Information Disclosure Statement filed 1 Dec 2025. Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“APPARATUSES SYSTEMS AND METHODS FOR LINKED BANK OPERATIONS AND BANK REFRESH ACTIVATIONS”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Examiner’s notes
1) According to applicant’s specification [0047], refresh commands can be “activation commands”; therefore the claimed “activation commands”, which can include at least refresh, read and write commands, is a broader limitation than the limitation “a refresh operation”.
2) The limitation “linked activation command” can comprise multiple ACT messages strung together (or linked) and is not limited to a single, 36-bit string command, shown in applicant’s fig. 4, unless explicitly limited.
3) The ACT messages are not limited to parallel or simultaneous execution unless explicitly limited.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 5, 7, 8, and 12 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bell, et al, U.S. Patent Application Publication 2022/0107905 (“Bell”).
Regarding claim 1, Bell teaches:
An apparatus comprising: a plurality of memory banks including a first bank and a second bank; (Bell, fig 1, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells.”; a memory device with multiple “memory banks”).
a command decoder configured to receive an activation command a bank address associated with the first bank; (Bell, fig 1, “[0025] The command signals CMD may be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations,”; a command decoder 115 that can receive commands. As stated in Examiner Notes above, an activation command can comprise refresh, read and write commands).
a refresh control circuit configured to perform a refresh operation on the second bank responsive to the activation command. (Bell, fig 3, 4, “[0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read) or a read auto precharge command (Read AP) in accordance with various embodiments of the present technology…. The first set command/address bits can be the same or different from the second set of command/address bits… In other words, assuming that the refresh command embedded into the read auto precharge+refresh command (Read APR) of FIG. 4 is a refresh single bank command (REFsb) directed to memory bank BO of the memory array 150, the memory device 100 proceeds to perform the same sequence of operations as illustrated in FIG. 3 but with two fewer commands”; that a single command can comprise two actions; that one of the actions can be a refresh command for a specific bank; that the specific bank can be different then the read bank. Note: the claimed “first bank” and “second bank” have been interpreted as different “banks”, but the banks can overlap unless explicitly limited).
Regarding claim 2, Bell teaches The apparatus of claim 1, wherein the activation command is a linked activation command. (Bell, fig 3, 4, “[0039] Therefore, by embedding the refresh command ( e.g., a refresh single bank command (REFsb) or another refresh command) into a read command (Read) or into a read auto precharge command (Read AP), the memory system 190 reduces the amount of command/address bus bandwidth utilized to refresh one or more memory banks of the memory array 150.”; that a single command can comprise two actions; that one of the actions can be a refresh command for a specific bank; that the specific bank can be different then the read bank. Note: as stated in examiner’s notes, the “linked activation command” can be two run-on separate commands with 2 times the bandwidth of a single command).
Regarding claim 3, Bell teaches:
The apparatus of claim 2, wherein a bit of the activation command indicates if the activation command is a linked activation command or a normal activation command, and (Bell, table 1, “[0043] Referring to Table 1 above as an example, the memory device 100 can monitor the command/address bit 12 of read commands (Read), a read auto precharge commands (Read AP), a write commands (Write), and/or a write auto precharge commands (Write AP) received over the command/address bus.”; that a single bit, here “bit 12” of the command is “embedded” in the typical command, that “bit 12” indicates the operations to be performed).
wherein when the activation command is a normal activation command, the refresh control circuit does not perform the refresh operation on the second bank. (Bell, table 1, “[0043] When the command/address bit 12 is asserted, the memory device can execute a refresh command after executing the corresponding read command (Read), the read auto precharge command (Read AP), the write command (Write), and/or a write auto precharge command (Write AP)… On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; if bit 12 is asserted, then the original command and an associated refresh is performed; if bit 12 is not asserted, then only the original command is performed).
Regarding claim 4, Bell teaches The apparatus of claim 1, wherein the bank address includes a linked bank address which specifies the second bank. (Bell, fig 3, 4, “[0039] The first set command/address bits can be the same or different from the second set of command/address bits. In response to the first set of command/address bits of the read auto precharge+refresh command (Read APR), the memory device 100 proceeds to read data from the memory array 150 and/or precharge all or a portion of the memory array 150. In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150.”; that the address bits for the first and second commands can be different or the same; that the first set of addresses can be all or part of the memory array 150; and that the second set can be a different set of addresses that comprise all or a part of the memory array 150).
Regarding claim 5, Bell teaches The apparatus of claim 1, wherein the refresh control circuit is configured to perform a normal refresh operation, a targeted refresh operation, or skip performing the refresh operation as the refresh operation on the second bank. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 7, Bell teaches The apparatus of claim 1, further comprising a row decoder configured to activate a word line in the first bank. (Bell, fig 1, “[0026] The memory cells of the memory array 150 may be arranged in a plurality of memory regions, and each memory region may include a plurality of word lines (WL),… In some embodiments, a memory region can be one or more memory banks… The selection of a word line WL may be performed by a row decoder 140,”; a memory array 150 can be arranged in a plurality of regions of memory cells; that the region can comprise plural word lines; that the region of plural wordlines can be selected as discussed in claim 1, that the selected wordlines can be actuated using a row decoder 140 for either refresh or other operations using row addresses).
Regarding claim 8, Bell teaches:
A method comprising: receiving a linked activation command and a bank address; (Bell, fig 1, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells… The selection of a word line WL may be performed by a row decoder 140,”; a memory device with multiple “memory banks”; that the memory banks can be accessed using wordlines and WL row decoders).
activating a word line in a first bank associated with the bank address responsive to the linked activation command; and (Bell, fig 1, “[0025] The command signals CMD may be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations,”; a command decoder 115 that can receive commands. As stated in Examiner Notes above, an activation command can comprise refresh, read and write commands).
performing a refresh operation in a second bank which is in a bank link group with the first bank responsive to the linked activation command. (Bell, fig 3, 4, “[0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read) or a read auto precharge command (Read AP) in accordance with various embodiments of the present technology…. The first set command/address bits can be the same or different from the second set of command/address bits… In other words, assuming that the refresh command embedded into the read auto precharge+refresh command (Read APR) of FIG. 4 is a refresh single bank command (REFsb) directed to memory bank BO of the memory array 150, the memory device 100 proceeds to perform the same sequence of operations as illustrated in FIG. 3 but with two fewer commands”; that a single command can comprise two actions; that one of the actions can be a refresh command for a specific bank; that the specific bank can be different then the read bank. Note: the claimed “first bank” and “second bank” have been interpreted as different “banks”, but the banks can overlap unless explicitly limited).
Regarding claim 12, Bell teaches The method of claim 8, further comprising determining whether or not to perform the refresh operation. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 13, Bell teaches The method of claim 12, further comprising performing a normal refresh operation, at least one targeted refresh operation, or combinations thereof as the refresh operation. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 14, Bell teaches The method of claim 8, receiving an activation command and determining if the activation command is a normal activation command or a linked activation command based on at least one bit of the activation command. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 15, Bell teaches:
An apparatus comprising: a plurality of memory banks; a command address input circuit configured to receive a linked activation command, a bank address, and a linked bank address; a row decoder (Bell, fig 1, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells… The selection of a word line WL may be performed by a row decoder 140,”; a memory device with multiple “memory banks”; that the memory banks can be accessed using wordlines and WL row decoders).
configured to activate word line in a first memory bank of the plurality of memory banks, wherein the first memory bank is associated with the bank address; and (Bell, fig 1, “[0025] The command signals CMD may be provided as internal command signals ICMD to a command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations,”; a command decoder 115 that can receive commands. As stated in Examiner Notes above, an activation command can comprise refresh, read and write commands).
a refresh control circuit configured to perform a refresh operation on a second memory bank of the plurality of memory banks, wherein the second memory bank is associated with the linked bank address. (Bell, fig 3, 4, “[0039] FIG. 4 is a timing diagram 420 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a read command (Read) or a read auto precharge command (Read AP) in accordance with various embodiments of the present technology…. The first set command/address bits can be the same or different from the second set of command/address bits… In other words, assuming that the refresh command embedded into the read auto precharge+refresh command (Read APR) of FIG. 4 is a refresh single bank command (REFsb) directed to memory bank BO of the memory array 150, the memory device 100 proceeds to perform the same sequence of operations as illustrated in FIG. 3 but with two fewer commands”; that a single command can comprise two actions; that one of the actions can be a refresh command for a specific bank; that the specific bank can be different then the read bank. Note: the claimed “first bank” and “second bank” have been interpreted as different “banks”, but the banks can overlap unless explicitly limited).
Regarding claim 16, Bell teaches The apparatus of claim 15, wherein the command address input circuit is configured to receive a command address packet which includes the linked activation command, the bank address, the linked bank address, and a row address. (Bell, fig 3, 4, “[0039] As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a read auto precharge+ refresh command (Read APR). A first set of (e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a read operation and/or a precharge operation, and a second set of ( e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a refresh operation. The first set command/address bits can be the same or different from the second set of command/address bits.”; that a command can comprise a command with comprises a first set of commands and addresses along with a second set of commands and a second set of address; that the first and second commands can be different; that the fist and second address banks can be different).
Regarding claim 17, Bell teaches The apparatus of claim 16, wherein one or more bits of the command address packet is shared between the bank address and the linked bank address. (Bell, table 1, “[0043] When the command/address bit 12 is asserted, the memory device can execute a refresh command after executing the corresponding read command (Read), the read auto precharge command (Read AP), the write command (Write), and/or a write auto precharge command (Write AP)… On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; if bit 12 is asserted, then the original command and an associated refresh is performed; if bit 12 is not asserted, then only the original command is performed).
Regarding claim 18, Bell teaches The apparatus of claim 15, wherein the first memory bank and the second memory bank are part of different bank groups. (Bell, fig 3, 4, “[0039] As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a read auto precharge+ refresh command (Read APR). A first set of (e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a read operation and/or a precharge operation, and a second set of ( e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a refresh operation. The first set command/address bits can be the same or different from the second set of command/address bits.”; that a command can comprise a command with comprises a first set of commands and addresses along with a second set of commands and a second set of address; that the first and second commands can be different; that the fist and second address banks can be different. Note: “different” does not explicitly prevent the first and second addresses from overlapping, merely that they be different).
Regarding claim 19, Bell teaches The apparatus of claim 15, wherein the refresh control circuit is configured to perform a normal refresh operation, one or more targeted refresh operations, or skip performing a refresh operation as the refresh operation on the second memory bank. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 20, Bell teaches The apparatus of claim 15, wherein the command address input circuit is further configured to receive a normal activation command and the bank address, and wherein the row decoder is configured to activate the word line in the first memory bank responsive to the normal activation command and the refresh control circuit is configured to not perform the refresh operation responsive to the normal activation command. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 6, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bell in view of SU, et al, U.S. Patent Application Publication 2024/0078202 (“SU”).
Regarding claim 6, Bell teaches the apparatus of claim 1.
Bell does not explicitly teach:
wherein the command decoder is configured to receive a second activation command and a second bank address associated with the second bank,
the apparatus comprising a second refresh control circuit configured to perform a refresh operation on the first bank..
SU teaches:
wherein the command decoder is configured to receive a second activation command and a second bank address associated with the second bank, (SU, fig 2, “[0011] Some aspects may further include receiving, at the first partial channel interface, a first signal configured to indicate to the first memory device of the logical rank to implement a first memory access command via the first partial channel, receiving, at the second partial channel interface, a second signal configured to indicate to the second memory device of the logical rank to implement a second memory access command via the second partial channel, implementing, via the first partial channel, the first memory access command at the first memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device, and implementing, via the second partial channel, the second memory access command at the second memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.”; that two commands can perform a “command then refresh” sequence on one portion of a memory array, and perform a “refresh then command” sequence on a second portion of a memory array).
the apparatus comprising a second refresh control circuit configured to perform a refresh operation on the first bank. (SU, fig 14A, 14B, “ [0110] FIGS. 14A and 14B illustrate methods for implementing memory access and refresh using ranks or logical ranks in a memory system according to some embodiments. [0112] With reference to FIG. 14A, in block 1402, the flexible rank memory device may receive signals for memory access at different partial channels of a same memory. [0115] In block 1408, the flexible rank memory device may implement refresh operations at the first partial channel of the same memory of the rank. [0117] In block 1412, the flexible rank memory device may implement refresh operations at the second partial channel of the same memory of the rank. [0144] As will be appreciated by one of skill in the art the order of operations in the foregoing embodiments may be performed in any order.”; that the commands can be performed in any order, that the command can come before the refresh, or vice versa, that the commands can go to both memory partial channels followed by two refresh cycles, or that the commands can be alternated with refresh operations).
In view of the teachings of SU it would have been obvious for a person of ordinary skill in the art to apply the teachings of SU to Bell before the effective filing date of the claimed invention in order to teach multiple operations at a memory array. The teachings of SU, in the same or in a similar field of endeavor with Bell, can combine SU’s explicit commands on two memory banks with Bell’s implied commands on two memory banks. The two operations, performed in any order merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Bell teaches the method of claim 8.
Bell does not explicitly teach:
further comprising: receiving a second activation command and a second bank address a first time after receiving the linked activation command
if the second bank address is associated with a different bank link group than the first bank or a second time after receiving the linked activation command if the second bank address is associated with a same bank link group as the first bank..
SU teaches:
further comprising: receiving a second activation command and a second bank address a first time after receiving the linked activation command (SU, fig 2, “[0011] Some aspects may further include receiving, at the first partial channel interface, a first signal configured to indicate to the first memory device of the logical rank to implement a first memory access command via the first partial channel, receiving, at the second partial channel interface, a second signal configured to indicate to the second memory device of the logical rank to implement a second memory access command via the second partial channel, implementing, via the first partial channel, the first memory access command at the first memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device, and implementing, via the second partial channel, the second memory access command at the second memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.”; that two commands can perform a “command then refresh” sequence on one portion of a memory array, and perform a “refresh then command” sequence on a second portion of a memory array).
if the second bank address is associated with a different bank link group than the first bank or a second time after receiving the linked activation command if the second bank address is associated with a same bank link group as the first bank. (SU, fig 14A, 14B, “ [0110] FIGS. 14A and 14B illustrate methods for implementing memory access and refresh using ranks or logical ranks in a memory system according to some embodiments. [0112] With reference to FIG. 14A, in block 1402, the flexible rank memory device may receive signals for memory access at different partial channels of a same memory. [0115] In block 1408, the flexible rank memory device may implement refresh operations at the first partial channel of the same memory of the rank. [0117] In block 1412, the flexible rank memory device may implement refresh operations at the second partial channel of the same memory of the rank. [0144] As will be appreciated by one of skill in the art the order of operations in the foregoing embodiments may be performed in any order.”; that the commands can be performed in any order, that the command can come before the refresh, or vice versa, that the commands can go to both memory partial channels followed by two refresh cycles, or that the commands can be alternated with refresh operations).
In view of the teachings of SU it would have been obvious for a person of ordinary skill in the art to apply the teachings of SU to Bell before the effective filing date of the claimed invention in order to teach multiple operations at a memory array. The teachings of SU, in the same or in a similar field of endeavor with Bell, can combine SU’s explicit commands on two memory banks with Bell’s implied commands on two memory banks. The two operations, performed in any order merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Bell teaches the method of claim 8.
Bell teaches further comprising: receiving a second linked activation command and a second bank address, (Bell, fig 6, “[0041] FIG. 6 is a timing diagram 620 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a write command (Write) or a write auto precharge command (Write AP) in accordance with various embodiments of the present technology.”; that a memory controller can process more than one command on more than one set of bank addresses; that a second operation can include a write operation or a subsequent read operation of figure 4).
Bell does not explicitly teach:
wherein the second bank address is associated with a third bank which is not in the same bank link group as the first bank or the second bank; activating a word line in the third bank responsive to the second linked activation command; and
performing a refresh operation in a fourth bank which is in a second bank link group with the third bank responsive to the linked activation command..
SU teaches:
wherein the second bank address is associated with a third bank which is not in the same bank link group as the first bank or the second bank; activating a word line in the third bank responsive to the second linked activation command; and (SU, fig 4, “[0058] FIG. 4 illustrates an example memory system 400 ( e.g., memory system 200 in FIG. 2) having a logical rank structure based on partial channels of a memory device. [0110] FIGS. 14A and 14B illustrate methods for implementing memory access and refresh using ranks or logical ranks in a memory system according to some embodiments. [0112] With reference to FIG. 14A, in block 1402, the flexible rank memory device may receive signals for memory access at different partial channels of a same memory. [0115] In block 1408, the flexible rank memory device may implement refresh operations at the first partial channel of the same memory of the rank. [0117] In block 1412, the flexible rank memory device may implement refresh operations at the second partial channel of the same memory of the rank. [0144] As will be appreciated by one of skill in the art the order of operations in the foregoing embodiments may be performed in any order.”; that a memory controller can comprise four separate logical rank structures; that the operations can be explicitly looped as shown in fig 14A and 14B).
performing a refresh operation in a fourth bank which is in a second bank link group with the third bank responsive to the linked activation command. (SU, fig 2, “[0056] As another example, for chip select signals received via the chip select bus 228b, different values may indicate to the partial channel 1 interface 214b to activate the memory banks 216b and/or implement the memory access commands at the memory banks 216b of one of the memory devices 212a, 212b.”; that different memory banks 216a-b can be accessed, can be refreshed, that read/write operations can be performed on the memory array).
In view of the teachings of SU it would have been obvious for a person of ordinary skill in the art to apply the teachings of SU to Bell before the effective filing date of the claimed invention in order to teach multiple operations at a memory array. The teachings of SU, in the same or in a similar field of endeavor with Bell, can combine SU’s explicit commands on two memory banks with Bell’s implied commands on two memory banks. The two operations, performed in any order merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825