DETAILED ACTION
This action is responsive to the amendments filed 11 May 2026. Claims 1-17 and 19-20 are pending. Claims 1, 8 and 15 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“APPARATUSES SYSTEMS AND METHODS FOR LINKED BANK OPERATIONS AND BANK REFRESH ACTIVATIONS”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Response to Amendment
The Amendment filed 11 May 2026 has been entered. Claims 1-17 and 19-20 are currently pending in the application.
Examiner’s notes
1) According to applicant’s specification [0047], refresh commands can be “activation commands”; therefore the claimed “activation commands”, which can include at least refresh, read and write commands, which is a broader limitation than the limitation “a refresh operation”.
2) The limitation “linked activation command” can comprise multiple ACT messages strung together (or linked) and is not limited to a single, 36-bit string command, shown in applicant’s fig. 4, unless explicitly limited.
3) The ACT messages can occur on different days, and the ACT messages are not limited to serial, parallel or simultaneous execution unless explicitly limited.
Response to Arguments
Applicant’s arguments filed on 11 May 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The Applicant states “The independent claims are amended to clarify the relationship between the first memory bank and the second memory bank. For example, the first memory bank and the second memory bank are in the same bank link group. The bank link groups are defined such that activation of one memory bank in the bank link group permits another memory bank in the same bank link group to perform refresh operation.
In contrast, Bell describes refresh behavior that is explicitly indicated by command and address bits and executed as part of a commanded operation sequence.”
Response 1: The Examiner respectfully disagrees. However, a new reference, Deshmukh has been added to this office action which teaches that at least two memory banks can be included in the same memory “bank group”.
Argument 2: The Applicant states “Claim 10 was objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form…”
Response 2: The Examiner respectfully notes that the amendments to claim 8 have introduced a 112(b) rejection into claim 9. As such, claim 10 was rejected with both the 112(b) associated with claim 9 and the art cited necessitated by applicant’s amendment to claim 8.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 9 is rejected. Amended claim 8 states, “performing a refresh operation in a second bank which is in a same bank link group with the first bank responsive to the linked activation command. However, claim 9 states, “if the second bank address is associated with a different bank link group…” Claim 9 is indefinite because the second bank address cannot be both in the same bank line group and in a different bank group link.
Claim 10 depends on rejected claim 9 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 10 and 12 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bell, et al, U.S. Patent Application Publication 2022/0107905 (“Bell”) in view of Deshmukh, et al, U.S. Patent Application Publication 2023/0305971 (“Deshmukh”).
Regarding claim 1, Bell teaches:
(Currently Amended) An apparatus comprising: a plurality of memory banks including a first bank and a second bank, (Bell, fig 1, 7, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL)… In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells. [0016] For example, a refresh ‘single bank’ command (REFsb) can be issued to a memory device following a read or write command. … In this manner, the memory systems of the present technology can issue and/or the memory devices of the present technology can receive refresh commands with minimal and/or reduced consumption of command/address bus bandwidth by embedding the refresh commands into other commands transmitted over the command/address bus. [0039] In this manner, the memory system 190 can issue (and/or the memory device 100 can receive) refresh single bank commands (REFsb) to refresh memory banks of the memory array 150 while keeping other memory banks of the memory array 150 available for reading or writing data and/or for other operations with minimal and/or reduced consumption of command/address bus bandwidth.”; a memory device with multiple “memory banks”; that the memory banks can be accessed using wordlines and WL row decoders; that the memory banks can comprise a memory bank group).
a command decoder configured to receive an activation command and a bank address associated with the first bank; (Bell, fig 1, 5, “[0038] To address this concern, the memory system 190 can embed refresh single bank commands (REFsb) and/or other refresh commands into one or more other commands (e.g., read, write, and/or other commands) issued to and/or received by the memory device 100 over the command/ address bus. [0040] FIG. 5 is a timing diagram 520 illustrating command/ address bus utilization under this example in accordance with various embodiments of the present technology. As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a write command (Write). Once data is written to the memory array 150, a precharge command (Pre) is sent to and/or received by the memory device 100 to precharge all or a portion of the memory array 150 for a refresh operation performed by the memory device 100 in response to receiving a subsequent refresh command, such as a refresh single bank command (REFsb).”; a command decoder 115 that can receive commands. Bell teaches a single command to perform a write, pre-charge, and refresh of a memory bank B0. See Examiner note where applicant’s claimed “activation command” can comprise a generic refresh command).
and a refresh control circuit configured to perform a refresh operation on the second bank responsive to the activation command. (Bell, fig 1, 5, “[0040] As another example, a refresh single bank command (REFsb) and/or another refresh command can be issued to the memory device 100 following a write command. [0037] In some embodiments, refresh single bank commands (REFsb) can be used in addition to or in lieu of refresh all banks commands (REFab)”; a command decoder that can include either the single bank REFsb command or a “refresh all’ REFab command which would refresh all of the memory banks, including all of the memory banks in all groups, which comprise the second bank).
Bell does not explicitly teach the first bank and the second bank being members of a bank link group;.
Deshmukh teaches the first bank and the second bank being members of a bank link group; (Deshmukh, fig 3A-C, “[0041] An overview of an improved memory device 300 is illustrated in FIGS. 3A-3C. … In this regard, FIG. 3A illustrates the memory device 300 that has a first memory block 302A having eight bank groups (BG), each with two banks and a second memory block 302B also having eight bank groups (BG), each with two banks, [0042] Thus, the REFpb command, as illustrated in FIG. 3C may operate on bank 306A(l)/306A(9) and concurrently on bank 306B(l)/ 3068(9).”; that a memory block 302A can be partitioned into multiple banks; that the block 302A can have 8 bank groups, that each bank group can have two banks; that each bank can have multiple rows; that a REFpb command can refresh at least four rows within the two banks using a single REFpb command).
In view of the teachings of Deshmukh it would have been obvious for a person of ordinary skill in the art to apply the teachings of Deshmukh to Bell before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Deshmukh, in the same or in a similar field of endeavor with Bell, can combine Deshmukh’s explicit refresh of multiple rows in a “bank group” and Bell’s implied refresh of multiple banks using a single command. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 2, Bell, as modified by Deshmukh, teaches the apparatus of claim 1.
Bell further teaches wherein the activation command is a linked activation command. (Bell, fig 3, 5, “[0039] Therefore, by embedding the refresh command ( e.g., a refresh single bank command (REFsb) or another refresh command) into a read command (Read) or into a read auto precharge command (Read AP), the memory system 190 reduces the amount of command/address bus bandwidth utilized to refresh one or more memory banks of the memory array 150.”; that a single command can comprise the three actions of fig 5; that one of the actions can be a refresh command for a specific bank; that the specific bank can be different then the read bank. Note: as stated in examiner’s notes, the “linked activation command” can be two run-on separate commands with 2 times the bandwidth of a single command).
Regarding claim 3, Bell, as modified by Deshmukh, teaches the apparatus of claim 2.
Bell further teaches:
wherein a bit of the activation command indicates if the activation command is a linked activation command or a normal activation command, and (Bell, table 1, “[0043] Referring to Table 1 above as an example, the memory device 100 can monitor the command/address bit 12 of read commands (Read), a read auto precharge commands (Read AP), a write commands (Write), and/or a write auto precharge commands (Write AP) received over the command/address bus.”; that a single bit, here “bit 12” of the command is “embedded” in the typical command, that “bit 12” indicates the operations to be performed).
wherein when the activation command is a normal activation command, the refresh control circuit does not perform the refresh operation on the second bank. (Bell, table 1, “[0043] When the command/address bit 12 is asserted, the memory device can execute a refresh command after executing the corresponding read command (Read), the read auto precharge command (Read AP), the write command (Write), and/or a write auto precharge command (Write AP)… On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; if bit 12 is asserted, then the original command and an associated refresh is performed; if bit 12 is not asserted, then only the original command is performed).
Regarding claim 4, Bell, as modified by Deshmukh, teaches the apparatus of claim 1.
Bell further teaches wherein the bank address includes a linked bank address which specifies the second bank. (Bell, fig 3, 4, 5, “[0039] The first set command/address bits can be the same or different from the second set of command/address bits. In response to the first set of command/address bits of the read auto precharge+ refresh command (Read APR), the memory device 100 proceeds to read data from the memory array 150 and/or precharge all or a portion of the memory array 150. In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150.”; that the address bits for the first and second commands can be different or the same; that the first set of addresses can be all or part of the memory array 150; and that the second set can be a different set of addresses that comprise all or a part of the memory array 150; that the steps can include a REFab at the end of the read operation which refreshes ALL of the memory banks in the memory array which also includes the second bank of this array as opposed to bank in another array).
Regarding claim 5, Bell, as modified by Deshmukh, teaches the apparatus of claim 1.
Bell further teaches wherein the refresh control circuit is configured to perform a normal refresh operation, a targeted refresh operation, or skip performing the refresh operation as the refresh operation on the second bank. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (REFab- normal) or part (REFsb- targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed (skipped)).
Regarding claim 6, Bell, as modified by Deshmukh, teaches the apparatus of claim 1.
Bell further teaches:
wherein the command decoder is configured to receive a second activation command and a second bank address associated with the second bank, (Bell, fig 1, 5, “[0040] As another example, a refresh single bank command (REFsb) and/or another refresh command can be issued to the memory device 100 following a write command. [0037] In some embodiments, refresh single bank commands (REFsb) can be used in addition to or in lieu of refresh all banks commands (REFab). [0034] For example, the memory system 190 can be configured to supply one or more refresh connnands to the memory device 100 at least every 7.8 μs such that an approximate minimum of 4000 refresh connnands are supplied to the memory device 100 within a 32 ms time window.”; a command decoder that can include either the single bank REFsb command or a “refresh all’ REFab command which would refresh all of the memory banks, including all of the memory banks in all groups, which comprise the second bank; that a DRAM memory is continously refreshing all of the memory cells to maintain the charge on the memory cells).
the apparatus comprising a second refresh control circuit configured to perform a refresh operation on the first bank. (Bell, fig 3, 4, 5, “[0039] The first set command/address bits can be the same or different from the second set of command/address bits. In response to the first set of command/address bits of the read auto precharge+ refresh command (Read APR), the memory device 100 proceeds to read data from the memory array 150 and/or precharge all or a portion of the memory array 150. In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150.”; that the address bits for the first and second commands can be different or the same; that the first set of addresses can be all or part of the memory array 150; and that the second set can be a different set of addresses that comprise all or a part of the memory array 150; as quoted above, a REFab can be issued at the end of the fig 5 command which refreshes every memory bank in the memory array, which inludes every memory bank group).
Regarding claim 7, Bell, as modified by Deshmukh, teaches the apparatus of claim 1.
Bell further teaches further comprising a row decoder configured to activate a word line in the first bank. (Bell, fig 1, “[0026] The memory cells of the memory array 150 may be arranged in a plurality of memory regions, and each memory region may include a plurality of word lines (WL),… In some embodiments, a memory region can be one or more memory banks… The selection of a word line WL may be performed by a row decoder 140,”; a memory array 150 can be arranged in a plurality of regions of memory cells; that the region can comprise plural word lines; that the region of plural wordlines can be selected as discussed in claim 1, that the selected wordlines can be actuated using a row decoder 140 for either refresh or other operations using row addresses).
Regarding claim 8, Bell teaches:
(Currently Amended) A method comprising: receiving a linked activation command and a bank address; (Bell, fig 1, 7, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL)… In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells. [0016] For example, a refresh ‘single bank’ command (REFsb) can be issued to a memory device following a read or write command. … In this manner, the memory systems of the present technology can issue and/or the memory devices of the present technology can receive refresh commands with minimal and/or reduced consumption of command/address bus bandwidth by embedding the refresh commands into other commands transmitted over the command/address bus. [0039] In this manner, the memory system 190 can issue (and/or the memory device 100 can receive) refresh single bank commands (REFsb) to refresh memory banks of the memory array 150 while keeping other memory banks of the memory array 150 available for reading or writing data and/or for other operations with minimal and/or reduced consumption of command/address bus bandwidth.”; a memory device with multiple “memory banks”; that the memory banks can be accessed using wordlines and WL row decoders; that the memory banks can comprise a memory bank group).
activating a word line in a first bank associated with the bank address responsive to the linked activation command; and (Bell, fig 1, 5, “[0038] To address this concern, the memory system 190 can embed refresh single bank commands (REFsb) and/or other refresh commands into one or more other commands (e.g., read, write, and/or other commands) issued to and/or received by the memory device 100 over the command/ address bus. [0040] FIG. 5 is a timing diagram 520 illustrating command/ address bus utilization under this example in accordance with various embodiments of the present technology. As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a write command (Write). Once data is written to the memory array 150, a precharge command (Pre) is sent to and/or received by the memory device 100 to precharge all or a portion of the memory array 150 for a refresh operation performed by the memory device 100 in response to receiving a subsequent refresh command, such as a refresh single bank command (REFsb).”; a command decoder 115 that can receive commands. Bell teaches a single command to perform a write, pre-charge, and refresh of a memory bank B0. See Examiner note where applicant’s claimed “activation command” can comprise a generic refresh command).
performing a refresh operation in a second bank (Bell, fig 1, 5, “[0040] As another example, a refresh single bank command (REFsb) and/or another refresh command can be issued to the memory device 100 following a write command. [0037] In some embodiments, refresh single bank commands (REFsb) can be used in addition to or in lieu of refresh all banks commands (REFab)”; a command decoder that can include either the single bank REFsb command or a “refresh all’ REFab command which would refresh all of the memory banks, including all of the memory banks in all groups, which comprise the second bank).
Bell does not explicitly teach which is in a same bank link group with the first bank responsive to the linked activation command..
Deshmukh teaches which is in a same bank link group with the first bank responsive to the linked activation command. (Deshmukh, fig 3A-C, “[0041] An overview of an improved memory device 300 is illustrated in FIGS. 3A-3C. … In this regard, FIG. 3A illustrates the memory device 300 that has a first memory block 302A having eight bank groups (BG), each with two banks and a second memory block 302B also having eight bank groups (BG), each with two banks, [0042] Thus, the REFpb command, as illustrated in FIG. 3C may operate on bank 306A(l)/306A(9) and concurrently on bank 306B(l)/ 3068(9).”; that a memory block 302A can be partitioned into multiple banks; that the block 302A can have 8 bank groups, that each bank group can have two banks; that each bank can have multiple rows; that a REFpb command can refresh at least four rows within the two banks using a single REFpb command).
In view of the teachings of Deshmukh it would have been obvious for a person of ordinary skill in the art to apply the teachings of Deshmukh to Bell before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Deshmukh, in the same or in a similar field of endeavor with Bell, can combine Deshmukh’s explicit refresh of multiple rows in a “bank group” and Bell’s implied refresh of multiple banks using a single command. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Bell, as modified by Deshmukh, teaches the method of claim 8.
Bell further teaches:
further comprising: receiving a second activation command and a second bank address a first time after receiving the linked activation command (Bell, fig 2, “[0030] When a read command is issued, and a row address and a column address are timely supplied with the read command, read data can be read from memory cells in the memory array 150 designated by these row address and column address. [0040] FIG. 5 is a timing diagram 520 illustrating command/ address bus utilization under this example in accordance with various embodiments of the present technology. As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a write command (Write). Once data is written to the memory array 150, a precharge command (Pre) is sent to and/or received by the memory device 100 to precharge all or a portion of the memory array 150 for a refresh operation [0034] For example, the memory system 190 can be configured to supply one or more refresh connnands to the memory device 100 at least every 7.8 μs such that an approximate minimum of 4000 refresh connnands are supplied to the memory device 100 within a 32 ms time window.”; that different memory banks B0-B4 can be accessed in a memory array for reading the data stored within, that each and every memory bank is continuosly refreshed on a timed cycle).
if the second bank address is associated with a different bank link group than the first bank or a second time after receiving the linked activation command if the second bank address is associated with a same bank link group as the first bank. (Bell, fig 14A, 14B, “[0034] Regardless of the refresh approach, the memory device 100 can be configured to refresh memory cells in the memory array 150 within a given refresh rate or time window (e.g., 32 ms, 28 ms, 25 ms, 23 ms, 21 ms, 18 ms, 16 ms, 8 ms, etc.), known as tREF.”; that every memory cell can be refreshed in a memory array on a given refresh rate).
Regarding claim 10, Bell, as modified by Deshmukh, teaches the method of claim 9.
Bell further teaches wherein the first time is shorter than the second time. (Bell, fig 1, 5, “[0040] As another example, a refresh single bank command (REFsb) and/or another refresh command can be issued to the memory device 100 following a write command. [0037] In some embodiments, refresh single bank commands (REFsb) can be used in addition to or in lieu of refresh all banks commands (REFab)”; a command decoder that can include either the single bank REFsb command or a “refresh all’ REFab command which would refresh all of the memory banks, including all of the memory banks in all groups, which comprise the second bank; that the REFab would take longer than the REFsb as shown in fig 2A/ 2B).
Regarding claim 12, Bell, as modified by Deshmukh, teaches the method of claim 8.
Bell further teaches further comprising determining whether or not to perform the refresh operation. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 13, Bell, as modified by Deshmukh, teaches the method of claim 12.
Bell further teaches further comprising performing a normal refresh operation, at least one targeted refresh operation, or combinations thereof as the refresh operation. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 14, Bell, as modified by Deshmukh, teaches the method of claim 8.
Bell further teaches receiving an activation command and determining if the activation command is a normal activation command or a linked activation command based on at least one bit of the activation command. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 15, Bell teaches:
(Currently Amended) An apparatus comprising: a plurality of memory banks; a command address input circuit configured to receive a linked activation command, a bank address, and a linked bank address; a row decoder (Bell, fig 1, 7, “[0026] The memory device 100 may include an array of memory cells, … each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL)… In some embodiments, a memory region can be one or more memory banks or another arrangement of memory cells. [0016] For example, a refresh ‘single bank’ command (REFsb) can be issued to a memory device following a read or write command. … In this manner, the memory systems of the present technology can issue and/or the memory devices of the present technology can receive refresh commands with minimal and/or reduced consumption of command/address bus bandwidth by embedding the refresh commands into other commands transmitted over the command/address bus. [0039] In this manner, the memory system 190 can issue (and/or the memory device 100 can receive) refresh single bank commands (REFsb) to refresh memory banks of the memory array 150 while keeping other memory banks of the memory array 150 available for reading or writing data and/or for other operations with minimal and/or reduced consumption of command/address bus bandwidth.”; a memory device with multiple “memory banks”; that the memory banks can be accessed using wordlines and WL row decoders; that the memory banks can comprise a memory bank group).
configured to activate word line in a first memory bank of the plurality of memory banks, wherein the first memory bank is associated with the bank address; and (Bell, fig 1, 5, “[0038] To address this concern, the memory system 190 can embed refresh single bank commands (REFsb) and/or other refresh commands into one or more other commands (e.g., read, write, and/or other commands) issued to and/or received by the memory device 100 over the command/ address bus. [0040] FIG. 5 is a timing diagram 520 illustrating command/ address bus utilization under this example in accordance with various embodiments of the present technology. As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a write command (Write). Once data is written to the memory array 150, a precharge command (Pre) is sent to and/or received by the memory device 100 to precharge all or a portion of the memory array 150 for a refresh operation performed by the memory device 100 in response to receiving a subsequent refresh command, such as a refresh single bank command (REFsb).”; a command decoder 115 that can receive commands. Bell teaches a single command to perform a write, pre-charge, and refresh of a memory bank B0. See Examiner note where applicant’s claimed “activation command” can comprise a generic refresh command).
a refresh control circuit configured to perform a refresh operation on a second memory bank of the plurality of memory banks, (Bell, fig 1, 5, “[0040] As another example, a refresh single bank command (REFsb) and/or another refresh command can be issued to the memory device 100 following a write command. [0037] In some embodiments, refresh single bank commands (REFsb) can be used in addition to or in lieu of refresh all banks commands (REFab)”; a command decoder that can include either the single bank REFsb command or a “refresh all’ REFab command which would refresh all of the memory banks, including all of the memory banks in all groups, which comprise the second bank).
Bell does not explicitly teach wherein the second memory bank is associated with the linked bank address and is in a bank link group with the first memory bank..
Deshmukh teaches wherein the second memory bank is associated with the linked bank address and is in a bank link group with the first memory bank. (Deshmukh, fig 3A-C, “[0041] An overview of an improved memory device 300 is illustrated in FIGS. 3A-3C. … In this regard, FIG. 3A illustrates the memory device 300 that has a first memory block 302A having eight bank groups (BG), each with two banks and a second memory block 302B also having eight bank groups (BG), each with two banks, [0042] Thus, the REFpb command, as illustrated in FIG. 3C may operate on bank 306A(l)/306A(9) and concurrently on bank 306B(l)/ 3068(9).”; that a memory block 302A can be partitioned into multiple banks; that the block 302A can have 8 bank groups, that each bank group can have two banks; that each bank can have multiple rows; that a REFpb command can refresh at least four rows within the two banks using a single REFpb command).
In view of the teachings of Deshmukh it would have been obvious for a person of ordinary skill in the art to apply the teachings of Deshmukh to Bell before the effective filing date of the claimed invention in order to teach refreshing of DRAM memory arrays. The teachings of Deshmukh, in the same or in a similar field of endeavor with Bell, can combine Deshmukh’s explicit refresh of multiple rows in a “bank group” and Bell’s implied refresh of multiple banks using a single command. The two refresh methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Bell, as modified by Deshmukh, teaches the apparatus of claim 15.
Bell further teaches wherein the command address input circuit is configured to receive a command address packet which includes the linked activation command, the bank address, the linked bank address, and a row address. (Bell, fig 3, 4, “[0039] As shown, an activate command (ACT) is sent to and/or received by the memory device 100, followed by a read auto precharge+ refresh command (Read APR). A first set of (e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a read operation and/or a precharge operation, and a second set of ( e.g., one or more) command/address bits of the read auto precharge+ refresh (Read APR) command indicate a refresh operation. The first set command/address bits can be the same or different from the second set of command/address bits.”; that a command can comprise a command with comprises a first set of commands and addresses along with a second set of commands and a second set of address; that the first and second commands can be different; that the fist and second address banks can be different).
Regarding claim 17, Bell, as modified by Deshmukh, teaches the apparatus of claim 16.
Bell further teaches wherein one or more bits of the command address packet is shared between the bank address and the linked bank address. (Bell, table 1, “[0043] When the command/address bit 12 is asserted, the memory device can execute a refresh command after executing the corresponding read command (Read), the read auto precharge command (Read AP), the write command (Write), and/or a write auto precharge command (Write AP)… On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; if bit 12 is asserted, then the original command and an associated refresh is performed; if bit 12 is not asserted, then only the original command is performed).
Regarding claim 19, Bell, as modified by Deshmukh, teaches the apparatus of claim 15.
Bell further teaches wherein the refresh control circuit is configured to perform a normal refresh operation, one or more targeted refresh operations, or skip performing a refresh operation as the refresh operation on the second memory bank. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Regarding claim 20, Bell, as modified by Deshmukh, teaches the apparatus of claim 15.
Bell further teaches wherein the command address input circuit is further configured to receive a normal activation command and the bank address, and wherein the row decoder is configured to activate the word line in the first memory bank responsive to the normal activation command and the refresh control circuit is configured to not perform the refresh operation responsive to the normal activation command. (Bell, fig 3, 4, “[0039] In response to the second set of command/address bits of the read auto precharge+ refresh command (Read APR), and the memory device 100 proceeds to perform one or more refresh operations on all or the portion of the memory array 150. [0043] On the other hand, when the command/address bit 12 is not asserted, the memory device 100 can execute the original command received.”; that the refresh portion of the command can refresh all (normal) or part (targeted) of the memory array 150; if the bit 12 is not asserted, then the refresh operation is not performed).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bell, as modified by Deshmukh, in view of SU, et al, U.S. Patent Application Publication 2024/0078202 (“SU”).
Bell, as modified by Deshmukh, teaches the method of claim 8.
Bell teaches further comprising: receiving a second linked activation command and a second bank address, (Bell, fig 6, “[0041] FIG. 6 is a timing diagram 620 illustrating command/ address bus utilization when a refresh command (e.g., a refresh single bank command (REFsb) or another refresh command) is embedded into a write command (Write) or a write auto precharge command (Write AP) in accordance with various embodiments of the present technology.”; that a memory controller can process more than one command on more than one set of bank addresses; that a second operation can include a write operation or a subsequent read operation of figure 4).
Bell, as modified by Deshmukh, does not explicitly teach:
wherein the second bank address is associated with a third bank which is not in the same bank link group as the first bank or the second bank; activating a word line in the third bank responsive to the second linked activation command; and
performing a refresh operation in a fourth bank which is in a second bank link group with the third bank responsive to the linked activation command..
SU teaches:
wherein the second bank address is associated with a third bank which is not in the same bank link group as the first bank or the second bank; activating a word line in the third bank responsive to the second linked activation command; and (SU, fig 4, “[0058] FIG. 4 illustrates an example memory system 400 ( e.g., memory system 200 in FIG. 2) having a logical rank structure based on partial channels of a memory device. [0110] FIGS. 14A and 14B illustrate methods for implementing memory access and refresh using ranks or logical ranks in a memory system according to some embodiments. [0112] With reference to FIG. 14A, in block 1402, the flexible rank memory device may receive signals for memory access at different partial channels of a same memory. [0115] In block 1408, the flexible rank memory device may implement refresh operations at the first partial channel of the same memory of the rank. [0117] In block 1412, the flexible rank memory device may implement refresh operations at the second partial channel of the same memory of the rank. [0144] As will be appreciated by one of skill in the art the order of operations in the foregoing embodiments may be performed in any order.”; that a memory controller can comprise four separate logical rank structures; that the operations can be explicitly looped as shown in fig 14A and 14B).
performing a refresh operation in a fourth bank which is in a second bank link group with the third bank responsive to the linked activation command. (SU, fig 2, “[0056] As another example, for chip select signals received via the chip select bus 228b, different values may indicate to the partial channel 1 interface 214b to activate the memory banks 216b and/or implement the memory access commands at the memory banks 216b of one of the memory devices 212a, 212b.”; that different memory banks 216a-b can be accessed, can be refreshed, that read/write operations can be performed on the memory array).
In view of the teachings of SU it would have been obvious for a person of ordinary skill in the art to apply the teachings of SU to Bell before the effective filing date of the claimed invention in order to teach multiple operations at a memory array. The teachings of SU, in the same or in a similar field of endeavor with Bell, can combine SU’s explicit commands on two memory banks with Bell’s implied commands on two memory banks. The two operations, performed in any order merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights