Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 18, 2026.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on November 21, 2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0162292 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on July 31. 2024 and September 25, 2026, were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-7, 10, and 15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhou et al. (US 20240136415 A1), hereinafter referred to as Zhou.
Regarding Claim 1, Zhou discloses a thin film transistor ([0046] “the display panel includes a thin-film transistor T”; FIG. 1-4: T), comprising:
a base substrate ([0047] “includes a substrate 10”; FIG. 1-4: 10);
a buffer layer on the base substrate ([0050] “an insulating layer 51 disposed on the substrate 10”; FIG. 1-4: 51), an upper surface of the buffer layer having a trench (FIG. 1-4: 51, It is noted that there is a trench surrounding 312 and 311 within 51);
an active layer on the buffer layer ([0057] “Each of the active portions 30 includes the conductor sublayer 31 and the semiconductor sublayer 32”; FIG. 1-4: 31, 32, 311, 312, 313); and
a gate electrode spaced apart from the active layer and at least partially overlapping the active layer in a plan view ([0051] “gate electrode 41”; FIG. 1-4: 41);
wherein the active layer includes:
a channel area that overlaps the gate electrode in the plan view ([0057] “semiconductor sublayer 32… the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other”; FIG. 1-4: 32, 311, 312, For the purposes of examination, the examiner is defining the channel area 32, as well as 311 and 312 up to and including the inner edges of 312 and 312 in the trenches.);
a source area connected to one side of the channel area in the plan view ([0057] “the second conductor subsection 312”; FIG. 1-4: 312, The examiner is considering the left side of the trench as well as the bottom section of 311 in the trench as the source area.); and
a drain area connected to the other side of the channel area in the plan view ([0057] “the first conductor subsection 311”; FIG. 1-4: 311, The examiner is considering the right side of the trench as well as the bottom section of 311 in the trench as the drain area.);
wherein the trench includes:
a first trench having the source area therein (FIG. 1-4: 51’s left trench); and
a second trench having the drain area therein (FIG. 1-4: 51’s right trench);
wherein the channel area includes:
a first channel area (FIG. 1-4: 32, 311, 312, Including the flat part of 311 and 312 between the trenches);
a second area on one side of the first channel area, in contact with the source area, and in the first trench (FIG. 1-4: 312, the sloped side of 312 on the right side of the left trench);
a third channel area on the other side of the first channel area, in contact with the drain area, and in the second trench (FIG. 1-4: 311, the sloped side of 311 on the left side of the right trench);
wherein a shortest distance between an upper surface of the base substrate and the second channel area is shorter than a shortest distance between the upper surface of the base substrate and the first channel area (FIG. 1-4: the substrate 10 is closer to the bottom of the sloped section of 312 than the flat section between trenches), and
wherein a shortest distance between the upper surface of the base substrate and the third channel area is shorter than the shortest distance between the upper surface of the base substrate and the first channel area (FIG. 1-4: the substrate 10 is closer to the bottom of the sloped section of 311 than the flat section between the trenches).
Regarding Claim 2, Zhou discloses the thin film transistor of claim 1, and further discloses the first and second trench being spaced apart from each other (FIG. 1-4: 51, trenches are spaced apart).
Regarding Claim 6, Zhou discloses the thin film transistor of claim 1, and further discloses a gate insulating layer between the active layer and the gate electrode ([0050] “a gate insulating layer 52 disposed on the active layer… an interlayer dielectric layer 53”; FIG. 1-4: 52, 53),
Wherein the gate insulating layer includes:
a first gate insulating layer on the active layer (FIG. 1-4: 53); and
a second gate insulating layer on the first gate insulating layer (FIG. 1-4: 52), and
wherein the first gate insulating layer is on the channel area of the active layer and the trench (FIG. 1-4: 53).
Regarding Claim 7, Zhou discloses the thin film transistor of claim 1, and further discloses a thickness of the first gate insulating layer being greater than a thickness of the second gate insulating layer (FIG. 1-4: 52, 53, It is noted the thickness of 53 is generally greater than 52 across the TFT).
Regarding Claim 10, Zhou discloses the thin film transistor of claim 1, and further discloses a gate insulating layer between the active layer and the gate electrode, wherein the gate insulating layer covers the channel area and exposes the source area and the drain area ([0050] “a gate insulating layer 52 disposed on the active layer”; FIG. 1-4: 52).
Regarding Claim 15, Zhou discloses a display apparatus comprising the thin film transistor of claim 1 ([0046] “the display panel includes a thin-film transistor T”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou.
Zhou teaches the thin film transistor of claim 1, but doesn’t explicitly teach the trench having a height to width ratio of 0.15 to 0.65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the trench height to width ratio of the thin film transistor with routine experiment and optimization in order to prevent conductorization diffusion and characteristic imbalances. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Luo (US 20240063230 A1), hereinafter referred to as Luo.
Zhou teaches the thin film transistor of claim 1, but does not teach the channel, source, and drain areas of the active layer being integrally formed, and the active layer having a constant thickness.
Luo teaches an active layer ([0024] “an active layer 20 disposed on the substrate 10”; FIG. 1-5: 20) composed of a channel portion and two conductive portions, representing the source and drain regions ([0024] “wherein the active layer 20 includes a channel portion 201 and two conductive portions 202”; FIG. 1-5: 201, 202), wherein the parts of the active layer are integrally formed, and the active layer has a constant thickness (FIG. 1-5, layer 20 is one full flat layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thin film transistor of Zhuo with the structure of the active layer of Luo. Both thin film transistors function in the same way, and modifying the active layer to be one integral structure would lead to the predictable result of easing the manufacturing process. The process of manufacturing the active layer of Luo is also the same as the one from the claimed invention (Luo [0053] “performing a conductorization process on two sides of the semiconductor layer 209 through the two first holes 001 on two sides of the semiconductor layer 209 to form the first conductive portion 2021.”; FIG. 5: 209, 201, 2021). Forming this same active layer over two trenches would lead to the expected result of the claimed invention.
Claims 4-5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Choi (US 20250393243 A1), hereinafter referred to as Choi.
Regarding Claim 4, Zhou teaches the thin film transistor of claim 1, and further teaches each of the first and second trenches including:
a first surface substantially parallel to an upper surface of the base substrate (FIG. 1-4: the flat portions of the trenches of 51 within the trench);
a second surface connected to one side of the first surface, the second surface inclined at a first angle relative to the first surface (FIG. 1-4: the inner slopes (closer to the center of the gate electrode 41) of the two trenches of 51); and
a third surface connected to the other side of the first surface, the third surface inclined at a second angle relative to the first surface (FIG. 1-4: the outer slopes of the two trenches of 51);
wherein the active layer is on the second surface and the third surface (FIG 1-4: 311 and 312 are disposed over the entirety of both trenches).
Zhou does not teach a portion of the second surface being overlapped with the gate electrode in the plan view.
Choi teaches a thin film transistor ([0081] “a thin film transistor (100)”; FIG. 2-3: 100) comprising of an active layer disposed into two trenches within a buffer layer ([0081] “a first buffer layer (121), an active layer (130)”; FIG. 2-3: 121, 130, 125) and a gate electrode overlapping the inner sloped surfaces of the two trenches (FIG. 2-3: gate electrode 150 overlaps the inner slopes of 125a and 125b).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the thin film transistor of Zhou with the gate electrode of Choi. Similar to the claimed invention, the trenches of Zhou exist to improve the conductorization of selective portions of the active layer ([0103] “The first connecting portion (130a) and the second connecting portion (130b) may be formed by selectively conductorized with respect to the active layer (130)”). Combining aspects of Choi into Zhou will result in the expected result of improving efficiency, specifically the selective conductorization of parts of the active layer.
Regarding Claim 5, Zhou in view of Choi teaches the thin film transistor of claim 4. Zhou does not teach the entire second surface of each of the first trench and the second trench being overlapped with the gate electrode.
Choi teaches the gate electrode overlapping the entirety of the second surface of the second trench (FIG. 2-3: gate electrode 150 fully overlaps the inner sloped surfaces of the two trenches).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the thin film transistor of Zhou with the gate electrode of Choi because of the reasoning described in claim 4.
Regarding Claim 14, Zhou in view of Choi teaches the thin film transistor of claim 4. Zhou does not explicitly teach the first and second angles being between 30° and 45° relative to the first surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second angles of the Zhou with routine experiment and optimization in order to prevent disconnection due to thicknesses of the active layer. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 8-9 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 20220392987 A1) is cited to teach aspects of the trenches within the thin film transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SHEN whose telephone number is (571)272-0642. The examiner can normally be reached M-Th 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW L SHEN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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