Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-8 and 17-20) in the reply filed on 11/25/2025 is acknowledged. And the newly added claims 21-28 are considered to fall within Group I.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 17-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM (US Pub. 2022/0051747).
Regarding independent claims 1, 17 and 21, KIM discloses a system comprising:
a memory device (Fig.1: memory cell array); and
a processing device (Fig.1: Control Logic Circuit 130), coupled with the memory device (Fig.1: memory cell array), configured to perform operations comprising:
receiving a write command to write data to the memory device (Fig.1: memory cell array) (Fig.12 and [0068] & [0107]: Referring to FIGS. 1 and 3, in an operation S210, the nonvolatile memory device 100 may receive a command CMD, an address ADDR, and first page data from an external device (e.g., a memory controller, a host, an application, etc.) and the command CMD may be a program command defined by an interface between the nonvolatile memory device 100 and the external device);
determining that the write command is associated with programming an operating system of the memory device (Fig.1: memory cell array) (Fig.12 and [0108]: In an operation S220, the nonvolatile memory device 100 may determine a program operation to be performed in response to the received command CMD. The claim / specification do not limit the recited “operating system” to a host computer operating system (e.g., Windows or Linux). Thus, such determination of program operation constitutes determining an operational mode of the memory device);
responsive to determining that the write command is associated with the programming of the operating system of the memory device (Fig.1: memory cell array), loading a first set of values for respective parameters (Fig.12 and [0112]: In an operation S230, the nonvolatile memory device 100 may adjust a program parameter according to a result of the determination. For example, when the operation to be performed is determined to be the first program operation explained with reference to FIG. 9, the nonvolatile memory device 100 (e.g., the control logic circuit 130) may set the program parameter such that pulse width of a program voltage becomes first time T1);
writing, using the first set of values, the data to the memory device (Fig.1: memory cell array) (Fig.12 and [0114]: In an operation S240, the nonvolatile memory device 100 may perform a program operation based on the adjusted program parameter); and
loading a second set of values for the respective parameters ([0112]: When the program operation to be performed is determined to be the second program operation described with reference to FIG. 9, the nonvolatile memory device 100 (e.g., the control logic circuit 130) may set the program parameter such that the pulse width of the program voltage becomes second time T2).
Regarding claims 2, 18 and 22, KIM teaches wherein the respective parameters include a timing parameter and an accuracy parameter ([0112]: the first pulse width with first time T1 and the second pulse width with second time T2 and [0075]-[0078]: verify voltages Vvfy11, Vvfy12, … Verify levels affect programming accuracy).
Regarding claims 3, 19 and 23, KIM teaches wherein the first set of values includes a higher value for the timing parameter and a higher value for the accuracy parameter and the second set of values includes a lower value for the timing parameter and a lower value for the accuracy parameter (Fig.5 and [0072]-[0078]: the second pulse width is different from the first pulse width and Kim further discloses different verify voltages for different program operations).
Regarding claims 4 and 24, KIM teaches wherein the processing device, to determine that the write command is associated with the programming of the operating system of the memory device, determines that the write command includes operating system data for programming an operating system of the memory device ([0108]: In an operation S220, the nonvolatile memory device 100 may determine a program operation to be performed in response to the received command CMD. For example, as described with reference to FIGS. 1 to 11, the nonvolatile memory device 100 may program data DATA based on a multi-step program scheme including a plurality of program operations. The nonvolatile memory device 100 may determine a program operation to be performed, among the plurality of program operations, in response to the received command CMD. The claim / specification do not limit the recited “operating system” to a host computer operating system (e.g., Windows or Linux). Thus, such determination of program operation constitutes determining an operational mode of the memory device).
Regarding claims 5, 20 and 25, KIM teaches wherein the respective parameters are step static offset parameters that include at least one of a program voltage step parameter or a program verify parameter ([0075]-[0078]: verify voltages Vvfy11, Vvfy12, … Verify levels affect programming accuracy).
Regarding claims 6 and 26, KIM teaches wherein a quantity of values in the first set of values is less than a quantity of values in the second set of values ([0061]-[0071]: KIM teaches different program schemes and verify steps for first and second operations, the number of parameter values differs between sets).
Regarding claims 7 and 27, KIM teaches wherein the second set of values is a default set of values for writing standard data that is not associated with the programming of the operating system of the memory device ([0108]-[0110]: the nonvolatile memory device 100 may determine the operation to be performed, based on the number of program operations performed on memory cells connected to a selected word line. For example, as described with reference to FIG. 11, first to third program operations are sequentially performed on memory cells connected to a single word line (e.g., first word line WL1). That is, the nonvolatile memory device 100 may determine a program operation to be performed, based on the number of program operations performed previously.).
Regarding claims 8 and 28 KIM teaches wherein the processing device is further configured to perform operations comprising: receiving a second write command to write second data to the memory device ([0068]-[0070]: After the first program operation is completed (i.e., the first page data is programmed into the selected memory cells), in an operation S130, the nonvolatile memory device 100 receives a command CMD, an address ADDR, and second page data from the external device. According to at least some example embodiments of the inventive concepts, the command CMD received at the operation S130 may be a program command for programming a second page data.);
determining that the second write command is not associated with the programming of the operating system of the memory device ([0108]: The nonvolatile memory device 100 may determine a program operation to be performed, among the plurality of program operations, in response to the received command CMD); and
writing the second data to the memory device using the second set of values for the respective parameters ([0112]-[0114]: When the program operation to be performed is determined to be the second program operation described with reference to FIG. 9, the nonvolatile memory device 100 (e.g., the control logic circuit 130) may set the program parameter such that the pulse width of the program voltage becomes second time T2. In an operation S240, the nonvolatile memory device 100 may perform a program operation based on the adjusted program parameter).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Porzio et al. (Pub. No.: US 2024/0289019) “TECHNIQUES FOR EFFICIENT MEMORY SYSTEM PROGRAMMING”
Considered for teachings related to one or more systems for memory, including techniques for efficient memory system programming.
Does not disclose or suggest responsive to determining that the write command is associated with the programming of the operating system of the memory device, loading a first set of values for respective parameters; writing, using the first set of values, the data to the memory device; and loading a second set of values for the respective parameters.
Cuthery (Pub. No.: US 2010/0230490) “SECURE ACCESS MODULE FOR INTEGRATED CIRCUIT CARD APPLICATIONS”
Considered for teachings related generally to data writing techniques and in particular mechanisms for securely writing data to a portable access credential.
Does not disclose or suggest responsive to determining that the write command is associated with the programming of the operating system of the memory device, loading a first set of values for respective parameters; writing, using the first set of values, the data to the memory device; and loading a second set of values for the respective parameters.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135