DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on May 19, 2026, in response to PTO Office Action mailed on March 19, 2026. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1-2, 8, and 15 have been amended. As a result, claims 1-20 are now pending in this application.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 19, 2026, has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on May 19, 2026, in response to PTO Office Action mailed on March 19, 2026, have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further review a new ground of rejection has been made in view of Lo et al. (Patent Number US 6,055,594).
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103(a) as being unpatentable over Aiki et al. (Patent Number US 5,410,540) in view of Jalan et al. (Publication Number US 2018/0239530 A1), Pilolli et al. (Publication Number US 2015/0019787 A1), and Lo et al. (Patent Number US 6,055,594).
As per claim 1, Aiki et al. discloses “A method, comprising: receiving, via a decoder (focus on the port select decoder 61; FIG. 4) coupled to a feature register resident on a memory device interface (write access register (WAR) 621 to 62N; FIG. 4; Column 3, lines 66-68 to Column 4, lines 1-11) that is divided into a first feature register portion and a second feature register portion (there are several instances of WAR (621 to 62N); FIG. 4), a bit string comprising at least one bit indicative of selection between the first feature register portion and the second feature register portion (through routing information contained in the additional header of the ATM cell; Column 3, lines 66-68 to Column 4, lines 1-11; Column 4, lines 58-68 to Column 5, lines 1-6).” Though Aiki et al. discloses individual registers [there are several instances of WAR (621 to 62N); FIG. 4], Aiki et al. does not disclose writing to selected registers as disclosed in the limitation “and responsive to the at least one bit being indicative of selecting the first feature register portion, writing the bit string to the first feature register portion of the memory device interface, or responsive to the at least one bit being indicative of selecting the second feature register portion, writing the bit string to the second feature register portion of the memory device interface.”
Jalan et al. discloses writing to selected registers as disclosed in the limitation “and responsive to the at least one bit being indicative of selecting the first feature register portion, writing the bit string to the first feature register portion of the memory device interface, or responsive to the at least one bit being indicative of selecting the second feature register portion, writing the bit string to the second feature register portion of the memory device interface (where write enable signals cause data to be written in enabled registers; Paragraph 0028; FIG. 2).”
Aiki et al. and Jalan et al. are analogous art in that they in the field of memory control systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. to enable parallel functionality of circuits [Paragraph 0003].
However, Aiki et al. and Jalan et al. do not disclose “wherein the first feature register portion includes a first set of memory resources to register address information for a first signal received from a host device and the second feature register portion includes a second set of memory resources to register address information for a second signal received from the host device.”
Pilolli et al. discloses “wherein the first feature register portion includes a first set of memory resources to register address information for a first signal received from a host device and the second feature register portion includes a second set of memory resources to register address information for a second signal received from the host device (where the register 230 can be divided into a plurality of portions corresponding to the plurality of interfaces [Paragraph 0023; FIG. 2]. See also the data register 331 (divided into portions 1-4) and cache register 333 (divided into portions 1-4), each corresponding to planes 301 in [FIG. 3]).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. with elements of Pilolli et al. to enable higher density memories without increasing the number of memory cells since each cell can represent more than one unit of data. [Paragraph 0005].
However, Aiki et al., Jalan et al., and Pilolli et al. do not disclose “and wherein the feature register is coupled to data path circuitry of the memory device interface” or “and providing the stored bit string to the data path circuitry.”
Lo et al. discloses “and wherein the feature register is coupled to data path circuitry of the memory device interface (see byte registers 8 connected to RAMS [FIG. 3]. See also second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register; Claim 1).”
Lo et al. discloses “and providing the stored bit string to the data path circuitry (See also second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register; Claim 1).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al., Jalan et al., and Pilolli et al. with elements of Lo et al. to enable s memory interface design having a large data bus but avoiding the problems associated with the high pin count required [Column 2, lines 24-34].
As per claim 2, Aiki et al. discloses “The method of claim 1 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), wherein the first feature register portion and the second feature register portion are designated to circuitry associated to a single output channel [coupled to a quantity of NAND devices] (WAR 621 to 62N are connected to a single bus L42 to memory 4; FIG. 4).”
Pilolli et al. discloses “coupled to a quantity of NAND devices (Paragraphs 0015-0017).”
As per claim 3, Aiki et al. discloses “The method of claim 1 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), further comprising receiving a signal from a first input channel at an input of the decoder (focus on the multiple buses LO1 to LON that connect to a multiplexer 2 and subsequently to selector 36; FIG. 4).”
As per claim 4, Aiki et al. discloses “The method of claim 3 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), further comprising receiving the signal at the input of the decoder from a multiplexor coupled to the first input channel and to a second input channel (multiplexer 2 to buses LO1 to LON; FIG. 4).”
As per claim 5, Aiki et al. discloses “The method of claim 1 (as disclosed by *** above), wherein the first feature register portion is a first designated memory address map and the second feature register portion is a second designated memory address map (through routing information contained in the additional header of the ATM cell; Column 3, lines 66-68 to Column 4, lines 1-11; Column 4, lines 58-68 to Column 5, lines 1-6).”
As per claim 6, Jalan et al. discloses “The method of claim 5 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), wherein the first designated memory address map comprises a first 1 kilobyte address map and the second designated memory address map comprises a second 1 kilobyte address map (note that the number of control bits can be up to 16,384 bits with each register being 32 bits each with individual control registers assigned to an address in the range 0 through 511 [Paragraph 0013]. Note that the size of the memory address maps can also be considered a design choice in the size of the memory address maps can vary depending on the amount of memory present).”
As per claim 7, Aiki et al. discloses “The method of claim 1 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), further comprising directly accessing one of the first feature register portion or the second feature register portion based on an address decode bit (through routing information contained in the additional header of the ATM cell; Column 3, lines 66-68 to Column 4, lines 1-11; Column 4, lines 58-68 to Column 5, lines 1-6).”
As per claim 8, Aiki et al. discloses “A system, comprising: a controller (cell copy section 3 connection to the port select decoder 61 in the buffer memory controller; FIG. 4).” Aiki et al. discloses “and a memory device interface to transfer communication between the controller and the plurality of memory [dice] (cell copy section 3 connection to the port select decoder 61; FIG. 4), wherein the memory device interface comprises: a feature register divided into a first feature register portion and a second feature register portion (through routing information contained in the additional header of the ATM cell; Column 3, lines 66-68 to Column 4, lines 1-11; Column 4, lines 58-68 to Column 5, lines 1-6), wherein the first feature register portion and the second feature register portion are designated to [data path] circuitry associated to a single output channel (WAR 621 to 62N are connected to a single bus L42 to memory 4; FIG. 4).” Aiki et al. discloses “a command decoder coupled to a first input of the first feature register portion and a second input of the second feature register portion (focus on the port select decoder 61; FIG. 4).” Though Aiki et al. discloses individual registers [there are several instances of WAR (621 to 62N); FIG. 4], Aiki et al. does not disclose writing to selected registers as disclosed in the limitation “discloses “and an address decode bit written to the first feature register portion to designate a selection between the first feature register portion and the second feature register portion when receiving signals from the command decoder “ or “a plurality of memory dice.”
Jalan et al. discloses “a plurality of memory dice (Jalen et al. discloses die packages [Paragraph 0044] which are well known in the art).”
Jalan et al. discloses writing to selected registers as disclosed in the limitation “and an address decode bit written to the first feature register portion to designate a selection between the first feature register portion and the second feature register portion when receiving signals from the command decoder (where write enable signals cause data to be written in enabled registers; Paragraph 0028; FIG. 2).”
Aiki et al. and Jalan et al. are analogous art in that they in the field of memory control systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. to enable parallel functionality of circuits [Paragraph 0003].
However, Aiki et al. and Jalan et al. do not disclose “coupled to a plurality of NAND devices,” “wherein the first feature register portion includes a first set of memory resources to register address information for a first signal received from a host device and the second feature register portion includes a second set of memory resources to register address information for a second signal received from the host device.”
Pilolli et al. discloses “coupled to a plurality of NAND devices (Paragraphs 0015-0017).”
Pilolli et al. discloses “wherein the first feature register portion includes a first set of memory resources to register address information for a first signal received from a host device and the second feature register portion includes a second set of memory resources to register address information for a second signal received from the host device (where the register 230 can be divided into a plurality of portions corresponding to the plurality of interfaces [Paragraph 0023; FIG. 2]. See also the data register 331 (divided into portions 1-4) and cache register 333 (divided into portions 1-4), each corresponding to planes 301 in [FIG. 3]).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. with elements of Pilolli et al. to enable higher density memories without increasing the number of memory cells since each cell can represent more than one unit of data. [Paragraph 0005].
However, Aiki et al., Jalan et al., and Pilolli et al. do not disclose first feature register portion and second feature portion are designated “to data path circuitry.”
Lo et al. discloses disclose first feature register portion and second feature portion are designated “to data path circuitry (see byte registers 8 connected to RAMS [FIG. 3]. See also second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register; Claim 1).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al., Jalan et al., and Pilolli et al. with elements of Lo et al. to enable s memory interface design having a large data bus but avoiding the problems associated with the high pin count required [Column 2, lines 24-34].
As per claim 9, Jalan et al. discloses “The system of claim 8 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), wherein the first feature register portion is a standard address map quantity of memory and the second feature register portion is the standard address map quantity of memory (note that the number of control bits can be up to 16,384 bits with each register being 32 bits each with individual control registers assigned to an address in the range 0 through 511 [Paragraph 0013]. Note that the size of the memory address maps can also be considered a design choice in the size of the memory address maps can vary depending on the amount of memory present).”
As per claim 10, Aiki et al. discloses “The system of claim 8 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), comprising a multiplexor, wherein an output of the multiplexor is coupled to an input of the command decoder and an input of the multiplexor is coupled to a first input channel and a second input channel (focus on the multiple buses LO1 to LON that connect to a multiplexer 2 and subsequently to selector 36; FIG. 4).”
As per claim 11, Aiki et al. discloses “The system of claim 8 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), comprising a third feature register portion and a fourth feature register portion coupled to an output of an additional decoder (see the buffer 64 where read address register (RAR) data with decoder 65 (Column 5, lines 7-20) come into play with the write address register (WAR) with decoder 61 data [Column 4, lines 58-68 to Column 5, lines 1-6] resulting in a copy operation by the cell copy section; Column 5, lines 21-27).”
As per claim 12, Aiki et al. discloses “The system of claim 11 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), comprising an additional address decode bit is written to the third feature register portion to designate a selection between the third feature register portion and the fourth feature register portion when receiving signals from the additional decoder (with read address register (RAR) data with decoder 65 (Column 5, lines 7-20) coming into play with the write address register (WAR) with decoder 61 data [Column 4, lines 58-68 to Column 5, lines 1-6] resulting in a copy operation by the cell copy section; Column 5, lines 21-27).”
As per claim 13, Aiki et al. discloses “The system of claim 11 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), wherein the third feature register portion and the fourth feature register portion are designated to the circuitry associated to a different output channel than the single output channel (see bus L43 for the read address registers (RAR) to bus L42 for the write address registers (WAR); FIG. 4).”
As per claim 14, Aiki et al. discloses “The system of claim 8 (as disclosed by Aiki et al., Jalan et al., Pilolli et al., and Lo et al. above), wherein the memory device interface operates in a one of a one channel mode and a two channel mode (see bus L43 for the read address registers (RAR) to bus L42 for the write address registers (WAR); FIG. 4).”
Claims 15-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Aiki et al. (Patent Number US 5,410,540) in view of Jalan et al. (Publication Number US 2018/0239530 A1), Pilolli et al. (Publication Number US 2015/0019787 A1), Kim et al. (Publication Number US 2019/0378551 A1), and Lo et al. (Patent Number US 6,055,594).
As per claim 15, Aiki et al. discloses “and a processing device coupled to the memory sub-system by a memory device interface, the memory device interface comprising: a feature register divided into a first plurality of designated feature register portions designated to [a first data path] circuitry associated with a first set of output channels and a second plurality of designated feature register portions designated to a [second data path] circuitry associated with a second set of output channels (there are several instances of WAR (621 to 62N); FIG. 4).” Aiki et al. discloses “a first command decoder coupled to a first input of the first plurality of designated feature register portions (focus on the port select decoder 61; FIG. 4).” Aiki et al. discloses “a second command decoder coupled to a second input of the second plurality of designated feature register portions (see the buffer 64 where read address register (RAR) data with decoder 65 (Column 5, lines 7-20) come into play with the write address register (WAR) with decoder 61 data [Column 4, lines 58-68 to Column 5, lines 1-6] resulting in a copy operation by the cell copy section; Column 5, lines 21-27).” Aiki et al. discloses “a multiplexor coupled to an input of the second command decoder (focus on the multiple buses LO1 to LON that connect to a multiplexer 2 and subsequently to selector 36; FIG. 4).”
However, Aiki et al. does not disclose “A system comprising: a memory sub-system comprising a non-volatile memory device.”
Jalan et al. discloses “A system comprising: a memory sub-system comprising a non-volatile memory device (Paragraph 0004).”
Aiki et al. and Jalan et al. are analogous art in that they in the field of memory control systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. to enable parallel functionality of circuits [Paragraph 0003]. Also, non-volatile memory is known in the art as a means of fast long-term data storage.
However, Aiki et al. and Jalan et al. do not disclose the presence of more than two decoders as disclosed in the limitation “and a third command decoder coupled to an input of the first command decoder and an input of the multiplexor.” Kim et al. discloses “and a third command decoder coupled to an input of the first command decoder and an input of the multiplexor (see the CMD decoder 150 that cascades into the rower decoder 140 and column decoder 130 [FIG. 2]. Note that Aiki et al. discloses the use of a multiplexer at the input in [FIG. 4]).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al. and Jalan et al. with elements of Kim et al. to more properly handle various other components within a memory system (as the CMD decoder controls other decoders such as column decoder and row decoder [Paragraph 0044]).
However, Aiki et al., Jalan et al., and Kim et al. do not disclose “wherein the first plurality of designated feature register portions includes a first set of memory resources to register address information for a first signal received from a host device and the second plurality of designated feature register portions includes a second set of memory resources to register address information for a second signal received from the host device.”
Pilolli et al. discloses “wherein the first plurality of designated feature register portions includes a first set of memory resources to register address information for a first signal received from a host device and the second plurality of designated feature register portions includes a second set of memory resources to register address information for a second signal received from the host device (where the register 230 can be divided into a plurality of portions corresponding to the plurality of interfaces [Paragraph 0023; FIG. 2]. See also the data register 331 (divided into portions 1-4) and cache register 333 (divided into portions 1-4), each corresponding to planes 301 in [FIG. 3]).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al., Jalan et al., and Kim et al. with elements of Pilolli et al. to enable higher density memories without increasing the number of memory cells since each cell can represent more than one unit of data. [Paragraph 0005].
However, Aiki et al., Jalan et al., Kim et al., and Pilolli et al. do not disclose first feature register portion and second feature portion are designated “to a first data path circuitry” or “to a second data path circuitry.”
Lo et al. discloses disclose first feature register portion and second feature portion are designated “to a first data path circuitry (see byte registers 8 connected to RAMS [FIG. 3]. See also second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register; Claim 1)” or “to a second data path circuitry (see byte registers 8 connected to RAMS [FIG. 3]. See also second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register; Claim 1).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Aiki et al., Jalan et al., Kim et al., and Pilolli et al. with elements of Lo et al. to enable s memory interface design having a large data bus but avoiding the problems associated with the high pin count required [Column 2, lines 24-34].
As per claim 16, Aiki et al. discloses “The system of claim 15 (as disclosed by Aiki et al., Jalan et al., Kim et al., Pilolli et al., and Lo et al. above), wherein the processing device is to write a first address decode bit to the first plurality of designated feature register portions to designate a selection between the first plurality of designated feature register portions for signals received from the first command decoder (through routing information contained in the additional header of the ATM cell; Column 3, lines 66-68 to Column 4, lines 1-11; Column 4, lines 58-68 to Column 5, lines 1-6).”
As per claim 17, Aiki et al. discloses “The system of claim 16 (as disclosed by Aiki et al., Jalan et al., Kim et al., Pilolli et al., and Lo et al. above), wherein the processing device is to write a second address decode bit to the second plurality of designated feature register portions to designate a selection between the second plurality of designated feature register portions for signals received from the second command decoder (see the buffer 64 where read address register (RAR) data with decoder 65 (Column 5, lines 7-20) come into play with the write address register (WAR) with decoder 61 data [Column 4, lines 58-68 to Column 5, lines 1-6] resulting in a copy operation by the cell copy section; Column 5, lines 21-27).”
As per claim 18, Aiki et al. discloses “The system of claim 15 (as disclosed by Aiki et al., Jalan et al., Kim et al., Pilolli et al., and Lo et al. above), comprising a first input channel coupled to the third command decoder (Kim et al. discloses a third decoder in [FIG. 2]) and a second input channel coupled to the multiplexor (FIG. 4).”
As per claim 19, Aiki et al. discloses “The system of claim 18 (as disclosed by Aiki et al., Jalan et al., Kim et al., Pilolli et al., and Lo et al. above), wherein the second input channel is disabled to execute a one channel mode utilizing the first input channel (see bus L43 for the read address registers (RAR) for read operations [Column 5, lines 7-20] to bus L42 for the write address registers (WAR) for write operations; Column 4, lines 58-68 to Column 5, lines 1-6; FIG. 4).”
As per claim 20, Kim et al. discloses “The system of claim 15 (a as disclosed by Aiki et al., Jalan et al., Kim et al., Pilolli et al., and Lo et al. above), wherein the first set of output channels includes a first output channel coupled to a first portion of NAND dice and a second output channel coupled to a second portion of NAND dice (Paragraph 0021).”
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to register connections to data buses:
U.S. PATENT NUMBERS:
2006/0069822 A1 – XENPAK register group 6 [FIG. 1]
5,961,611 – [FIG. 2]
CONCLUDING REMARKS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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/H.W.Y/Examiner, Art Unit 2181 September 2, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
Prosecution Insights