Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (CN 107566009 A and Hu hereinafter.).
Regarding claim 1, Hu discloses a circuit comprising: a differential to single ended (DSE) circuit [fig. 1, balance to unbalance converter 150] having a first input [unlabeled connection of 150 coupled to 180], a second input [unlabeled connection of 150 directly coupled to ground], a first output [unlabeled connection of 150 coupled to transistor M1a], and a second output [unlabeled connection of 150 coupled to transistor M1b]; a first transistor [M1a] having first [drain], second [source], and control [gate] terminals, the control terminal of the first transistor coupled to the first output of the DSE circuit [gate of M1a coupled to 150 through itself]; a second transistor [M1b] having first [drain], second [source], and control [gate] terminals, the control terminal of the second transistor coupled to the second output of the DSE circuit [gate of M1b coupled to 150 through itself]; a third transistor [M2a] having first [drain], second [source], and control [gate] terminals, the first terminal of the third transistor coupled to the first terminal of the first transistor [M2a coupled to M1a through themselves] and the control terminal of the third transistor coupled to the first terminal of the second transistor [M2a coupled to M1b through themselves as well as 150 or 160]; and a fourth transistor [M2b] having first [drain], second [source], and control [gate] terminals, the first terminal of the fourth transistor coupled to the first terminal of the second transistor [M2b coupled to M1b], and the control terminal of the fourth transistor coupled to the first terminal of the first transistor [M2b coupled to M1a through themselves as well as 150 or 160].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shrivastava et al. (US 20230308323 A1 and Shrivastava hereinafter.) in view of Tzeng et al. (US 20160147252 A1 and Tzeng hereinafter.).
Regarding claim 12, Shrivastava discloses a circuit comprising: a first transistor [fig. 9, transistor 950] having first, second, and control terminals, a second transistor [955] having first, second, and control terminals; a third transistor [920] having first, second, and control terminals, the control terminal of the third transistor coupled to the first terminal of the first transistor [gate of 920 coupled to 950 through 945]; a fourth transistor [925] having first, second, and control terminals, the control terminal of the fourth transistor coupled to the first terminal of the second transistor [gate of 925 coupled to 950 through 945]; a fifth transistor [945] having first, second, and control terminals, the control terminal of the fifth transistor coupled to the first terminal of the fourth transistor [gate of 945 coupled to 925]; a sixth transistor [940] having first, second, and control terminals, the control terminal of the sixth transistor coupled to the first terminal of the third transistor [gate of 940 coupled to 920 through 925]; a first inverter [930] having an input and an output. Shrivastava discloses further a second inverter [935] having an input and an output, the input of the second inverter coupled to the first terminal of the fourth transistor [input of 935 coupled to 925 through 920] and the first terminal of the sixth transistor [input of 935 coupled to 925 through 920 and 925]. Shrivastava does not explicitly disclose the input of the first inverter coupled to the first terminal of the third transistor and the first terminal of the fifth transistor.
However, Tzeng discloses the input of the first inverter [fig. 1, inverter 12] coupled to the first terminal of the third transistor [P5] and the first terminal of the fifth transistor [P6]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Shrivastava to include the input of the first inverter coupled to the first terminal of the third transistor and the first terminal of the fifth transistor as taught by Tzeng to improve power requirements in a clocking circuit.
Response to Arguments
Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive.
Regarding claim 1, applicant argues [pg. 11 of Remarks] Hu does not teach “the control terminal of the first transistor coupled to the first output of the DSE circuit. Examiner respectfully disagrees.
The gate of transistor M1 is coupled to output winding of 150 through the PN junction formed between the gate and drain of M1 as shown in fig. 1. Therefore Hu reads on the claims and the rejection still stands.
Regarding claim 12, applicant argues [pg. 11 of Remarks] Shrivastava does not disclose “the control terminal of the third transistor coupled to the first terminal of the first transistor. Examiner respectfully disagrees.
The gate of transistor 920 is coupled to transistor 950 through the PN junction formed between the gate and drain of 920 and the PN junction formed between gate and source of transistor 945. Therefore Shrivastava reads on the claims and the rejection still stands.
Allowable Subject Matter
Claims 2, 3, 7, 9, 11, 13 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 18 is allowed because the prior art of record does not disclose nor render obvious “An apparatus comprising: a transformer including a primary winding, a secondary winding, and an isolation barrier, the secondary winding having a first terminal and a second terminal; a transmitter coupled to the primary winding; and a receiver coupled to the secondary winding, the receiver including: a differential to single ended (DSE) circuit having a first input, a second input, a first output, and a second output, the first input of the DSE circuit coupled to the first terminal of the secondary winding, the second input of the DSE circuit coupled to the second terminal of the secondary winding; a first transistor having first, second, and control terminals, the control terminal of the first transistor coupled to the first output of the DSE circuit; a second transistor having first, second, and control terminals, the control terminal of the second transistor coupled to the second output of the DSE circuit; a third transistor having first, second, and control terminals; a fourth transistor having first, second, and control terminals; a first inverter having an input and an output, the input of the first inverter coupled to the first terminal of the first transistor and the first terminal of the third transistor; a second inverter having an input and an output, the input of the second inverter coupled to the first terminal of the second transistor and the first terminal of the fourth transistor; a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor coupled to the output of the first inverter and the control terminal of the fourth transistor; and a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the output of the second inverter and the control terminal of the third transistor.” as cited with the rest of the claimed limitation.
Dependent claims 19-20 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, K (US 20200119758 A1) is cited to teach a communication system with increased noise suppression.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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