Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The specification has been amended to overcome the objection to the drawings. The objection to the drawings is withdrawn.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 4-8, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “responsive to each pulse of a self-refresh signal” in lines 2-3, as well as “periodically provide pulses of the self-refresh signal” in lines 4-5. It is unclear whether “each pulse” and “pulses” are intended to refer to the same pulses. For example, the claim also sets forth “the self-refresh oscillator provides the pulses of the self-refresh signal” in lines 7-8, which clearly refers back to the same “pulses of the self-refresh signal” as set forth earlier in the claim, providing proper antecedent basis. Appropriate clarification is required.
Claims 4-8 are rejected as dependent upon claim 1.
Claim 4 sets forth “and a second voltage terminal configures to receive the reference voltage”. It is unclear the intended meaning of this claim language, in particular what the second voltage terminal is configuring in the claim.
Claim 5 is rejected as dependent upon claim 4.
Claim 17 sets forth “wherein the refresh control circuit is configured to perform refresh operation responsive to the self-refresh signal.” This language is unclear. For purposes of compact prosecution, this is being interpreted as “wherein the refresh control circuit is configured to perform a self-refresh operation responsive to the self-refresh signal”. Appropriate clarification is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 3 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 3 is dependent upon canceled claim 2. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim) in view of US 20100061160 A1 (Jeong) in view of US 20060146631 (Jang).
Regarding claim 1, Kim teaches an apparatus (Kim, FIG. 1-4) comprising: a refresh control circuit (Kim, [0004]: “self-refresh control circuit”, and “command decoder 110”) configured to perform a refresh operation responsive to each pulse of a self-refresh signal; (Kim, “self-refresh operation”) a self-refresh oscillator configured to periodically provide pulses of the self- refresh signal at a rate; (Kim, FIG. 5, “a first oscillator”; [0049]:“The first oscillator 121_2 may generate the self-period signal SOSC with a pulse…”). However, Kim does not appear to explicitly teach a self-refresh rate adjustment circuit configured to compare a system voltage to a reference voltage and reduce the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal when the system voltage is less than the reference voltage based on the comparison.
Jeong teaches a self-refresh rate adjustment circuit (Jeong, “self-refresh operation”; Jeong, [0056]: “The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI.”). However, Jeong does not appear to explicitly teach configured to compare a system voltage to a reference voltage and reduce the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal when the system voltage is less than the reference voltage based on the comparison.
Jang cures the deficiencies of Kim/Jeong. Jang teaches configured to compare a system voltage to a reference voltage and reduce the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal when the system voltage is less than the reference voltage based on the comparison. (Jang, [0007]: “there is provided a self refresh period signal generator including: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.”; [0019]: “The voltage detection unit 100 detects a voltage level of a power supply voltage VDD to thereby generate a first and a second period control signals HOSC and LOSC according to the detected voltage level of the power supply voltage VDD.”). Jang, unlike Jeong, does not directly teach the opposite of the claim (for example, reducing a rate of self-refresh if system voltage increases above a threshold), but instead provides for a voltage detection unit to generate a period control signal and either reduce or increase a rate of self-refresh depending on a reference voltage, including if a reference voltage increases or decreases beyond a threshold (Jang, “voltage level”).
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on device factors such as device/supply voltage. It would be obvious to one of ordinary skill in the art to combine the methods of Kim and the methods of Jeong to implement a circuit in which voltage levels are sensed in order to reduce a rate at which a refresh signal is oscillated. Both Jeong/Kim and Jang are directed to systems involving self refresh rate control in view of voltage levels of such a system. One of ordinary skill in the art would be motivated to modify the methods of Jeong/Kim with the teachings of Jang to reduce a rate of self-refresh operations if a system voltage falls below a voltage level, or if a system voltage increases above a voltage level, depending on desired behavior of the self-refresh operations in accordance with a memory system.
Regarding claim 7, Kim/Jeong/Jang teaches the apparatus of claim 1, wherein the self-refresh rate adjustment circuit is configured to compare the system voltage to the reference voltage during a self-refresh mode. (Jeong, [0028]: “The semiconductor memory device may further include a pulse generator configured to generate an enable control signal that enables operation of the voltage comparator only during a non self refresh operation period.”)
Regarding claim 16, Kim teaches an apparatus (Kim, FIG. 1-4) comprising: a refresh control circuit (Kim, [0004]: “self-refresh control circuit”, and “command decoder 110”) configured to periodically perform self-refresh operations (“self-refresh operation”). Kim does not appear to explicitly teach wherein the operations are performed in a self-refresh mode; and a self-refresh rate adjustment circuit configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage.
Jeong cures the deficiencies of Kim. Jeong teaches wherein self-refresh operations are performed in a self-refresh mode; (Jeong, [0056]: “The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI.”) and a self-refresh rate adjustment circuit (Jeong, “self-refresh operation”). Jeong does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage.
Jang cures the deficiencies of Kim/Jeong. Jang teaches wherein the self-refresh rate adjustment circuit is configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage. (Jang, [0007]: “there is provided a self refresh period signal generator including: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.”; [0019]: “The voltage detection unit 100 detects a voltage level of a power supply voltage VDD to thereby generate a first and a second period control signals HOSC and LOSC according to the detected voltage level of the power supply voltage VDD.”). Jang, unlike Jeong, does not directly teach the opposite of the claim (for example, reducing a rate of self-refresh if system voltage increases above a threshold), but instead provides for a voltage detection unit to generate a period control signal and either reduce or increase a rate of self-refresh depending on a reference voltage, including if a reference voltage increases or decreases beyond a threshold (Jang, “voltage level”).
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on device factors such as device/supply voltage. It would be obvious to one of ordinary skill in the art to combine the methods of Kim and the methods of Jeong to implement a circuit in which voltage levels are sensed in order to reduce a rate at which a refresh signal is oscillated. Both Jeong/Kim and Jang are directed to systems involving self refresh rate control in view of voltage levels of such a system. One of ordinary skill in the art would be motivated to modify the methods of Jeong/Kim with the teachings of Jang to reduce a rate of self-refresh operations if a system voltage falls below a voltage level, or if a system voltage increases above a voltage level, depending on desired behavior of the self-refresh operations in accordance with a memory system.
Regarding claim 17, Kim/Jeong/Jang teaches the apparatus of claim 16, further comprising: a self-refresh oscillator configured to provide pulses of a self-refresh signal, (Kim, FIG. 5, “a first oscillator”; [0049]:“The first oscillator 121_2 may generate the self-period signal SOSC with a pulse…”) wherein the refresh control circuit is configured to perform refresh operation responsive to the self-refresh signal, (Jeong, “self-refresh operation”) and wherein the self-refresh rate adjustment circuit is configured to change the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal. (Jeong, “[0027] In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a reference voltage generator configured to receive a self refresh enable control signal and to generate a plurality of reference voltages each having different voltage levels, and a voltage comparator configured to compare each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit, and to generate a result signal that controls a self refresh operation cycle; [0061] For example, if the temperature information voltage VTEMP expresses a temperature lower than 45° C. because the internal temperature of the integrated circuit is so low, the three flag signals TEMPA, TEMPB, and TEMPC are low-disabled. Therefore, if the self refresh operation period, which is performed by the self refresh oscillator 111, can be set to four times of a reference cycle, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high-enabled, and the self refresh operation cycle may be set to two times, one times, or 1.5 times of a reference cycle.”)
Regarding claim 19, Kim/Jeong/Jang teaches the apparatus of claim 18, wherein the system voltage is VDD and the reference voltage is VDDQ. (One of ordinary skill in the art would recognize these terms to refer to drain voltage and supply voltage to an output buffer. Jeong teach wherein the system voltage (“temperature voltage”) is VDD and the reference voltage (“reference voltage”) is VDDQ.)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim) in view of US 20100061160 A1 (Jeong) in view of US 20060146631 (Jang) in view of US 20180061483 A1 (Morgan).
Regarding claim 8, Kim/Jeong/Jang teaches the apparatus of claim 1, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to reducing the rate of the self-refresh signal.
Morgan cures the deficiencies of Kim/Jeong/Jang. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to reducing the rate of the self-refresh signal. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the
subarray refresh circuits may enter into an idle state, at block 630.”)
Both Kim/Jeong/Jang and Morgan are directed to refresh circuits including systems and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Kim/Jeong/Jang and the methods of Morgan to
implement a circuit in which the alert signal of Morgan is sent in response to a reduction
in rate of a self-refresh signal as taught in Kim/Jeong/Jang. One of ordinary skill in the art would have the motivation to combine Kim/Jeong/Jang and Morgan for the purpose of implementing a system alert and improving versatility of the device.
Claim(s) 9 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20060146631 (Jang).
Regarding claim 9, Jeong teaches a method (Jeong, “method for on die thermal sensor suitable for auto self refresh”) comprising: comparing a system voltage of a memory device (Jeong, [0009]: “The temperature voltage generator 101 senses an internal temperature of an integrated circuit and generates a temperature information voltage VTEMP”) to a reference voltage (Jeong, “plurality of reference voltages”) during a self-refresh mode of the memory device; (Jeong, “self refresh operation”; “self refresh operation cycle”). Jeong does not appear to explicitly teach and reducing a rate of self-refresh operations if the system voltage falls below the reference voltage.
Jang cures the deficiencies of Jeong. Jang teaches reducing a rate of self-refresh operations if the system voltage falls below the reference voltage. (Jang, [0007]: “there is provided a self refresh period signal generator including: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.”; [0019]: “The voltage detection unit 100 detects a voltage level of a power supply voltage VDD to thereby generate a first and a second period control signals HOSC and LOSC according to the detected voltage level of the power supply voltage VDD.”). Jang, unlike Jeong, does not directly teach the opposite of the claim (for example, reducing a rate of self-refresh if system voltage increases above a threshold), but instead provides for a voltage detection unit to generate a period control signal and either reduce or increase a rate of self-refresh depending on a reference voltage, including if a reference voltage increases or decreases beyond a threshold (Jang, “voltage level”).
Both Jeong and Jang are directed to systems involving self refresh rate control in view of voltage levels of such a system. One of ordinary skill in the art would be motivated to modify the methods of Jeong with the teachings of Jang to reduce a rate of self-refresh operations if a system voltage falls below a voltage level, or if a system voltage increases above a voltage level, depending on desired behavior of the self-refresh operations in accordance with a memory system.
Regarding claim 13, Jeong/Jang teaches the method of claim 9, wherein the system voltage is VDD and the reference voltage is VDDQ. (One of ordinary skill in the art would recognize these terms to refer to drain voltage and supply voltage to an output buffer. Jeong teach wherein the system voltage (“temperature voltage”) is VDD and the reference voltage (“reference voltage”) is VDDQ.)
Regarding claim 14, Jeong/Jang teaches the method of claim 9, further comprising comparing the system voltage to the reference voltage while a self-refresh enable signal (Jeong, [0014]: “enable signal ENABLE”) is active. (Jeong, [0028]: “The semiconductor memory device may further include a pulse generator configured to generate an enable control signal that enables operation of the voltage comparator only during a non self refresh operation period.”)
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20060146631 (Jang) in view of US 20180061483 A1 (Morgan).
Regarding claim 15, Jeong/Jang teaches the method of claim 9, but does not appear to explicitly teach further comprising sending an alert signal responsive to reducing the rate of the self-refresh operations.
Morgan cures the deficiencies of Jeong/Jang. Morgan teaches further comprising sending an alert signal responsive to reducing the rate of the self-refresh operations. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the
subarray refresh circuits may enter into an idle state, at block 630.”)
Both Jeong/Jang and Morgan are directed to refresh circuits including systems
and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Morgan to
implement a circuit in which the alert signal of Morgan is sent in response to a reduction
in rate of a self-refresh signal as taught in Jeong/Jang. One of ordinary skill in the art
would have the motivation to combine Jeong/Jang and Morgan for the purpose of
implementing a system alert and improving versatility of the device.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim) in view of US 20100061160 A1 (Jeong) in view of US 20060146631 (Jang) in view of US 20180061483 A1 (Morgan).
Regarding claim 20, Kim/Jeong/Jang teaches the apparatus of claim 16, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to changing the rate of the pulses of the self-refresh signal.
Morgan cures the deficiencies of Kim/Jeong/Jang. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to changing the rate of the pulses of the self-refresh signal. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the subarray refresh circuits may enter into an idle state, at block 630.”)
Both Kim/Jeong/Jang and Morgan are directed to refresh circuits including systems and methods for self-refresh rate control. It would be obvious to one of ordinary skill in the art to combine the methods of Kim/Jeong/Jang and the methods of Morgan to implement a circuit in which the alert signal of Morgan is sent in response to an adjustment of rate of a self-refresh signal as taught in Kim/Jeong/Jang. One of ordinary skill in the art would have the motivation to combine Kim/Jeong/Jang and Morgan for the purpose of implementing a system alert and improving versatility of the device.
Response to Arguments
The indefiniteness rejections of claims 5, 13, and 19 regarding the use of the abbreviations VDD and VDDQ have been clearly defined and the rejections are withdrawn.
The arguments regarding the indefiniteness rejection to claim 18 are persuasive and the indefiniteness rejection to claim 18 is withdrawn.
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Resolution of indefiniteness issues is required and further search and consideration is required before indication of allowable subject matter.
Claims 10-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of record does not appear to teach a method comprising: comparing a system voltage of a memory device to a reference voltage during a self-refresh mode of the memory device; and reducing a rate of self-refresh operations if the system voltage falls below the reference voltage, further comprising: periodically providing a self-refresh signal during the self-refresh mode; and performing the self-refresh operation by refreshing one or more word lines responsive to the self-refresh signal.
Regarding claim 18, the prior art of record does not appear to teach an apparatus comprising: a refresh control circuit configured to periodically perform self-refresh operations in a self-refresh mode; and a self-refresh rate adjustment circuit configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage, further comprising: a memory array; and an input/output circuit, wherein the system voltage is used by the memory array and the reference voltage is used by the input/output circuit but not the memory array.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights