Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 1: 124. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10-13, and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “a pulse of a self-refresh signal”. Claim 1 also sets forth “provide pulses of the self-refresh signal” and “the pulses of the self-refresh signal”. It is unclear whether “a pulse of a self-refresh signal” is included and/or may be included in the “pulses of the self-refresh signal”. Appropriate clarification is required.
Claims 2-8 are rejected as dependent upon claim 1.
Claim 2 sets forth “when the system voltage is less than reference voltage”. Claim 1, upon which claim 2 depends, sets forth “a reference voltage”. It is unclear whether the “less than reference voltage” of claim 2 is referring to the same “reference voltage”. Appropriate clarification is required.
Claim 3 is rejected as dependent upon claim 2.
Claim 4 sets forth “a first voltage terminal configured to receive system voltage”. Claim 1, upon which claim 4 depends, sets forth “a system voltage”. It is unclear whether “receive system voltage” is referring to the same “system voltage” as claim 1. Appropriate clarification is required.
Claim 5 is rejected as dependent upon claim 4.
Claim 4 sets forth “a second voltage terminal configures to receive reference voltage”. Claim 1, upon which claim 4 depends, sets forth “a reference voltage”. It is unclear whether “receive reference voltage” is referring to the same “reference voltage” as claim 1. Further, for purposes of compact prosecution, “configures” is being interpreted as “configured”. Appropriate clarification is required.
Claim 5 is rejected as dependent upon claim 4.
Claim 5 sets forth “VDD” and “VDDQ”. For purposes of compact prosecution, one of ordinary skill in the art would recognize these terms to generally refer to a drain voltage and supply voltage to output buffers. However, clarification and spelling out of the abbreviations is required.
Claim 10 sets forth “a self-refresh operation”. Claim 9, upon which claim 10 depends, sets forth “self-refresh operations”. It is unclear whether “a self-refresh operation” is belonging to the group of “self-refresh operations”. Appropriate clarification is required.
Claims 11-12 are rejected as dependent upon claim 10.
Claim 10 sets forth “a self-refresh mode”. Claim 9, upon which claim 10 depends, also sets forth “a self-refresh mode”. It is unclear whether each instance of “a self-refresh mode” is referring to the same “self-refresh mode”. Appropriate clarification is required.
Claims 11-12 are rejected as dependent upon claim 10.
Claim 13 sets forth “VDD” and “VDDQ”. For purposes of compact prosecution, one of ordinary skill in the art would recognize these terms to generally refer to a drain voltage and supply voltage to output buffers. However, clarification and spelling out of the abbreviations is required.
Claim 17 sets forth “wherein the refresh control circuit configured to perform refresh operation”. This language is unclear. Appropriate clarification is required.
Claim 18 sets forth “the apparatus of claim 16, further comprising: a memory array; and an input/output circuit, wherein the system voltage is used by the memory array and the reference voltage is used by the input/output circuit but not the memory array.” As set forth in MPEP 2173.05(i), “The current view of the courts is that there is nothing inherently ambiguous or uncertain about a negative limitation. So long as the boundaries of the patent protection sought are set forth definitely…Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims.” There does not appear to be support for this claim in the disclosure. Appropriate clarification is required.
Claim 19 is rejected as dependent upon claim 18.
Claim 19 sets forth “VDD” and “VDDQ”. For purposes of compact prosecution, one of ordinary skill in the art would recognize these terms to generally refer to a drain voltage and supply voltage to output buffers. However, clarification and spelling out of the abbreviations is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20100061160 A1 (Jeong).
Regarding claim 9, Jeong teaches a method (Jeong, “method for on die thermal sensor suitable for auto self refresh”) comprising: comparing a system voltage of a memory device (Jeong, [0009]: “The temperature voltage generator 101 senses an internal temperature of an integrated circuit and generates a temperature information voltage VTEMP”) to a reference voltage (Jeong, “plurality of reference voltages”) during a self-refresh mode of the memory device; (Jeong, “self refresh operation”; “self refresh operation cycle”) and reducing a rate of self-refresh operations (Jeong, “self refresh operation period”) if the system voltage falls below the reference voltage. (Jeong, [0077]: “As described above, the comparison results TEMPAI, TEMPBI, and TEMPCI indicate one of four temperature regions where the internal temperature of the integrated circuit belongs to. Therefore, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high enabled or low disabled according to the internal temperature of the integrated circuit. Therefore, the self refresh oscillator 111 controls the self refresh cycle to four times, two times, one times, or 0.5 times of a refresh cycle based on the flag signals TEMPA, TEMPB, and TEMPC.”)
Regarding claim 13, Jeong teaches the method of claim 9, wherein the system voltage is VDD and the reference voltage is VDDQ. (One of ordinary skill in the art would recognize these terms to refer to drain voltage and supply voltage to an output buffer, but clarification is required as it applies to the instant claims. Jeong appears to teach wherein the system voltage (“temperature voltage”) can serve as VDD and the reference voltage (“reference voltage”) can serve as VDDQ.
Regarding claim 14, Jeong teaches the method of claim 9, further comprising comparing the system voltage to the reference voltage while a self-refresh enable signal (Jeong, [0014]: “enable signal ENABLE”) is active. (Jeong, [0028]: “The semiconductor memory device may further include a pulse generator configured to generate an enable control signal that enables operation of the voltage comparator only during a non self refresh operation period.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 16-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim, et al., hereinafter Kim) in view of US 20100061160 A1 (Jeong).
Regarding claim 1, Kim teaches an apparatus (Kim, FIG. 1-4) comprising: a refresh control circuit (Kim, [0004]: “self-refresh control circuit”, and “command decoder 110”) configured to perform a refresh operation (“self-refresh operation”) responsive to a pulse of a self-refresh signal; (Kim, [0038]: “self-refresh signal SRET”) a self-refresh oscillator configured to periodically provide pulses of the self-refresh signal at a rate; (Kim, FIG. 5, “a first oscillator”; [0049]:“The first oscillator 121_2 may generate the self-period signal SOSC with a pulse…”).
Kim does not appear to teach a self-refresh rate adjustment circuit configured to compare a system voltage to a reference voltage and reduce the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal based on the comparison.
Jeong cures the deficiencies of Kim. Jeong teaches a self-refresh rate adjustment circuit (Jeong, “self-refresh operation”) configured to compare a system voltage to a reference voltage (Jeong, “[0027] In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a reference voltage generator configured to receive a self refresh enable control signal and to generate a plurality of reference voltages each having different voltage levels, and a voltage comparator configured to compare each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit, and to generate a result signal that controls a self refresh operation cycle.”) and reduce the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal based on the comparison. (Jeong provides several embodiments, for example, “[0056] The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI… [0063] The temperature information voltage is in inverse proportion to the internal temperature of the integrated circuit. The reference voltages VREFA_TS, VREFB_TS, and VREFC_TS, and the trimming voltage VTRIM_TS may be internal temperatures T|TEMPA, T|TEMPB, T|TEMPC, and T|TEMP—TRIM of the integrated circuit, for example, 45° C., 65° C., 85° C., and 93° C.”)
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on device factors such as device/supply voltage. It would be obvious to one of ordinary skill in the art to combine the methods of Kim and the methods of Jeong to implement a circuit in which voltage levels are sensed in order to reduce a rate at which a refresh signal is oscillated. One of ordinary skill in the art would have the motivation to combine Kim and Jeong for the purpose of improving the DRAM device and maintain data integrity.
Regarding claim 2, Kim/Jeong teaches the apparatus of claim 1, wherein the self-refresh rate adjustment circuit is configured to reduce the rate when the system voltage (Jeong, “temperature voltage VTEMP”) is less than reference voltage. (Jeong, “[0061] For example, if the temperature information voltage VTEMP expresses a temperature lower than 45° C. because the internal temperature of the integrated circuit is so low, the three flag signals TEMPA, TEMPB, and TEMPC are low-disabled. Therefore, if the self refresh operation period, which is performed by the self refresh oscillator 111, can be set to four times of a reference cycle, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high-enabled, and the self refresh operation cycle may be set to two times, one times, or 1.5 times of a reference cycle.”)
Regarding claim 3, Kim/Jeong teaches the apparatus of claim 2, wherein the self-refresh rate adjustment circuit is configured to change a period of the self-refresh oscillator from a first period to a second period which is longer than the first period, responsive to the system voltage being less than the reference voltage. (Jeong, [0077]: “As described above, the comparison results TEMPAI, TEMPBI, and TEMPCI indicate one of four temperature regions where the internal temperature of the integrated circuit belongs to. Therefore, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high enabled or low disabled according to the internal temperature of the integrated circuit. Therefore, the self refresh oscillator 111 controls the self refresh cycle to four times, two times, one times, or 0.5 times of a refresh cycle based on the flag signals TEMPA, TEMPB, and TEMPC.”)
Regarding claim 4, Kim/Jeong teaches the apparatus of claim 1, further comprising: a first voltage terminal configured to receive system voltage; (Jeong, FIG. 1; [0053]: “ The temperature sensor 301 senses an internal temperature of an integrated circuit using a property that a voltage between a base terminal and an emitter terminal of a bipolar junction transistor (BJT) in a band-gap circuit of the integrated circuit…”) and a second voltage terminal configures to receive reference voltage. (Jeong, [0074]: “One of the comparators of the voltage comparator 307 includes a multiplexer 701 at an input terminal receiving the reference voltage.”)
Regarding claim 5, Kim/Jeong teaches the apparatus of claim 4, wherein the system voltage is VDD and the reference voltage is VDDQ. (One of ordinary skill in the art would recognize these terms to refer to drain voltage and supply voltage to an output buffer, but clarification is required as it applies to the instant claims. Jeong appears to teach wherein the system voltage (“temperature voltage”) can serve as VDD and the reference voltage (“reference voltage”) can serve as VDDQ.
Regarding claim 7, Kim/Jeong teaches the apparatus of claim 1, wherein the self-refresh rate adjustment circuit is configured to compare the system voltage to the reference voltage during a self-refresh mode. (Jeong, [0056]: “The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI.”)
Regarding claim 16, Kim teaches an apparatus (Kim, FIG. 1-4) comprising: a refresh control circuit (Kim, [0004]: “self-refresh control circuit”, and “command decoder 110”) configured to periodically perform self-refresh operations (“self-refresh operation”), but Kim does not appear to explicitly teach wherein the operations are performed in a self-refresh mode; and a self-refresh rate adjustment circuit configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage.
Jeong cures the deficiencies of Kim. Jeong teaches wherein self-refresh operations are performed in a self-refresh mode; (Jeong, [0056]: “The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI.”) and a self-refresh rate adjustment circuit (Jeong, “self-refresh operation”) configured to change a rate of the self-refresh operations if a system voltage falls below a reference voltage. (Jeong provides several embodiments, for example, “[0056] The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI… [0063] The temperature information voltage is in inverse proportion to the internal temperature of the integrated circuit. The reference voltages VREFA_TS, VREFB_TS, and VREFC_TS, and the trimming voltage VTRIM_TS may be internal temperatures T|TEMPA, T|TEMPB, T|TEMPC, and T|TEMP—TRIM of the integrated circuit, for example, 45° C., 65° C., 85° C., and 93° C.”)
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on device factors such as device/supply voltage. It would be obvious to one of ordinary skill in the art to combine the methods of Kim and the methods of Jeong to implement a circuit in which voltage levels are sensed in order to reduce a rate at which a refresh signal is oscillated. One of ordinary skill in the art would have the motivation to combine Kim and Jeong for the purpose of improving the DRAM device and maintain data integrity.
Regarding claim 17, Kim/Jeong teaches the apparatus of claim 16, further comprising: a self-refresh oscillator configured to provide pulses of a self-refresh signal, (Kim, FIG. 5, “a first oscillator”; [0049]:“The first oscillator 121_2 may generate the self-period signal SOSC with a pulse…”) wherein the refresh control circuit configured to perform refresh operation responsive to the self-refresh signal, (Jeong, “self-refresh operation”) and wherein the self-refresh rate adjustment circuit is configured to change the rate at which the self-refresh oscillator provides the pulses of the self-refresh signal. (Jeong, “[0027] In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a reference voltage generator configured to receive a self refresh enable control signal and to generate a plurality of reference voltages each having different voltage levels, and a voltage comparator configured to compare each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit, and to generate a result signal that controls a self refresh operation cycle; [0061] For example, if the temperature information voltage VTEMP expresses a temperature lower than 45° C. because the internal temperature of the integrated circuit is so low, the three flag signals TEMPA, TEMPB, and TEMPC are low-disabled. Therefore, if the self refresh operation period, which is performed by the self refresh oscillator 111, can be set to four times of a reference cycle, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high-enabled, and the self refresh operation cycle may be set to two times, one times, or 1.5 times of a reference cycle.”)
Regarding claim 19, Kim/Jeong teaches the apparatus of claim 18, wherein the system voltage is VDD and the reference voltage is VDDQ. (One of ordinary skill in the art would recognize these terms to refer to drain voltage and supply voltage to an output buffer, but clarification is required as it applies to the instant claims. Jeong appears to teach wherein the system voltage (“temperature voltage”) can serve as VDD and the reference voltage (“reference voltage”) can serve as VDDQ.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim, et al., hereinafter Kim) in view of US 20100061160 A1 (Jeong) in view of 20040114446 A1 (Takahashi, et al., hereinafter Takahashi).
Regarding claim 6, Kim/Jeong teaches the apparatus of claim 1, but does not appear to explicitly teach wherein the refresh control circuit is configured to refresh multiple word lines responsive to each pulse of the self-refresh signal.
Takahashi cures the deficiencies of Kim/Jeong. Takahashi teaches wherein the refresh control circuit (taught in Kim/Jeong; also taught in Takahashi, “refresh control circuit 7”) is configured to refresh multiple word lines responsive to each pulse of the self-refresh signal. (Takahashi, [0113]: “In addition, the memory cells of memory cell array 101 are arranged in the form of a matrix at those locations where word lines and pairs of bit lines, running in the row and column directions, respectively, intersect. Each memory cell uses a DRAM cell and so forth composed of one transistor and one capacitor. Furthermore, although the following explanation is provided on the assumption of an example of there being 4096 word lines (decimal, and this is to apply similarly to other values unless indicated otherwise), there may be any number of word lines.”)
Claim(s) 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220406367 A1 (Kim, et al., hereinafter Kim) in view of US 20100061160 A1 (Jeong) in view of 20180061483 A1 (Morgan).
Regarding claim 8, Kim/Jeong teaches the apparatus of claim 1, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to reducing the rate of the self-refresh signal.
Morgan cures the deficiencies of Kim/Jeong. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to reducing the rate of the self-refresh signal. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the subarray refresh circuits may enter into an idle state, at block 630.”)
Both Kim/Jeong and Morgan are directed to refresh circuits including systems
and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Morgan to
implement a circuit in which the alert signal of Morgan is sent in response to a reduction
in rate of a self-refresh signal as taught in Jeong. One of ordinary skill in the art
would have the motivation to combine Jeong and Morgan for the purpose of
implementing a system alert and improving versatility of the device.
Regarding claim 20, Kim/Jeong teaches the apparatus of claim 16, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to changing the rate of the pulses of the self-refresh signal.
Morgan cures the deficiencies of Kim/Jeong. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to provide an alert signal responsive to changing the rate of the pulses of the self-refresh signal. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the subarray refresh circuits may enter into an idle state, at block 630.”)
Both Jeong/Kim and Morgan are directed to refresh circuits including systems
and methods for self-refresh rate control. It would be obvious to one of ordinary skill in the art to combine the methods of Jeong/Kim and the methods of Morgan to implement a circuit in which the alert signal of Morgan is sent in response to an adjustment of rate of a self-refresh signal as taught in Jeong/Kim. One of ordinary skill in the art would have the motivation to combine Jeong/Kim and Morgan for the purpose of implementing a system alert and improving versatility of the device.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20180061483 A1 (Morgan).
Regarding claim 15, Jeong teaches the method of claim 9, but does not appear to explicitly teach further comprising sending an alert signal responsive to reducing the rate of the self-refresh operations.
Morgan cures the deficiencies of Jeong. Morgan teaches further comprising sending an alert signal responsive to reducing the rate of the self-refresh operations. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the
subarray refresh circuits may enter into an idle state, at block 630.”)
Both Jeong and Morgan are directed to refresh circuits including systems
and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Morgan to
implement a circuit in which the alert signal of Morgan is sent in response to a reduction
in rate of a self-refresh signal as taught in Jeong. One of ordinary skill in the art
would have the motivation to combine Jeong and Morgan for the purpose of
implementing a system alert and improving versatility of the device.
Allowable Subject Matter
Resolution of indefiniteness issues must be resolved before indication of allowable subject matter.
Claims 10-12 include an unclear reference to a self-refresh operation and to a self-refresh mode, and due to the recursive reference of a self-refresh operation and the self-refresh mode with claim 9, further search and consideration is required upon resolution of indefiniteness issues.
Further clarification as to the basis for claim 18 in the original disclosure is required, and further search and consideration is required before any indication of allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827