Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/16/25 has been entered.
Response to Amendment
This Office action is in response to Applicant' s communication filed 1/16/2026 in response to the Office action dated 11/20/2025. Claims 1, 7-8, 14-15, and 20 have been amended. Claims 1-20 are pending in this application.
Allowable Subject Matter
Claims 7, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and rewritten to overcome the rejection(s) under 35 U.S.C 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 7, 14, and 20 recite the limitations of (or similar thereof):
“identifying a range of the host system throughput requirement corresponding to a threshold throughput loss level; identifying a first number of valid blocks value associated with a start point of the range; identifying a second number of valid blocks value associated with an end point of the range; and determining a difference between the first number of valid blocks value and the second number of valid blocks value, wherein the grown bad blocks allowance is equal to the difference.”
Claims 7, 14, and 20 are directed towards a nonobvious improvement over the invention published in US 9766980 B1. Although the prior art also teaches a bad block allowance threshold, claims 7, 14, and 20 better align the threshold with desired performance metrics by calculating an optimal balance between throughput loss and valid block amount, improving the lifespan and quality of service of a memory device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hou et al. (US 20190286341 A1), hereinafter Hou, in view of Anantharaman et al. (US 9766980 B1), hereinafter Anantharaman.
Regarding claim 1, Hou teaches a method comprising: generating, by a processing device (Paragraph 183; Fig. 11, processor 23 manages the storage medium)
executing a model during a pre-runtime stage associated with a memory device, a first modeling of a first parameter of the memory device (Paragraphs 87-89, 97, 99-102; Figs. 3 and 4, steps S101-S102, S202, before SSD delivery [pre-runtime], calculating, using a zero-mean normalization algorithm [model], a health degree score Scorei [modeling] corresponding to an i-th health degree statistics indicator, such as RBER [first parameter]) ;
generating, by the processing device executing the model during the pre-runtime stage, a second modeling of a second parameter of the memory device (Paragraphs 87-89, 97, 99-102; Figs. 3 and 4, steps S101-S102, S202, before SSD delivery [pre-runtime], calculating, using a zero-mean normalization algorithm [model], another health degree score Scorei [modeling] which corresponds to another i-th health degree statistics indicator, such as tBERS [second parameter]);
determining, by the processing device during the pre-runtime stage associated with a memory device, a first relationship comprising the first modeling of the first parameter of the memory device and the second modeling of the second parameter of the memory device (Paragraphs 83, 87, 106; Fig. 4, step S204, before SSD delivery, testing a performance of the SSD and determining an overall health degree score Score [first relationship] based off of the weighted sum of the individual health degree scores Scorei [first and second modelings]),
wherein the first parameter corresponds to a first performance requirement associated with the memory device, and wherein the second parameter corresponds to a second performance requirement associated with the memory device (Paragraph 89; Fig. 3, the health degree statistics indicators are performance parameters of storage blocks of the storage medium).
Hou does not explicitly teach determining, during the pre-runtime stage, a grown bad block allowance based on the first relationship associated with the memory device; and storing the grown bad block allowance in a storage location associated with the memory device, wherein a controller of the memory device accesses the storage location and uses the grown bad block allowance during runtime operation of the memory device.
However, Anantharaman teaches determining, during the pre-runtime stage, a grown bad block allowance based on the first relationship associated with the memory device (Col. 5, lines 36-40; Fig. 4, steps 406, predetermining a bad block generation threshold rate 406 based off of testing storage devices (such as the first relationship which was determined by the pre-delivery performance testing of the SSD of Hou)); and
storing the grown bad block allowance in a storage location associated with the memory device (Col. 5, lines 23-54; Fig. 4, step 404, bad block generation threshold rate 406 is stored in memory since it is required in the comparing against the error rate of the storage device),
wherein a controller of the memory device accesses the storage location and uses the grown bad blocks allowance during runtime operation of the memory device (Col. 3, lines 33-42; Col. 5, lines 23-36, Fig. 4, step 404, a processor [controller] of the storage device compares current storage device error rate with the threshold rate 406 (stored and accessed in memory)).
Hou and Anantharaman are analogous art because they are in the same field of endeavor, that being storage optimization. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Hou to further include the grown bad block allowance according to the teachings of Anantharaman. The motivation for doing so would have been reduce occurrences of data unavailability and data loss by swapping storage devices based on device health (Anantharaman, Col. 2, lines 46-63).
Regarding claim 8, this is a system version of the claimed method discussed above (claim 1, respectively), in which Hou in view of Anantharaman also teaches a system comprising a memory comprising instructions (Hou, Paragraphs 183, 185-186; Fig. 11, storage device 20 includes a memory 22 which stores program code).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman.
Regarding claim 15, this is a non-transitory computer-readable storage medium version of the claimed method discussed above (claim 1, respectively), in which Hou in view of Anantharaman also teaches a non-transitory computer-readable storage medium comprising instructions (Hou, Paragraphs 183, 185-186; Fig. 11, storage device 20 includes a storage medium 21 and a memory 22 which stores program code).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman.
Claims 2-6, 9-13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Anantharaman in view of Kim et al. (US 20220283720 A1), hereinafter Kim.
Regarding claim 2, Hou in view of Anantharaman teaches the method of claim 1, wherein the first parameter comprises a host system throughput requirement associated with the memory device (Anantharaman, Col. 5, lines 36-54; Fig. 4, steps 406 and 408, threshold rate 406 may be based on host/disk scan rate [throughput])
and the second parameter (Hou, Paragraph 89; Fig. 4, step S101, performance parameters [including the second parameter]).
Hou in view of Anantharaman does not explicitly teach wherein the second parameter comprises a write amplification requirement associated with the memory device.
However, Kim teaches wherein the second parameter comprises a write amplification requirement associated with the memory device (Paragraphs 81, 89; Figs. 5A and 5B, determining memory availability based on a write amplification factor WAF).
Hou, Anantharaman and Kim are analogous art because they are in the same field of endeavor, that being storage optimization. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Hou in view of Anantharaman to further include the write amplification factor requirement according to the teachings of Kim. The motivation for doing so would have been to improve processing speed and avoid memory wear by balancing the workload based on memory conditions (Kim, Paragraphs 158-159).
Regarding claim 3, Hou in view of Anantharaman, further in view of Kim teaches the method of claim 2, wherein the host system throughput requirement (Anantharaman, Col. 5, lines 36-54, the host/disk scan rate [throughput] is an indication of read performance [media access operation workload type])
and the write amplification requirement are associated with a media access operation workload type (Kim, Paragraph 81, write amplification factor WAF is determined based on the relative size of write operations [media access operation workload type]).
Regarding claim 4, Hou in view of Anantharaman teaches the method of claim 2, the first relationship (Hou, Paragraphs 89, 101, 106; Figs. 3 and 4, steps S101, S202, S204, determining an overall health degree score Score [first relationship] based on health degree statistics indicators RBER and tBERS),
determining, during the pre-runtime stage, based on the first relationship, a third relationship associated with the memory device (Hou, Paragraphs 87, 89, 103, 106; Figs. 3 and 4, steps S101, S202, S204, before SSD delivery, determining, by a second manner, an overall health degree score Score [third relationship] based on health degree statistics indicators RBER, tBERS, P/E, read retry count, ECC count, and other health indicators), and
wherein the grown bad block allowance is determined based on the third relationship (Anantharaman, Col. 5, lines 36-40; Fig. 4, steps 406, predetermining a bad block generation threshold rate 406 based off of testing storage devices (such as the third relationship which was determined by the pre-delivery performance testing of the SSD of Hou)).
Hou in view of Anantharaman does not explicitly teach a second relationship and determining the second relationship associated with the memory device.
However, Kim teaches a second relationship and determining the second relationship associated with the memory device (Paragraphs 51, 115-116; Fig. 9, determining memory availability includes factors such as a valid page [block] count VPC and a write amplification factor WAF [second relationship] of the corresponding memory region).
Hou, Anantharaman and Kim are analogous art because they are in the same field of endeavor, that being storage optimization. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Hou in view of Anantharaman to further include the second relationship according to the teachings of Kim. The motivation for doing so would have been to improve processing speed and avoid memory wear by balancing the workload based on memory conditions (Kim, Paragraphs 158-159).
Regarding claim 5, Hou in view of Anantharaman, further in view of Kim teaches the method of claim 4, wherein the second relationship comprises a second modeling of the write amplification requirement (Kim, Paragraphs 115-116, 127; Fig. 9, determining memory availability includes a write amplification factor WAF threshold value),
and a number of valid blocks requirement associated with the memory device (Kim, Paragraphs 51, 115-116, 121; Fig. 9, determining memory availability also includes a valid page [block] count VPC maximum value).
Regarding claim 6, Hou in view of Anantharaman, further in view of Kim teaches the method of claim 5, wherein the third relationship comprises a third modeling of the host system throughput requirement associated with the memory device (Anantharaman, Col. 5, lines 36-54; Fig. 4, steps 406 and 408, threshold rate 406 may be based on the host/disk scan rate [throughput] and other relevant factors),
and the number of valid blocks requirement associated with the memory device (Kim, Paragraphs 51, 116, 121; Fig. 9, determining memory availability includes factors such as a maximum valid page [block] count VPC value).
Regarding claim 9, this is a system version of the claimed method discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 10, this is a system version of the claimed method discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 11, this is a system version of the claimed method discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 12, this is a system version of the claimed method discussed above (claim 5, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 13, this is a system version of the claimed method discussed above (claim 6, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 16, this is a non-transitory computer-readable storage medium version of the claimed method discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 17, this is a non-transitory computer-readable storage medium version of the claimed method discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 18, this is a non-transitory computer-readable storage medium version of the claimed method discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Hou in view of Anantharaman, further in view of Kim.
Regarding claim 19, Hou in view of Anantharaman, further in view of Kim teaches the non-transitory computer-readable storage medium of claim 18, wherein the second relationship comprises a second modeling of the write amplification requirement (Kim, Paragraphs 116, 127; Fig. 9, determining memory availability includes a write amplification factor WAF threshold value)
and a number of valid blocks requirement associated with the memory device (Kim, Paragraphs 51, 116, 121; Fig. 9, determining memory availability also includes a valid page [block] count VPC maximum value); and
wherein the third relationship comprises a third modeling of the host system throughput requirement associated with the memory device (Anantharaman, Col. 5, lines 36-54; Fig. 4, steps 406 and 408, threshold rate 406 may be based on the host/disk scan rate and other relevant factors),
and the number of valid blocks requirement associated with the memory device (Kim, Paragraphs 51, 116, 121; Fig. 9, determining memory availability includes factors such as a maximum valid page [block] count VPC value).
Response to Arguments
Applicant’s arguments (see pages 9-12 of the remarks) filed 1/16/26 with respect to the rejections of claims 1-20 under 35 U.S.C 101 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant’s arguments (see pages 12-13 of the remarks) filed 1/16/25 with respect to the rejections of claims 1, 8, and 15 under 35 U.S.C 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hou and Anantharaman.
Applicant’s arguments (see pages 13-14 of the remarks) filed 1/16/25 with respect to the rejections of claims 2-6, 9-13, and 16-19 under 35 U.S.C 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hou, Anantharaman, and Kim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
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supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137