Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5)
because they include the following reference character(s) not mentioned in the
description: FIG. 1: 124. Corrected drawing sheets in compliance with 37 CFR
1.121(d), or amendment to the specification to add the reference character(s) in the
description in compliance with 37 CFR 1.121(b) are required in reply to the Office action
to avoid abandonment of the application. Any amended replacement drawing sheet
should include all of the figures appearing on the immediate prior version of the sheet,
even if only one figure is being amended. Each drawing sheet submitted after the filing
date of an application must be labeled in the top margin as either “Replacement Sheet”
or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the
examiner, the applicant will be notified and informed of any required corrective action in
the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to
determine the presence of all possible minor errors. Applicant’s cooperation is
requested in correcting any errors of which applicant may become aware in the
specification.
Claim Objections
Claim 15 is objected to because of the following informalities: the claim seems to be missing “and” between the second-to-last and last claim element (“during a self-refresh mode; and a self-refresh rate adjustment circuit…”).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20100061160 A1 (Jeong).
Regarding claim 8, Jeong teaches a method (Jeong, FIG. 1-4) comprising: measuring a temperature of a memory device; (Jeong, [0009]: “The temperature voltage generator 101 senses an internal temperature of an integrated circuit and generates a temperature information voltage VTEMP...”) comparing the temperature to a threshold during a self-refresh mode of the memory device; and reducing a self-refresh rate during the self-refresh mode if the temperature crosses the threshold. (Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”; as the temperature rises above a threshold, or temperature region, the rate of self-refresh is reduced)
Regarding claim 9, Jeong teaches the method of claim 8, further comprising reducing the self-refresh rate if the temperature becomes greater than the threshold. (Jeong sets forth further reducing the self-refresh rate as the temperature continues increasing, for example, Jeong, [0061]: “the self refresh operation cycle may be set to two times, one times, or 1.5 times of a reference cycle.”)
Regarding claim 10, Jeong teaches the method of claim 8, further comprising: periodically updating a value of a temperature signal; and comparing the temperature signal to the threshold when the temperature signal is updated. (Jeong, [0030]: “a temperature sensor for sensing an internal temperature of the integrated circuit”; no specific period is set forth by “periodically”, and the temperature sensor of Jeong provides periodic updates of the temperature reading)
Regarding claim 11, Jeong teaches the method of claim 8, further comprising reducing the self-refresh rate by increasing a period of a self-refresh signal. (Jeong, [0057]: “ for example. FIG. 3 shows the transmitter 309 generating three flag signals TEMPA, TEMPB, and TEMPC. The plurality of generated flag signals TEMPA, TEMPB, and TEMPC are used to control a self refresh operation period. It will be described in detail later with reference to FIGS. 4 and 7…”)
Regarding claim 12, Jeong teaches the method of claim 8, further comprising entering the self-refresh mode responsive to the temperature crossing a second threshold which is below the first threshold. (Jeong, “self refresh operation cycle”; including [0070]: “FIG. 6 shows the selector 603 generating three reference voltages VREFA_TS, VREFB_TS, and VREFC_TS for controlling a self refresh operation cycle and a trimming voltage VTRIM_TS for trimming the three reference voltages.”)
Regarding claim 13, Jeong teaches the method of claim 8, further comprising reducing the self-refresh rate from a first rate to a second rate if the temperature crosses the threshold. (Jeong provides for at least three thresholds: “Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”)
Regarding claim 14, Jeong teaches the method of claim 13, further comprising keeping the self-refresh rate at the second rate until the temperature crosses a second threshold which is below the first threshold. (Jeong provides for at least three thresholds: “Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”; as the temperature rises above a threshold, the rate of self-refresh is reduced)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20220406367 A1 (Kim, et al., hereinafter Kim).
Regarding claim 1, Jeong teaches an apparatus (Jeong, FIG. 1-4) comprising: a self-refresh oscillator circuit (Jeong, “self refresh oscillator”) configured to provide a self-refresh signal at a rate; (Jeong, [0031]: “configured to control the self refresh operation cycle based on the plurality of result signals.”); a temperature sensor configured to measure a temperature of the apparatus; (Jeong, [0009]: “The temperature voltage generator 101 senses an internal temperature of an integrated circuit and generates a temperature information voltage VTEMP”) and a self-refresh rate adjustment circuit configured to reduce the rate of the self-refresh signal if the temperature rises above a threshold. (Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”; as the temperature rises above a threshold, the rate of self-refresh is reduced)
Jeong does not appear to explicitly teach a refresh control circuit configured to perform at least one refresh operation responsive to the self-refresh signal.
Kim cures the deficiencies of Jeong. Kim teaches a refresh control circuit (Kim, [0004]: “refresh control circuit”) configured to perform at least one refresh operation (“self-refresh operation”) responsive to the self-refresh signal. (Kim, [0038]: “self-refresh signal SRET”)
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on
device factors such as device/supply voltage. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Kim to implement a
circuit in which temperature levels are sensed in order to reduce a rate at which a refresh signal is oscillated. One of ordinary skill in the art would have the motivation to combine Jeong and Kim for the purpose of improving the memory device and maintaining data integrity.
Regarding claim 2, Jeong/Kim teaches the apparatus of claim 1, wherein the temperature sensor is configured to periodically update a value of a temperature signal based on the measured temperature, (Jeong, [0030]: “a temperature sensor for sensing an internal temperature of the integrated circuit”; no specific period is set forth by “periodically”, and the temperature sensor of Jeong provides periodic updates of the temperature reading) and wherein the self-refresh adjustment circuit compares the temperature signal to the threshold. (Jeong provides several embodiments, for example, “[0056] The voltage comparator 307 compares the temperature voltage VTEMP generated by the temperature sensor 301 with the four reference voltage and the trimming voltage VREFA_TS, VREFB_TS, VREFC_TS, and VTRIM_TS, and outputs a comparison result signal. FIG. 3 shows the voltage comparator 307 generating three comparison result signals TEMPAI, TEMPBI, and TEMPCI…[0063] The temperature information voltage is in inverse proportion to the internal temperature of the integrated circuit. The reference voltages VREFA_TS, VREFB_TS, and VREFC_TS, and the trimming voltage VTRIM_TS may be internal temperatures T|TEMPA, T|TEMPB, T|TEMPC, and T|TEMP—TRIM of the integrated circuit, for example, 45° C., 65° C., 85° C., and 93° C.”)
Regarding claim 4, Jeong/Kim teaches the apparatus of claim 1, wherein the self-refresh rate adjustment circuit is configured to compare the temperature to a second threshold which is lower than the threshold and to increase the rate of the self-refresh signal if the temperature falls below the second threshold. (Jeong provides for at least three thresholds: “Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”; as the temperature rises above a threshold, the rate of self-refresh is reduced)
Regarding claim 5, Jeong/Kim teaches the apparatus of claim 1, wherein the refresh control circuit is configured to generate a refresh address responsive to the self-refresh signal. (Jeong, [0003]: “The auto refresh operation and the self refresh operation are identical in a view that an address is internally generated in the refresh operation…”)
Regarding claim 7, Jeong/Kim teaches the apparatus of claim 1, wherein the self-refresh rate adjustment circuit is configured to reduce the rate by changing a period at which the self-refresh oscillator circuit provides the self-refresh signal from a first period to a second period which is longer than the first period. (Jeong, [0077]: “As described above, the comparison results TEMPAI, TEMPBI, and TEMPCI indicate one of four temperature regions where the internal temperature of the integrated circuit belongs to. Therefore, all or some of the flag signals TEMPA, TEMPB, and TEMPC are high enabled or low disabled according to the internal temperature of the integrated circuit. Therefore, the self refresh oscillator 111 controls the self refresh cycle to four times, two times, one times, or 0.5 times of a refresh cycle based on the flag signals TEMPA, TEMPB, and TEMPC.”)
Regarding claim 15, Jeong teaches an apparatus (Jeong, FIG. 1-4) comprising: a temperature sensor configured to measure a temperature; (Jeong, [0009]: “The temperature voltage generator 101 senses an internal temperature of an integrated circuit and generates a temperature information voltage VTEMP”); a self-refresh rate adjustment circuit configured to adjust the rate of self-refresh operations from a first rate to a second rate which is lower than the first rate responsive to the temperature crossing a threshold. (Jeong, FIG. 4, also [0060]: “For example, the self refresh operation cycle is differently decided according to four temperature regions distinguished by the internal temperatures of the integrated circuit, which are expressed by T|TEMPA, T|TEMPB, and T|TEMPC. For example, the internal temperatures T|TEMPA, T|TEMPB, and T|TEMPC may be 45° C., 65° C., and 85° C., respectively, and correspond to three flag signals TEMPA, TEMPB, and TEMPC that are transferred from the transmitter 309 to the self refresh oscillator 111.”; as the temperature rises above a threshold, the rate of self-refresh is reduced)
Jeong does not appear to teach a refresh control circuit configured to periodically perform self-refresh operations at a rate during a self-refresh mode.
Kim cures the deficiencies of Jeong. Kim teaches a refresh control circuit (Kim, [0004]: “refresh control circuit”) configured to periodically perform self-refresh operations (“self-refresh operation”) at a rate during a self-refresh mode. (Kim, [0164], “When the auto refresh signal AREF is input 4 times in the auto refresh period AUTO REFRESH PERIOD, an internal refresh signal IREF may be generated 6 times in the self-refresh period SELF REFRESH PERIOD.”; Kim provides for other rates of self-refresh operations…)
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on
device factors such as device/supply voltage. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Kim to implement a
circuit in which temperature levels are sensed in order to adjust a rate at which a refresh signal is oscillated. One of ordinary skill in the art would have the motivation to combine Jeong and Kim for the purpose of improving the memory device and maintaining data integrity.
Regarding claim 16, Jeong/Kim teaches the apparatus of claim 15, further comprising a self-refresh oscillator circuit (Jeong, “self refresh oscillator”) configured to periodically provide a self-refresh signal, (Jeong, [0031]: “configured to control the self refresh operation cycle based on the plurality of result signals.”)
Jeong does not appear to explicitly teach wherein the refresh control circuit is configured to perform one or more refresh operations responsive to the self-refresh signal.
Kim cures the deficiencies of Jeong. Kim teaches a refresh control circuit (Kim, [0004]: “refresh control circuit”) configured to perform at least one refresh operation (“self-refresh operation”) responsive to the self-refresh signal. (Kim, [0038]: “self-refresh signal SRET”)
Jeong and Kim are both directed to a circuit for adjusting a refresh rate based on
device factors such as device/supply voltage. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong and the methods of Kim to implement a
circuit in which temperature levels are sensed in order to adjust a rate at which a refresh signal is oscillated. One of ordinary skill in the art would have the motivation to combine Jeong and Kim for the purpose of improving the memory device and maintaining data integrity.
Regarding claim 17, Jeong/Kim teaches the apparatus of claim 16, wherein the refresh control circuit is configured to perform one or more normal refresh operations responsive to the self-refresh signal. (Jeong, [0074]: “In a normal mode, the comparator receives the reference voltage VREFC_TS for controlling the self refresh operation cycle. When it is required to trim the plurality of reference voltages, for example, in a test mode, the comparator receives the trimming voltage VTRIM_TS for trimming the plurality of reference voltages.”)
Regarding claim 18, Jeong/Kim teaches the apparatus of claim 15, wherein the apparatus is placed into the self-refresh mode responsive to the temperature crossing a second threshold which is lower than the first threshold. (Jeong, “self refresh operation cycle”; including [0070]: “FIG. 6 shows the selector 603 generating three reference voltages VREFA_TS, VREFB_TS, and VREFC_TS for controlling a self refresh operation cycle and a trimming voltage VTRIM_TS for trimming the three reference voltages.”)
Regarding claim 19, Jeong/Kim teaches the apparatus of claim 15, wherein the temperature sensor is configured to periodically update a temperature signal based on the temperature, (Jeong, “a temperature sensor for sensing an internal temperature of the integrated circuit”; no specific period is set forth by “periodically”, and the temperature sensor of Jeong provides periodic updates of the temperature reading) and wherein the self-refresh rate adjustment circuit includes a threshold comparator configured to compare the temperature signal to the threshold. (Jeong, [0027]: “and a voltage comparator configured to compare each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit, and to generate a result signal that controls a self refresh operation cycle.”)
Claim(s) 3 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20220406367 A1 (Kim, et al., hereinafter Kim) in view of US 20180061483 A1 (Morgan).
Regarding claim 3, Jeong/Kim teaches the apparatus of claim 1, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to send an alert signal responsive to reducing the rate of the self-refresh signal.
Morgan cures the deficiencies of Jeong/Kim. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to send an alert signal responsive to reducing the rate of the self-refresh signal. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the subarray refresh circuits may enter into an idle state, at block 630.”)
Both Jeong/Kim and Morgan are directed to refresh circuits including systems and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong/Kim and the methods of Morgan to implement a circuit in which the alert signal of Morgan is sent in response to a reduction in rate of a self-refresh signal as taught in Jeong/Kim. One of ordinary skill in the art would have the motivation to combine Jeong/Kim and Morgan for the purpose of implementing a system alert and improving versatility of the device.
Regarding claim 20, Jeong/Kim teaches the apparatus of claim 15, but does not appear to explicitly teach wherein the self-refresh rate adjustment circuit is configured to provide an alert responsive to adjusting the rate of the self-refresh operations from the first rate to the second rate.
Morgan cures the deficiencies of Jeong/Kim. Morgan teaches wherein the self-refresh rate adjustment circuit is configured to provide an alert responsive to adjusting the rate of the self-refresh operations from the first rate to the second rate. (Morgan, [0041]: “ If the high threshold has been reached by any of the subarray refresh circuits, at block 625, a refresh alert may be raised to a memory controller, requesting that a refresh command be issued. In some embodiments, the refresh command may be a global refresh command across one or more ranks, a per-bank refresh command, or a refresh command for a subset of banks in one or more ranks. If no refresh status count reaches the high threshold, the subarray refresh circuits may enter into an idle state, at block 630.”)
Both Jeong/Kim and Morgan are directed to refresh circuits including systems and methods for self-refresh rate control. It would be obvious to one of ordinary
skill in the art to combine the methods of Jeong/Kim and the methods of Morgan to implement a circuit in which the alert signal of Morgan is sent in response to an adjustment of rate of a self-refresh signal as taught in Jeong/Kim. One of ordinary skill in the art would have the motivation to combine Jeong/Kim and Morgan for the purpose of implementing a system alert and improving versatility of the device.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100061160 A1 (Jeong) in view of US 20220406367 A1 (Kim, et al., hereinafter Kim) in view of US 20040114446 A1 (Takahashi, et al., hereinafter Takahashi).
Regarding claim 6, Jeong/Kim teaches the apparatus of claim 5, but does not appear to explicitly teach wherein the refresh address specifies more than one word line.
Takahashi cures the deficiencies of Jeong/Kim. Takahaski teaches wherein the refresh address specifies more than one word line. (Takahashi, [0113]: “In addition, the memory cells of memory cell array 101 are arranged in the form of a matrix at those locations where word lines and pairs of bit lines, running in the row and column directions, respectively, intersect. Each memory cell uses a DRAM cell and so forth composed of one transistor and one capacitor. Furthermore, although the following explanation is provided on the assumption of an example of there being 4096 word lines (decimal, and this is to apply similarly to other values unless indicated otherwise), there may be any number of word lines.”)
Both Jeong/Kim and Takahashi are relating to methods and systems including memory systems. It would be obvious to one of ordinary skill in the art to combine the methods of Jeong/Kim and the methods of Takahashi to include a refresh address applying to more than one word line. Although Jeong/Kim does not appear to explicitly mention more than one word line, one of ordinary skill in the art would have the motivation to add the refresh address specifying more than one word line of Takahashi as an obvious modification and with the motivation of increasing utility of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827