Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are pending in the application.
Election/Restrictions
Applicant’s election without traverse of Group 1 (claims 1-8) is acknowledged.
Therefore, claims 9-20 are withdrawn from further consideration.
Since the applicant makes an election without traverse of Group 1 (claims 1-
8). Therefore, the arguments is not needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Antonyan (US 20210383844 A1).
Regarding claim 1: Antonyan discloses a memory device for calibrating a variable reference resistor (10), comprising: a memory cell array (11) including a plurality of memory cells (Mi and Ri), the memory cell array divided into a first region (Mi) and a second region (Ri); a sensing circuit (13) configured to determine data stored in memory cells of the first region (par. 30) based on a reference resistance (REF, par. 30); and a mismatch correction circuit (19, par. 21) configured to shift a value of the reference resistance depending on a temperature (15, par. 33) and to adjust the shifted value of the reference resistance based on at least one of a value of a magnetic tunnel junction (MTJ) resistance of the memory cell array (MTJ, par. 25) and a leakage current (par. 53) of the memory cell array, wherein the second region is configured to store a value (desired resistance, par. 31) of the reference resistance for distinguishing a parallel state and an anti-parallel state (par. 31, Fig. 5) of a memory cell where the data are stored.
Regarding claim 2: Antonyan discloses a memory device for calibrating a variable reference resistor wherein the value of the MTJ resistance of the memory cell array is obtained based on a resistance distribution (diagram of temperature characteristic of resistance for MTJ, pars. 50-51, FIG. 5) of the memory cell array programmed at a reference temperature (RREF of MTJ at different temperatures, FIG. 5).
Regarding claim 3: Antonyan discloses a memory device for calibrating a variable reference resistor, wherein the leakage current is based on a leakage current flowing to a memory cell, which is not targeted for a read operation or a program operation (leakage current through non-selected memory cells, par. 53), from among memory cells connected to one bit line (…from bit line BL, par. 53).
Regarding claim 4: Antonyan discloses a memory device for calibrating a variable reference resistor, further comprising: a leakage current detector configured to detect the leakage current (device compensates for deviation in leakage circuit occurring at high temperatures after detection, par. 82).
Regarding claim 7: Antonyan discloses a memory device for calibrating a variable reference resistor, wherein each of the plurality of memory cells (Mi, FIG. 1) includes: a cell transistor (MT) including a first end connected to a source line (the variable resistance element MTJ and the memory cell transistor MT may be connected in series between the source line SL and the bit line BL in an order different from that as shown in FIG. 1, par. 25), and a gate electrode connected to a word line (gate of cell transistor MT connected to word line WLi, FIG. 1); and a magnetic tunneling junction element (MTJ) including a first end connected to a second end of the cell transistor (magnetic tunneling junction MTJ connected to MT, FIG. 1) and a second end connected to a bit line (the variable resistance element MTJ and the memory cell transistor MT may be connected in series between the source line SL and the bit line BL in an order different from that as shown in FIG. 1, par. 25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Antonyan (US 20210383844 A1) in view of Kim (US 20220328085 A1).
Regarding claim 5: Antonyan does not disclose a memory device, wherein the sensing circuit includes: a first current source configured to generate a first read current; a second current source configured to generate a second read current; and a sense amplifier configured to amplify a difference between a first voltage drop at a first node and a second voltage drop at a second node, the first voltage drop in response to the first read current being applied to a first bit line connected to a selected memory cell, the second voltage drop at a second node in response to the second read current being applied to a reference bit line.
Kim does disclose a memory device including a magnetic storage element (100), wherein the sensing circuit (sensing circuit 150, FIG. 12) includes: a first current source configured to generate a first read current (current source generating first read current IRD1, FIG. 12); a second current source configured to generate a second read current (current source generating second read current IRD2, FIG. 12); and a sense amplifier (sense amplifier 152 SA, FIG. 12) configured to amplify a difference between a first voltage drop at a first node and a second voltage drop at a second node (sense amplifier senses and amplifies a sensed voltage difference between a voltage drop of a first node N1 and a second voltage drop of a second node N2, par. 93, FIG. 12), the first voltage drop in response to the first read current being applied to a first bit line connected to a selected memory cell (The first read current IRD1 may be used to sense a voltage drop in the selected memory cell of the first bit line BL1, par. 91), the second voltage drop at a second node in response to the second read current being applied to a reference bit line (The second read current IRD2 may be used to determine a voltage drop in a second node N2 through a reference bit line Rref BL, par. 92).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read circuit of Antonyan with the configuration of Kim to allow the circuit to help read and determine the data from the memory cell.
Regarding claim 6: Antonyan does not disclose a memory device, further comprising: a voltage generator configured to generate a code value; and a write driver configured to perform a program operation on the first region based on the code value, and wherein the write driver includes, first-type transistors each including a first end connected to a first power supply voltage and a second end connected to an output node, and second-type transistors each including a first end connected to a second power supply voltage and a second end connected to the output node.
Kim does disclose a memory device including a magnetic storage element (100), further comprising: a voltage generator (182, FIG. 14) configured to generate a code value (voltage generator may generate a code value CV, par. 108); and a write driver (140, FIG. 14) configured to perform a program operation on the first region based on the code value (write driver performs pre-program operation on memory cells based on code value CV, par. 86), and wherein the write driver includes, first-type transistors (transistors PU1-PU4, FIG. 15) each including a first end connected to a first power supply voltage (VDD, FIG. 15) and a second end connected to an output node (node between PU and PD transistors which connects to MTJ, FIG. 15), and second-type transistors (transistors PD1-PD4, FIG. 15) each including a first end connected to a second power supply voltage (VSS, FIG. 15) and a second end connected to the output node (node between PU and PD transistors which connects to MTJ, FIG. 15).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Antonyan with the configuration of Kim to allow the system to interact with and program the cells of the array to parallel or anti-parallel before operation, aiding in storing the write data.
Regarding claim 8: Antonyan does not disclose a memory device, wherein the second region has anti-fuse cell array.
Kim does disclose a memory device including a magnetic storage element (100), wherein the second region has anti-fuse cell array (par. 44 and 141).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Antonyan with the configuration of Kim to allow the device to write information about the device to be programmed for operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/HOAI V HO/Primary Examiner, Art Unit 2827