DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henze et al. (U.S. PGPub No. 2022/0035566) in view of Seroff et al. (U.S. PGPub No. 2013/0138868).
Claim 1
Henze (2022/0035566) teaches:
A memory device comprising: a first plane group and a second plane group; and […] FIG. 3 each die contains at least two planes (plane group); FIG. 1 plurality of dies 154
Henze does not explicitly teach first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group
Seroff (2013/0138868) teaches:
[…] a first plane group and a second plane group; and FIG. 4 Memory Dies 1-1 and 1-2 (plane groups)
a multiplexer circuit coupled to a first input/output (I/O) interface and a second I/O interface, the multiplexer circuit to perform operations comprising: FIG. 5 Internal Channel MUX 524 coupled to internal interfaces 511a-n; FIG. 7 memory channel MUXs 740-746 provide communication between a host and NVM dies using external channels 716 a-b and internal channels 726 a-b
enabling the first I/O interface to access the first plane group and the second plane group, and enabling the second I/O interface to access the first plane group and the second plane group. P. 0044 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Henze with the first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group taught by Seroff
The motivation being to achieve point-to-point communication between a host and one or more memory dies (see Seroff P. 0005)
The systems of Henze and Seroff are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Henze with Seroff to obtain the invention as recited in claims 1-8.
Claim 2
Seroff (2013/0138868) teaches:
The memory device of claim 1, further comprising a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. P. 0044 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
The rationale to combine Henze with Seroff for claim 1 equally applies for dependent claim 2.
Claim 3
Henze (2022/0035566) teaches:
The memory device of claim 1, the operations further comprising: receiving a first command to execute a first memory access operation associated with at least a portion of the first plane group; and receiving a second command to execute a second memory access operation associated with at least a portion of the second plane group. P. 0019 commands can be carried out in parallel if the required resource sets do not overlap (e.g., commands to different dies on different channels); FIG. 3 each die contains at least two planes (plane group)
Claim 4
Henze (2022/0035566) teaches:
The memory device of claim 3, wherein the first memory access operation and the second memory access operation are executed concurrently. P. 0019 commands can be carried out in parallel if the required resource sets do not overlap (e.g., commands to different dies on different channels); FIG. 4 and P. 0034 parallel data transfer operations via a plural number M channels 156, one die can be accessed by each channel at a time
Claim 5
Seroff (2013/0138868) teaches:
The memory device of claim 3, the operations further comprising: enabling, via the first I/O interface, a first access to the at least the portion of the first plane group to execute the first memory access operation; and enabling, via the second I/O interface, a second access to the at least the portion of the second plane group to execute the second memory access operation. P. 0036 use internal channel MUX 342 to activate a number of internal interfaces (thereby switching between internal communications channels 326 a-p to access memory dies 312 a-p; P. 0044 each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
The rationale to combine Henze with Seroff for claim 1 equally applies for dependent claim 5.
Claim 6
Henze (2022/0035566) teaches:
The memory device of claim 5, wherein the first access by the first I/O interface to the first plane group and second access by the second I/O interface to the second plane group are performed concurrently. P. 0019 commands can be carried out in parallel if the required resource sets do not overlap (e.g., commands to different dies on different channels)
Claim 7
Seroff (2013/0138868) teaches:
The memory device of claim 1, wherein the second I/O interface is deactivated. P. 0039 Each memory controller may adjust the number of active external interfaces that an associated NVM package uses; P. 0050 memory controller 706 can deactivate external interface 710 a
The rationale to combine Henze with Seroff for claim 1 equally applies for dependent claim 7.
Claim 8
Seroff (2013/0138868) teaches:
The memory device of claim 6, wherein one or more commands are transmitted to the second plane group via the first I/O interface. P. 0050 and FIG. 7 memory controller 706 can deactivate external interface 710 a, such that external interface 710b [first I/O interface] handles all communications. Signals received through external interface 710 b can then be processed in processor(s) 720 a or processor(s) 720 b based on a selection made by memory channel MUX 742; P. 0053 and pair each external interface with a single internal communications channel
The rationale to combine Henze with Seroff for claim 1 equally applies for dependent claim 8.
Claim 9
Henze (2022/0035566) teaches:
[…] a first plane group and a second plane group of the memory device […] FIG. 3 each die contains at least two planes (plane group); FIG. 1 plurality of dies 154
Henze does not explicitly teach first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group.
Seroff (2013/0138868) teaches:
A method comprising: enabling, by a multiplexer circuit coupled to a first input/output (I/O) interface and a second I/O interface of a memory device, FIG. 5 Internal Channel MUX 524 coupled to internal interfaces 511a-n; FIG. 7 memory channel MUXs 740-746 provide communication between a host and NVM dies using external channels 716 a-b and internal channels 726 a-b
the first I/O interface to access a first plane group and a second plane group of the memory device; and enabling, by the multiplexer circuit, the second I/O interface to access the first plane group and the second plane group of the memory device. P. 0044 and FIG. 5 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Henze with the first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group taught by Seroff
The motivation being to achieve point-to-point communication between a host and one or more memory dies (see Seroff P. 0005)
The systems of Henze and Seroff are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Henze with Seroff to obtain the invention as recited in claims 9-14.
Claim 10
Seroff (2013/0138868) teaches:
The method of claim 9, further comprising receiving, from a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel, a first command to execute a first memory access operation associated with at least a portion of the first plane group. P. 0044 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
Claim 11
Seroff (2013/0138868) teaches:
The method of claim 10, further comprising receiving, from the controller, a second command to execute a second memory access operation associated with at least a portion of the second plane group. P. 0044 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
Claim 12
Henze (2022/0035566) teaches:
The method of claim 11, wherein the first memory access operation and the second memory access operation are executed concurrently. P. 0019 commands can be carried out in parallel if the required resource sets do not overlap (e.g., commands to different dies on different channels); FIG. 4 and P. 0034 parallel data transfer operations via a plural number M channels 156, one die can be accessed by each channel at a time
Claim 13
Seroff (2013/0138868) teaches:
The method of claim 9, wherein the second I/O interface is deactivated. P. 0050 and FIG. 7 memory controller 706 can deactivate external interface 710a
Claim 14
Seroff (2013/0138868) teaches:
The method of claim 13, wherein one or more commands are transmitted to the second plane group via the first I/O interface. P. 0050 and FIG. 7 memory controller 706 can deactivate external interface 710a, such that external interface 710b handles all communications with a connected host device
Claim 15
Henze (2022/0035566) teaches:
A memory sub-system comprising: a first memory device comprising a first plane group, a second plane group, […] FIG. 3 each die contains at least two planes (plane group); FIG. 1 plurality of dies 154
Henze does not explicitly teach first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group.
Seroff (2013/0138868) teaches:
[…] a first plane group, a second plane group, FIG. 4 Memory Dies 1-1 and 1-2 (plane groups)
a multiplexer circuit, FIG. 5 Internal Channel MUX 524
a first I/O interface and a second I/O interface; and FIG. 5 internal interfaces 511a-n
control logic, operatively coupled with the first I/O interface via a first channel and the second I/O interface via a second channel, to perform one or more operations comprising: FIG. 5 Processor(s) 520 coupled to Internal Channel MUX 524
transmitting, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane group, P. 0043 and FIG. 5 External interface 510 coupled to processor(s) 520, can carry out access requests received from a host device
wherein the multiplexer circuit enables the first I/O interface to access the first plane group and the second plane group. P. 0044 internal channel MUX 542 can select one of internal interfaces 511a-p to receive incoming signals from one or more NVMs over internal communications channels 526a-p, each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Henze with the first and second I/O interfaces coupled to a multiplexer, each I/O interface able to access either plane group taught by Seroff
The motivation being to achieve point-to-point communication between a host and one or more memory dies (see Seroff P. 0005)
The systems of Henze and Seroff are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Henze with Seroff to obtain the invention as recited in claims 15-20.
Claim 16
Seroff (2013/0138868) teaches:
The memory sub-system of claim 15, the one or more operations further comprise transmitting, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane group, wherein the multiplexer circuit enables the second I/O interface to access the first plane group and the second plane group. P. 0036 use internal channel MUX 342 to activate a number of internal interfaces (thereby switching between internal communications channels 326 a-p to access memory dies 312 a-p; P. 0044 each internal communications channel 526a-p may be an internal bus that can communicate with more than one memory die
Claim 17
Seroff (2013/0138868) teaches:
The memory sub-system of claim 16, the one or more operations further comprising: activating the first I/O interface; and activating the second I/O interface. P. 0036 use internal channel MUX 342 to activate a number of internal interfaces
Claim 18
Seroff (2013/0138868) teaches:
The memory sub-system of claim 17, the one or more operations further comprising: deactivating the second I/O interface, wherein the first I/O interface accesses the first plane group and the second plane group to perform one or more memory access operations. P. 0050 and FIG. 7 memory controller 706 can deactivate external interface 710a, such that external interface 710b handles all communications with a connected host device
Claim 19
Seroff (2013/0138868) teaches:
The memory sub-system of claim 16, further comprising a second memory device comprising a third plane group and a fourth plane group. FIG. 3 and P. 0034 there are n number of NVM Packages 304a-n, each package containing p memory dies (plane groups)
Claim 20
Seroff (2013/0138868) teaches:
The memory sub-system of claim 19, the one or more operations further comprising transmitting one or more commands associated with the third plane group and the fourth plane group of the second memory device. FIG. 5 Memory controller (e.g. the memory controller in NVM Package 2 304b in FIG. 3) includes processor(s) 520 coupled to Internal Channel MUX 524; P. 0043 and FIG. 5 External interface 510 coupled to processor(s) 520, can carry out access requests received from a host device
Response to Arguments
Applicant's arguments filed 12/8/2025 have been fully considered but they are not persuasive.
The applicant states “the MUX 542 in Seroff does not control or enable access by the
interfaces of Seroff and memory plane groups of a memory die. Instead, Seroff’s MUX 542 is configured to "route one external communications channel (e.g., external communications channel 516) to one of several internal communications channels." (Seroff, paragraph [0044]). Seroff does not teach or suggest a multiplexer within a memory device which enables each I/O interface to access multiple different plane groups (e.g., a first plane group and a second plane group) of the memory device. The relied upon portions of Seroff fail to teach or suggest a memory device including a multiplexer circuit that controls access between multiple different interfaces and multiple different memory planes. Instead, Seroff's MUX 542 provides for channel selection, not cross-plane group access.”
The examiner respectfully notes the internal interfaces 511a-n of Seroff FIG. 5 are analogous to the claimed first and second I/O interfaces. The applicant highlighted one embodiment of FIG. 5, in which the internal interfaces Seroff P. 0044 states:
Internal channel MUX 542 can be any component suitable to route one external communications channel (e.g., external communications channel 516) to one of several internal communications channels. For example, internal channel MUX 542 can be a multiplexer/de-multiplexer. Functioning as a de-multiplexer, internal channel MUX 542 can route outgoing signals over a selected one of internal interfaces 511 a-p and internal communications channels 526 a-p. Functioning as a multiplexer, internal channel MUX 542 can select one of internal interfaces 511 a-p to receive incoming signals from one or more NVMs over internal communications channels 526 a-p. According to some embodiments, each one of internal communications channels 526 a-p can couple memory controller 506 to a single NVM memory die (e.g., one of memory dies 312 a-p of FIG. 3) to provide direct point-to-point connection between a host device and each memory die in a system. In other embodiments, each internal communications channel 526 a-p may be an internal bus that can communicate with more than one memory die.
The highlighted portions of the paragraph explicitly teach a single internal communications channel being able to communicate with more than one memory die (mapped to plane group), and an internal interface 511a-p (mapped to I/O interface) may be coupled to any of internal communications channels 526a-p to access more than one NVM (also referred to as NVM die 312 in other portions of the paragraph). The paragraph clearly describes an embodiment where an internal interface may access more than one NVM die via one or more of the internal communications channels. The applicant has chosen to focus on a different embodiment of FIG. 5 in their remarks, without addressing alternative embodiments described in Seroff FIG. 5 and P. 0044. This does not discredit the embodiment relied upon to teach the multiplexer circuit and I/O interfaces in the claims, in which each of the internal interfaces 511a-p may access more than one NVM die 312.
FIG. 7 was also cited, which shows both internal 726a-b and external 716a-b channels, either of which are analogous to the claimed I/O interfaces. Paragraphs 0049-50 describe alternative routing paths to any of the NVM dies by a single external interface.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ji et al. (U.S. PGPub No. 2020/0363955) teaches each die including at least two planes, where different memory dies corresponding to different channels may process operations corresponding to different commands independently, or in parallel.
Vittal Prabhu et al. (U.S. PGPub No. 2022/0415380) teaches a NAND die with a plurality of planes, where reads can be concurrently conducted on multiple plane groups in a single die.
Stolowitz et al. (U.S. PGPub No. 2004/0264309) which teaches a switch that allows the plurality of logical ports on a controller to access any of the disk drives
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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