Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 sets forth “patterning the first continuous free layer, the first continuous tunnel barrier layer, the first continuous reference layer, the continuous magnetic polarizer layer using the first pillar structures and the tubular dielectric spacers to form first magnetic tunnel junctions having a smaller horizontal area than the second tunnel junctions.” For purposes of compact prosecution, this is being interpreted as “patterning the first continuous free layer, the first continuous tunnel barrier layer, the first continuous reference layer, and the continuous magnetic polarizer layer using the first pillar structures and the tubular dielectric spacers to form first magnetic tunnel junctions having a smaller horizontal area than the second tunnel junctions.”
Appropriate clarification is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-9 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 sets forth “the first antiparallel state” and “the second antiparallel state”. Although claim 2 sets forth “a first fixed magnetization direction that is antiparallel to the hard magnetization direction”, and “a second fixed magnetization direction that is antiparallel to the hard magnetization direction”, and claim 3 sets forth “a first antiparallel state resistance” and “a second antiparallel state resistance”, these claims, upon which claim 4 depends, do not provide proper antecedent basis for “the first antiparallel state” and “the second antiparallel state”. Appropriate clarification is required.
Claims 5-9 and 19 are rejected as dependent upon claim 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-2, 11, 13, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210320245 A1 (Kalitsov, et al., hereinafter Kalitsov) in view of US 20110194338 A1 (Baek, et al., hereinafter Baek).
Regarding claim 1, Kalitsov teaches a magnetoresistive memory cell, (Kalitsov, FIG. 1-2; Kalitsov, “an array of magnetoresistive or magnetoelectric memory cells…”) comprising: a magnetic polarizer layer (Kalitsov, [0003]: “the polarizer layer, also known as a reference layer.”; [0004]: “plurality of reference layers”; [0043]: “The magnetic tunnel junction 140 includes a reference layer 132 (which may also be referred to as a “pinned” layer) having a fixed vertical magnetization, a nonmagnetic tunnel barrier layer 134, and the free layer 136 (which may also be referred to as a “storage” layer) having a magnetization direction that can be programmed.”) having a hard magnetization along a hard magnetization direction; (Kalitsov, [0139]: “In one embodiment, the reference layer 132 may be provided as a component within a synthetic antiferromagnetic structure (SAF structure) 120. The SAF structure 120 can include a hard (i.e., fixed) ferromagnetic layer 112 with fixed magnetization along a vertical direction,”) a first magnetic tunnel junction (Kalitsov, “magnetic tunnel junction 140”) located on a first side of the magnetic polarizer layer and comprising a first reference layer having a first side facing the magnetic polarizer layer, (Kalitsov, FIG. 1) a first free layer facing a second side of the first reference layer, (Kalitsov, “the free layer 136.”) and a first tunnel barrier layer located between the first free layer and the first reference layer; (Kalitsov, FIG. 14-18, including FIG. 15; Kalitsov, [0022]: “tunnel barrier layer”) and a second magnetic tunnel junction (Kalitsov, “a magnetic tunnel junction 240”) located on a second side of the magnetic polarizer layer and comprising a second reference layer having a second side facing the magnetic polarizer layer, (Kalitsov, FIG. 1, 16; Kalitsov, [0211]: “The magnetic tunnel junction 240 can comprise, in order, a first reference layer 132, a first nonmagnetic tunnel barrier layer 134, a free layer 136, a second nonmagnetic tunnel barrier layer 234, and a second reference layer 232.”) a second free layer facing a first side of the second reference layer, (Kalitsov, [0211]: “The magnetic tunnel junction 240 can comprise, in order, a first reference layer 132, a first nonmagnetic tunnel barrier layer 134, a free layer 136, a second nonmagnetic tunnel barrier layer 234, and a second reference layer 232.”) and a second tunnel barrier layer located between the second free layer and the second reference layer, (Kalitsov, [0211]: “Generally, the eighth exemplary structure (as illustrated in FIG. 16 or as derived from any of the previously described exemplary structures) may include a memory device including: a first electrode 32, a second electrode 92, and a magnetic tunnel junction 240”; also Kalitsov, [0212]: “In some embodiments, the free layer 136 contacts the first nonmagnetic tunnel barrier 134 layer and the second nonmagnetic tunnel barrier layer 234. In some embodiments, the first nonmagnetic tunnel barrier layer 134 contacts the first reference layer 132, and the second nonmagnetic tunnel barrier layer 234 contacts the second reference layer 232.”). Kalitsov does not appear to explicitly teach wherein the magnetoresistive memory cell is configured to be programmed into three or four different memory states.
Baek cures the deficiencies of Kalitsov. Baek teaches wherein the magnetoresistive memory cell is configured to be programmed into three or four different memory states. (Baek, [0005]: “According to some embodiments of the present invention, an integrated circuit memory device may include an integrated circuit substrate, a memory cell on the integrated circuit substrate, and a controller electrically coupled to the memory cell. The memory cell may be programmable to at least two different magnetoresistive states determined by a magnetic polarization of a free magnetic layer relative to a fixed magnetic layer. The memory cell may also be programmable to at least two different resistance states determined by a resistance characteristic of a layer of a resistive memory material. Accordingly, the memory cell may provide at least four different memory states for the memory cell…. In addition, the controller may be configured to apply an electrical signal to the memory cell to discriminate between the at least four different memory states and thereby read the at least two bits of data from the memory cell.”)
Kalitsov and Baek are both directed to magnetoresistive memory devices including multi-bit memory cells including free layers and methods for making and operating the same. It would have been obvious to one of ordinary skill in the art to combine the magnetoresistive memory cell which is configured to be programmed into three or four different memory states of Baek with the magnetoresistive memory cell of Kalitsov. One of ordinary skill in the art would be motivated to combine in order to improve functionality by including multiple memory states and therefore improving efficiency of the device.
Regarding claim 2, Kalitsov/Baek teaches the magnetoresistive memory cell of claim 1, wherein: the first reference layer faces the first side of the magnetic polarizer layer, is antiferromagnetically coupled to the magnetic polarizer layer, and has a first fixed magnetization direction that is antiparallel to the hard magnetization direction; (Kalitsov, [0047]: “In one embodiment, the reference layer 132 may be provided as a component within a synthetic antiferromagnetic structure (SAF structure) 120. The SAF structure 120 can include a hard (i.e., fixed) ferromagnetic layer 112 with fixed magnetization along a vertical direction, an antiferromagnetic coupling layer 114, and the reference layer 132 which remains adjacent to the nonmagnetic tunnel barrier layer 134. “) and the second reference layer faces the second side of the magnetic polarizer layer, antiferromagnetically coupled to the magnetic polarizer layer, and has a second fixed magnetization direction that is antiparallel to the hard magnetization direction. (Kalitsov, including FIG. 16-19; “second reference layer 232; Kalitsov, [0005]: “In one embodiment, the plurality of reference layers comprise a first reference layer and a second reference layer, and the at least one free layer is located between the first reference layer and the second reference layer.”; [0208]: “ second reference layer 232 between the free layer 136 and a material layer that directly overlies, and contacts, a top surface of the free layer 136. In this case, the second nonmagnetic tunnel barrier layer 234 contacts a top surface of the free layer 136, and the second reference layer 232 contacts a top surface of the second nonmagnetic tunnel barrier layer 234. In one embodiment, the second reference layer 132 may be provided as a component within a second synthetic antiferromagnetic structure (SAF structure)….”)
Regarding claim 11, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 1, wherein: the first free layer has a first area in a horizontal plane; and the second free layer has a second area less than the first area in the horizontal plane. wherein the second lateral dimension is less than the first lateral dimension. (Kalitsov, [0030]: “Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layer thereupon, thereabove, and/or therebelow.”; Kalitsov, FIG. 1-5)
Regarding claim 13, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 1, wherein: the first free layer has a first thickness; and the second free layer has a second thickness different than the first thickness. (Kalitsov, [0048]: “ The thickness of the free layer 136 can be in a range from 0.5 nm to 2 nm, although lesser and greater thicknesses can also be employed.”; Kalitsov, [0224]: “Each of the first free layer 136 and the second free layer 236 may have any material composition that may be employed for the free layer 136 in previously described embodiments. Each of the first free layer 136 and the second free layer 236 may have the same thickness range as the free layer 136 in previously described embodiments.”)
Regarding claim 15, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 1, wherein the magnetic polarizer layer comprises a hard magnet layer. (Kalitsov, [0047]: “In one embodiment, the reference layer 132 may be provided as a component within a synthetic antiferromagnetic structure (SAF structure) 120. The SAF structure 120 can include a hard (i.e., fixed) ferromagnetic layer 112 with fixed magnetization along a vertical direction,”)
Regarding claim 16, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 1, wherein: the first reference layer underlies the magnetic polarizer layer; the first free layer underlies the first reference layer; the second reference layer overlies the magnetic polarizer layer; and the second free layer overlies the second reference layer. (Kalitsov, FIG. 1, 16; [0030]: “As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure.”)
Regarding claim 17, Kalitsov/Baek teaches a method of operating the magnetoresistive memory cell of Claim 1, comprising programming the magnetoresistive memory cell into the three or the four different memory states. (Baek, [0005]: “According to some embodiments of the present invention, an integrated circuit memory device may include an integrated circuit substrate, a memory cell on the integrated circuit substrate, and a controller electrically coupled to the memory cell. The memory cell may be programmable to at least two different magnetoresistive states determined by a magnetic polarization of a free magnetic layer relative to a fixed magnetic layer. The memory cell may also be programmable to at least two different resistance states determined by a resistance characteristic of a layer of a resistive memory material. Accordingly, the memory cell may provide at least four different memory states for the memory cell…. In addition, the controller may be configured to apply an electrical signal to the memory cell to discriminate between the at least four different memory states and thereby read the at least two bits of data from the memory cell.”)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210320245 A1 (Kalitsov, et al., hereinafter Kalitsov) in view of US 20110194338 A1 (Baek, et al., hereinafter Baek) in view of US 20230292528 A1 (Katine, et al., hereinafter Katine).
Regarding claim 12, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 11, but does not teach wherein the magnetoresistive memory cell further comprises a tubular dielectric spacer laterally surrounding and contacting the second magnetic tunnel junction and not contacting the first magnetic tunnel junction.
Katine cures the deficiencies of Kalitsov/Baek. Katine teaches wherein the magnetoresistive memory cell further comprises a tubular dielectric spacer laterally surrounding and contacting the second magnetic tunnel junction and not contacting the first magnetic tunnel junction. (Katine, [0096]: “magnetoresistive memory device in which sidewalls of magnetic tunnel junctions 130 are protected by tubular dielectric spacers; [0077]: “Remaining portions of the dielectric spacer material layer after 178L after anisotropically etching the dielectric spacer material layer 178L comprise a two-dimensional array of tubular dielectric spacers 178 laterally surrounding the two-dimensional array of MTJ pillar structures 184.”; [0082]: “In one embodiment, the second cylindrical surface segment CSS2 is laterally offset inward from the cylindrical vertical plane including the first cylindrical surface segment CSS1 by a uniform lateral offset distance that equals a lateral thickness of each tubular dielectric spacer 178 of the two-dimensional array of tubular dielectric spacers 178. In one embodiment, the second cylindrical surface segment CSS2 is in contact with a portion of an inner sidewall of a respective one of the tubular dielectric spacers 178, and the base portion 153B comprises the annular top surface ATS contacting an annular bottom surface of the respective one of the tubular dielectric spacers 178. In one embodiment, the tubular dielectric spacer 178 does not contact the entire respective selector-containing pillar structure 182. In one embodiment, the tubular dielectric spacer 178 does not contact the non-Ohmic selector material plate 152 and/or the lower selector electrode 151 of the underlying selector-containing pillar structure 182.”)
Kalitsov/Baek and Katine are both directed to magnetoresistive memory devices including multi-bit memory cells including free layers and methods for making and operating the same. It would have been obvious to one of ordinary skill in the art to combine the tubular dielectric spacer which is configured to surround and contact the second tunnel junction without contacting the first tunnel junction of Katine with Kalitsov/Baek. One of ordinary skill in the art would be motivated to combine in order to provide insulation and separation between materials and therefore improve functionality of the device.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210320245 A1 (Kalitsov, et al., hereinafter Kalitsov) in view of US 20110194338 A1 (Baek, et al., hereinafter Baek) in view of US 20090201720 (Lim).
Regarding claim 14, Kalitsov/Baek teaches the magnetoresistive memory cell of Claim 1, but does not teach wherein: the first free layer has a magnetic damping coefficient; and the second free layer has a second magnetic damping coefficient different than the second magnetic damping coefficient.
Lim cures the deficiencies of Kalitsov/Baek. Lim teaches wherein: the first free layer has a magnetic damping coefficient; and the second free layer has a second magnetic damping coefficient different than the second magnetic damping coefficient. (Lim, FIG. 1-2; [0096, “In addition, the magnetic layers M1, M2 of the invention may have the same or differing spin precession frequencies. Also the magnetic layers M1, M2 may have the same or differing magnetic damping constants to provide for better energy dissipation, as needed.”)
Kalitsov/Baek and Lim are both directed to magnetoresistive memory devices including multi-bit memory cells including free layers and methods for making and operating the same. It would have been obvious to one of ordinary skill in the art to combine the first free layer including a magnetic damping coefficient and the second free layer having a second magnetic damping coefficient with Kalitsov/Baek. One of ordinary skill in the art would be motivated to combine in order to improve functionality of the device.
Allowable Subject Matter
Claims 3, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record does not teach a magnetoresistive memory cell, comprising: a magnetic polarizer layer having a hard magnetization along a hard magnetization direction; a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and comprising a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer; and a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and comprising a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer, wherein the magnetoresistive memory cell is configured to be programmed into three or four different memory states, wherein: the first reference layer faces the first side of the magnetic polarizer layer, is antiferromagnetically coupled to the magnetic polarizer layer, and has a first fixed magnetization direction that is antiparallel to the hard magnetization direction; and the second reference layer faces the second side of the magnetic polarizer layer, antiferromagnetically coupled to the magnetic polarizer layer, and has a second fixed magnetization direction that is antiparallel to the hard magnetization direction, wherein: the first magnetic tunnel junction has a first parallel state resistance when a magnetization direction of the first free layer is parallel to the first fixed magnetization direction; the second magnetic tunnel junction has a second parallel state resistance when a magnetization direction of the second free layer is parallel to the second fixed magnetization direction; the second parallel state resistance is different from the first parallel state resistance; the first magnetic tunnel junction has a first antiparallel state resistance when the magnetization direction of the first free layer is antiparallel to the first fixed magnetization direction; the second magnetic tunnel junction has a second antiparallel state resistance when the magnetization direction of the second free layer is antiparallel to the second fixed magnetization direction; and a sum of the first antiparallel state resistance and the second parallel state resistance is different from a sum of the first parallel state resistance and the second antiparallel state resistance.
Regarding claim 10, the prior art of record does not teach the magnetoresistive memory cell of Claim 1, wherein the magnetoresistive memory cell further comprises: a selector element; a first antiferromagnetic coupling layer located between the magnetic polarizer layer and the first reference layer and providing the antiferromagnetic coupling therebetween; and a second antiferromagnetic coupling layer located between the magnetic polarizer layer and the second reference layer and providing the antiferromagnetic coupling therebetween. Although Kalitsov teaches a first antiferromagnetic coupling layer and a second antiferromagnetic coupling layer, the prior art of record does not teach each of the limitations of claim 10.
Regarding claim 18, the prior art of record does not teach a magnetoresistive memory cell, comprising: a magnetic polarizer layer having a hard magnetization along a hard magnetization direction; a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and comprising a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer; and a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and comprising a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer, wherein the magnetoresistive memory cell is configured to be programmed into three or four different memory states, comprising programming the magnetoresistive memory cell into the three or the four different memory states, wherein the programming the magnetoresistive memory cell into three or four different memory states comprises the four memory states selected from a first memory state in which the first magnetic tunnel junction is in a first parallel state and the second magnetic tunnel junction is in a second parallel state; a second memory state in which the first magnetic tunnel junction is in a first antiparallel state and the second magnetic tunnel junction is in the second parallel state; a third memory state in which the first magnetic tunnel junction is in the first parallel state and the second magnetic tunnel junction is in a second antiparallel state; or a fourth memory state in which the first magnetic tunnel junction is in the first antiparallel state and the second magnetic tunnel junction is in the second antiparallel state.
Claims 4-9 and 19 are rejected for indefiniteness issues. Clarification of indefiniteness issues is required before indication of allowability, and further search and consideration is required upon resolution of indefiniteness issues.
Claim 20 is objected to for informalities. However, the subject matter of claim 20, including a method of forming a magnetoresistive memory device, comprising: forming a layer stack comprising, in order from bottom to top, a first continuous free layer, a first continuous tunnel barrier layer, a first continuous reference layer, a continuous magnetic polarizer layer, a second continuous reference layer, a second continuous tunnel barrier layer, and a second continuous free layer; patterning the second continuous free layer, the second continuous tunnel barrier layer, and the second continuous reference layer into first pillar structures comprising second magnetic tunnel junctions; forming tubular dielectric spacers around the first pillar structures; and patterning the first continuous free layer, the first continuous tunnel barrier layer, the first continuous reference layer, the continuous magnetic polarizer layer using the first pillar structures and the tubular dielectric spacers to form first magnetic tunnel junctions having a smaller horizontal area than the second tunnel junctions, is not taught by the prior art of record.
Conclusion
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827